182 lines
5.2 KiB
C
182 lines
5.2 KiB
C
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#ifndef _HW_WAR_H_
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#define _HW_WAR_H_
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#include "iot_config.h"
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/* define which level would make SW ASSERT when abnormal HW behavior */
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#define PLC_HW_ISSUE_ASSERT_ALL 0
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#define PLC_HW_ISSUE_ASSERT_DEBUG 1
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#define PLC_HW_ISSUE_ASSERT_CRITICAL 3
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#define PLC_HW_ISSUE_ASSERT_BLOCK 5
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#define PLC_HW_ISSUE_ASSERT_LEVEL PLC_HW_ISSUE_ASSERT_DEBUG
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/******************hw war macro******************/
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#ifndef ENA_WAR_421_DEBUG
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#define ENA_WAR_421_DEBUG 1
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#endif
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/* MAC HW overwrite WAR */
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#define ENA_WAR_396 0
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#define ENA_WAR_396_DEBUG 1
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/* sack war */
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#define ENA_WAR_244 0
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/*rawdata mode write fl war*/
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#define ENA_WAR_325 0
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#if SUPPORT_SOUTHERN_POWER_GRID
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#define ENA_WAR_NSG_EXTMI 0
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#define ENA_WAR_SPG_TX_OK 0
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#endif
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#define ENA_SYNC_DIFF_CCO_PPM (((PLC_SUPPORT_CCO_ROLE == 0) \
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|| MAC_MM_SNIFFER_MODE) \
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&& IOT_MP_SUPPORT)
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/* kl2 war for tx ppm
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* kl3 add the function of tx nn ppm
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*/
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#define ENA_HW_SYNC_PPM_WAR (0)
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/* tx ppm per pkt */
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#define ENA_DBG_TX_PPM_PER_PKT (ENA_SYNC_DIFF_CCO_PPM)
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/* kl3 mac rx mpdu complete dsr enable bb rx ppm
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* 0 enable
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* 1 disable
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*/
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#define ENA_RX_BB_PPM 0
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/* nncco war */
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#if PLC_SUPPORT_NEIGHBOR_NW_NEGO
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#define ENA_WAR_NNCCO_FEAT 0
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#else
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#define ENA_WAR_NNCCO_FEAT 0
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#endif
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#ifndef ENA_WAR_440
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#define ENA_WAR_440 0
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#endif
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//war for timeout tx abort
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#define WAR_TIMEOUT_TX_ABORT 0
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#define MAC_WAR_244_TIMESTAMPING 0
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/* war for rx desc not complete for the whole mpdu
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* SW pop buf from ring for wr idx update
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* and check the rx_pb_done, once it's set,
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* SW thought HW has complete the whole buf
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* but HW maybe complete when multi-pb case
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* the rx_mpdu_done may update after rx_pb_done
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* this would make SW think it's an error case
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* enable the following macro to force SW
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* wait first pb's attention desc to be rx_mpdu_done
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* set, if not, SW would keep waiting and hang
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*/
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#define MAC_RX_RING_WAIT_MPDU_DONE 0
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/* kl3 no need the war, should be 0 */
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#define MAC_WAR_SPLIT_TX_RX_RIFS 0
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/* debug tx abort for kl3 */
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#define DEG_TX_ABORT 1
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/*enable hwretry bcast
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*hwretry and sw retry can not both enable
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*/
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#ifndef MAC_BCAST_HWRETRY_ENABLE
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#define MAC_BCAST_HWRETRY_ENABLE 1
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#endif
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/* enable mac rawdata tx start intr for kl2 */
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#define ENA_WAR_CTL 1
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/* for WAR MAC HW overwrite issue */
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#if !defined(MAC_HW_WAR_RESV_BYTES)
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#define MAC_HW_WAR_RESV_BYTES (0)
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#endif
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#if !defined(MAC_HW_WAR_SPG_RESV_SHORT_BYTES)
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#define MAC_HW_WAR_SPG_RESV_SHORT_BYTES (0)
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#endif
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#ifndef DEBUG_NID_ERR
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#define DEBUG_NID_ERR (0)
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#endif
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/* SW SYNC NTB, low 32 bit overflow, high 32 bit not + 1*/
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#ifndef ENA_WAR_911
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#define ENA_WAR_911 (0)
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#endif
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/* define high32bit ntb equal 1 */
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#ifndef ENA_HIGH32_EQUAL_ONE
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#define ENA_HIGH32_EQUAL_ONE (!ENA_WAR_911)
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#endif
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#ifndef WAR_BUGID757_EN
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/* master and role is cco to debug */
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#define WAR_BUGID757_EN (1)
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#endif
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/* kl3 hw bug, rf csma only one hwq can be enabled */
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#ifndef ENA_RF_ONLY_ONE_CSMA_HWQ
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#define ENA_RF_ONLY_ONE_CSMA_HWQ (HPLC_RF_DEV_SUPPORT && 0)
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#endif
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/* kl3 hw bug, 4 hwq war */
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#ifndef ENA_RF_MULTI_CSMA_HWQ_WAR
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#define ENA_RF_MULTI_CSMA_HWQ_WAR (HPLC_RF_DEV_SUPPORT && \
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(!ENA_RF_ONLY_ONE_CSMA_HWQ))
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#endif
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/* kl3 hw bug, after tx abort happend, mpdu cannot goto next mpdu */
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#ifndef ENA_RF_FORCE_RESET_HWQ
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#define ENA_RF_FORCE_RESET_HWQ (HPLC_RF_DEV_SUPPORT && 1)
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#endif
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/* kl3 csma beacon use one hwq */
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#ifndef ENA_RF_CSMA_BCN_HWQ
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#define ENA_RF_CSMA_BCN_HWQ (!ENA_RF_ONLY_ONE_CSMA_HWQ)
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#endif
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/* tx raw int */
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#ifndef ENA_TX_RAW_INT
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#define ENA_TX_RAW_INT (1)
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#endif
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#if (ENA_TX_RAW_INT && ENABLE_CCA_ISR == 1)
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#error "ENA_TX_RAW_INT and ENABLE_CCA_ISR cannot be valid at the same time!"
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#endif
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/* rf special config for hplc2rf cert test */
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#ifndef ENA_RF_CERT_SPECIAL_CFG
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#define ENA_RF_CERT_SPECIAL_CFG (HPLC_RF_DEV_SUPPORT && 1)
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#endif
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/* war for low power mode */
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#define WAR_FOR_LOW_POWER 1
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/* reset tx fd fsm when tx td done. fix tx sof pb crc error after tx nncco */
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#define ENA_WAR_TX_TD_DONE_RST_TX_FD 1
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#endif
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