2540 lines
89 KiB
C
2540 lines
89 KiB
C
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//-----------------------------------
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#define CFG_MAC_RTL_VERSION_ADDR 0x0000
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#define RO_MAC_RTL_VERSION_OFFSET 0
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#define RO_MAC_RTL_VERSION_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_MAC_TRX_START_ADDR 0x0004
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#define CFG_MAC_TX_LOCK_EN_OFFSET 2
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#define CFG_MAC_TX_LOCK_EN_MASK 0x00000004
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#define CFG_MAC_TRX_START_TRIG_OFFSET 1
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#define CFG_MAC_TRX_START_TRIG_MASK 0x00000002
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#define CFG_MAC_TRX_START_NEED_TRIG_OFFSET 0
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#define CFG_MAC_TRX_START_NEED_TRIG_MASK 0x00000001
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//-----------------------------------
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#define CFG_GP_TX_SACKI_FORCE0_ADDR 0x0008
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#define CFG_TX_SACKI_FORCE_VAL0_OFFSET 0
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#define CFG_TX_SACKI_FORCE_VAL0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GP_TX_SACKI_FORCE1_ADDR 0x000C
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#define CFG_TX_SACKI_FORCE_VAL1_OFFSET 0
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#define CFG_TX_SACKI_FORCE_VAL1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GP_TX_SACK_FORCE_ADDR 0x0010
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#define CFG_TX_SACKT_FORCE_VAL_OFFSET 2
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#define CFG_TX_SACKT_FORCE_VAL_MASK 0x000003FC
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#define CFG_TX_SACKT_FORCE_EN_OFFSET 1
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#define CFG_TX_SACKT_FORCE_EN_MASK 0x00000002
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#define CFG_TX_SACKI_FORCE_EN_OFFSET 0
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#define CFG_TX_SACKI_FORCE_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_NTB_LOCAL_GAP_ADDR 0x0014
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#define NTB_LOCAL_GAP_OFFSET 0
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#define NTB_LOCAL_GAP_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_ICG_SW_FORCE_ADDR 0x0018
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#define CFG_TX_PB_CG_FORCE_ON_OFFSET 9
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#define CFG_TX_PB_CG_FORCE_ON_MASK 0x00000200
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#define CFG_TX_FC_CG_FORCE_ON_OFFSET 8
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#define CFG_TX_FC_CG_FORCE_ON_MASK 0x00000100
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#define CFG_TX_VEC_CG_FORCE_ON_OFFSET 7
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#define CFG_TX_VEC_CG_FORCE_ON_MASK 0x00000080
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#define CFG_BUF_RING_CG_FORCE_ON_OFFSET 6
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#define CFG_BUF_RING_CG_FORCE_ON_MASK 0x00000040
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#define CFG_RX_PPB_CG_FORCE_ON_OFFSET 5
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#define CFG_RX_PPB_CG_FORCE_ON_MASK 0x00000020
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#define CFG_RX_PB_CG_FORCE_ON_OFFSET 4
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#define CFG_RX_PB_CG_FORCE_ON_MASK 0x00000010
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#define CFG_RX_FC_CG_FORCE_ON_OFFSET 3
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#define CFG_RX_FC_CG_FORCE_ON_MASK 0x00000008
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#define CFG_RX_VEC_CG_FORCE_ON_OFFSET 2
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#define CFG_RX_VEC_CG_FORCE_ON_MASK 0x00000004
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#define CFG_AHB_MASTER_ICG_FORCE_ON_OFFSET 1
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#define CFG_AHB_MASTER_ICG_FORCE_ON_MASK 0x00000002
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#define CFG_ICG_FORCE_ON_OFFSET 0
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#define CFG_ICG_FORCE_ON_MASK 0x00000001
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//-----------------------------------
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#define CFG_RO_NTB_SW_SYNC_VAL_ADDR 0x001C
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#define NTB_SW_SYNC_VAL_OFFSET 0
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#define NTB_SW_SYNC_VAL_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_RO_NTB_HW_SYNC_VAL_ADDR 0x0020
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#define NTB_HW_SYNC_VAL_OFFSET 0
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#define NTB_HW_SYNC_VAL_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_MAC_DBG_CTRL0_ADDR 0x0024
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#define CFG_DBG_LOCK_EN_OFFSET 18
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#define CFG_DBG_LOCK_EN_MASK 0x00040000
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#define CFG_MAC_BUS_LOCK_SEL_OFFSET 2
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#define CFG_MAC_BUS_LOCK_SEL_MASK 0x0003FFFC
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#define CFG_MAC_DBG_USE_TRIG_LATCH_OFFSET 1
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#define CFG_MAC_DBG_USE_TRIG_LATCH_MASK 0x00000002
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#define CFG_MAC_DBG_SEL_OFFSET 0
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#define CFG_MAC_DBG_SEL_MASK 0x00000001
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//-----------------------------------
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#define CFG_MAC_DBG_CTRL1_ADDR 0x0028
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#define CFG_MAC_DBG_DLY_AFTER_TRIG_OFFSET 18
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#define CFG_MAC_DBG_DLY_AFTER_TRIG_MASK 0xFFFC0000
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#define CFG_MAC_DBG_TRIG_SEL_OFFSET 13
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#define CFG_MAC_DBG_TRIG_SEL_MASK 0x0003E000
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#define RO_REG_TEST_OFFSET 12
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#define RO_REG_TEST_MASK 0x00001000
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#define CFG_MAC_DBG_BUS_SEL_OFFSET 0
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#define CFG_MAC_DBG_BUS_SEL_MASK 0x00000FFF
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//-----------------------------------
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#define CFG_MAC_DBG_BUS_ADDR 0x002C
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#define MAC_DBG_BUS_OFFSET 0
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#define MAC_DBG_BUS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_TX_DBG_CTRL_ADDR 0x0030
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#define CFG_POSSIBLE_UNDERFLOW_CYCLE_CNT_OFFSET 16
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#define CFG_POSSIBLE_UNDERFLOW_CYCLE_CNT_MASK 0xFFFF0000
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#define RO_TX_FIFO_UNDERFLOW_OFFSET 7
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#define RO_TX_FIFO_UNDERFLOW_MASK 0x00000080
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#define POSSIBLE_UNDERFLOW_OFFSET 6
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#define POSSIBLE_UNDERFLOW_MASK 0x00000040
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#define CFG_TX_FIFO_UNDERFLOW_CLR_OFFSET 5
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#define CFG_TX_FIFO_UNDERFLOW_CLR_MASK 0x00000020
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#define CFG_PHY_TX_ABORT_DBG_CNT_CLR_OFFSET 4
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#define CFG_PHY_TX_ABORT_DBG_CNT_CLR_MASK 0x00000010
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#define CFG_TX_BYPASS_CCA_OFFSET 2
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#define CFG_TX_BYPASS_CCA_MASK 0x00000004
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#define CFG_TX_BYPASS_PHY_OFFSET 1
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#define CFG_TX_BYPASS_PHY_MASK 0x00000002
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#define CFG_TX_DBG_CNT_CLR_OFFSET 0
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#define CFG_TX_DBG_CNT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_TX_DBG_CNT_ADDR 0x0034
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#define DBG_TX_CNT_OFFSET 16
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#define DBG_TX_CNT_MASK 0xFFFF0000
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#define PHY_TX_ABORT_DBG_CNT_OFFSET 0
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#define PHY_TX_ABORT_DBG_CNT_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_RD_LOCAL_TMR_ADDR 0x0038
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#define LOCAL_TMR_OFFSET 0
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#define LOCAL_TMR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_MYNID_ADDR 0x003C
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#define CFG_MYNID_OFFSET 0
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#define CFG_MYNID_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_MYSTAT_ADDR 0x0040
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#define CROSS_CMD_TX_CNT_OFFSET 4
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#define CROSS_CMD_TX_CNT_MASK 0x000FFFF0
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#define CROSS_CMD_TX_CLR_OFFSET 3
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#define CROSS_CMD_TX_CLR_MASK 0x00000008
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#define CFG_CCO_MODE_OFFSET 2
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#define CFG_CCO_MODE_MASK 0x00000004
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#define CFG_AUTHENTICATED_OFFSET 1
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#define CFG_AUTHENTICATED_MASK 0x00000002
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#define CFG_ASSOCIATED_OFFSET 0
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#define CFG_ASSOCIATED_MASK 0x00000001
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//-----------------------------------
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#define CFG_MAC_SEC_ADDR 0x0044
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#define CFG_RX_INIT_VEC_ENDIAN_CTRL_OFFSET 24
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#define CFG_RX_INIT_VEC_ENDIAN_CTRL_MASK 0x7F000000
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#define CFG_TX_INIT_VEC_ENDIAN_CTRL_OFFSET 16
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#define CFG_TX_INIT_VEC_ENDIAN_CTRL_MASK 0x007F0000
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#define CFG_INITIAL_VEC_BUG_FIX_OFFSET 12
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#define CFG_INITIAL_VEC_BUG_FIX_MASK 0x00001000
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#define CFG_GP_INITIAL_VEC_FORCE_EN_OFFSET 11
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#define CFG_GP_INITIAL_VEC_FORCE_EN_MASK 0x00000800
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#define CFG_RX_DECRYPTION_EN_OFFSET 10
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#define CFG_RX_DECRYPTION_EN_MASK 0x00000400
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#define CFG_SEC_AES_MODE_OFFSET 9
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#define CFG_SEC_AES_MODE_MASK 0x00000200
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#define CFG_AES_ENDIAN_OFFSET 0
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#define CFG_AES_ENDIAN_MASK 0x000001FF
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//-----------------------------------
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#define CFG_BEACON_PERIOD_ADDR 0x0048
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#define CFG_BEACON_PERIOD_OFFSET 16
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#define CFG_BEACON_PERIOD_MASK 0xFFFF0000
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//-----------------------------------
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#define CFG_GP_CTRL_ADDR 0x004C
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#define CFG_GP_MFSCMDDATA_OFFSET 9
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#define CFG_GP_MFSCMDDATA_MASK 0x00000E00
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#define CFG_GP_MFSCMDMGMT_OFFSET 6
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#define CFG_GP_MFSCMDMGMT_MASK 0x000001C0
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#define CFG_GP_SACK_MFSRESPDATA_OFFSET 4
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#define CFG_GP_SACK_MFSRESPDATA_MASK 0x00000030
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#define CFG_GP_SACK_MFSRESPMGMT_OFFSET 2
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#define CFG_GP_SACK_MFSRESPMGMT_MASK 0x0000000C
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#define CFG_GP_RTS_EN_OFFSET 1
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#define CFG_GP_RTS_EN_MASK 0x00000002
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#define CFG_GP_PB_SIZE_SEL_OFFSET 0
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#define CFG_GP_PB_SIZE_SEL_MASK 0x00000001
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//-----------------------------------
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#define CFG_TMI_CTRL_ADDR 0x0050
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#define CFG_ENABLE_MAC_LOAD_TMI_OFFSET 2
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#define CFG_ENABLE_MAC_LOAD_TMI_MASK 0x00000004
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#define CFG_TONE_AMP_EN_OFFSET 1
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#define CFG_TONE_AMP_EN_MASK 0x00000002
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#define CFG_TONE_MASK_EN_OFFSET 0
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#define CFG_TONE_MASK_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_TMSK_PTR_ADDR 0x0054
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#define CFG_TONE_MASK_PTR_OFFSET 0
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#define CFG_TONE_MASK_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_TAMP_PTR_ADDR 0x0058
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#define CFG_TONE_AMP_PTR_OFFSET 0
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#define CFG_TONE_AMP_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BAND_PTR_ADDR 0x005C
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#define CFG_BAND_TBL_PTR_OFFSET 0
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#define CFG_BAND_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PRS_CTRL_ADDR 0x0060
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#define CFG_PRS_SENSE_EN_OFFSET 1
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#define CFG_PRS_SENSE_EN_MASK 0x00000002
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#define CFG_PRS_TX_EN_OFFSET 0
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#define CFG_PRS_TX_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_TX_CTRL_ADDR 0x0064
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#define CFG_PB_EXPIRE_TIMER_OFFSET 27
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#define CFG_PB_EXPIRE_TIMER_MASK 0xF8000000
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#define CFG_TX_BEACON_PLD_CRC_BY_SW_OFFSET 26
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#define CFG_TX_BEACON_PLD_CRC_BY_SW_MASK 0x04000000
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#define CFG_NEED_TX_HP10_FC_OFFSET 25
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#define CFG_NEED_TX_HP10_FC_MASK 0x02000000
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#define CFG_TX_FCNUM_OFFSET 24
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#define CFG_TX_FCNUM_MASK 0x01000000
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#define CFG_SG_STA_LOADING_OFFSET 16
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#define CFG_SG_STA_LOADING_MASK 0x00FF0000
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#define CFG_SG_SACK_VER_OFFSET 12
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#define CFG_SG_SACK_VER_MASK 0x0000F000
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#define CFG_SG_FC_VER_OFFSET 8
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#define CFG_SG_FC_VER_MASK 0x00000F00
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#define CFG_RXWSZ_OFFSET 4
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#define CFG_RXWSZ_MASK 0x000000F0
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#define CFG_GP_BDF_OFFSET 3
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#define CFG_GP_BDF_MASK 0x00000008
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#define CFG_GP_SACK_VER_OFFSET 2
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#define CFG_GP_SACK_VER_MASK 0x00000004
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#define CFG_GP_HP10DF_OFFSET 1
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#define CFG_GP_HP10DF_MASK 0x00000002
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#define CFG_GP_HP11DF_OFFSET 0
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#define CFG_GP_HP11DF_MASK 0x00000001
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//-----------------------------------
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#define CFG_TX_CTRL1_ADDR 0x0068
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#define CFG_HWRETRY_OPT_OFFSET 11
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#define CFG_HWRETRY_OPT_MASK 0x00000800
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#define CFG_SW_TX_TRG_OFFSET 10
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#define CFG_SW_TX_TRG_MASK 0x00000400
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#define CFG_HWRETRY_MODIFY_OFFSET 9
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#define CFG_HWRETRY_MODIFY_MASK 0x00000200
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#define CFG_SG_SNR_BY_SW_OFFSET 8
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#define CFG_SG_SNR_BY_SW_MASK 0x00000100
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#define CFG_SG_SNR_OFFSET 0
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#define CFG_SG_SNR_MASK 0x000000FF
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//-----------------------------------
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#define CFG_MYTEI_ADDR 0x006C
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#define CFG_MYTEI_OFFSET 0
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#define CFG_MYTEI_MASK 0x00000FFF
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//-----------------------------------
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#define CFG_PHY_CTRL_ADDR 0x0070
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#define CFG_TX_DIVERSITY_COPY_OFFSET 3
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#define CFG_TX_DIVERSITY_COPY_MASK 0x00000008
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#define CFG_MULTI_RATE_BASE_SPEED_OFFSET 2
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#define CFG_MULTI_RATE_BASE_SPEED_MASK 0x00000004
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#define CFG_PHY_TX_LONG_PREAM_EN_OFFSET 1
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#define CFG_PHY_TX_LONG_PREAM_EN_MASK 0x00000002
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#define CFG_PHY_ALWAYS_TX_OFFSET 0
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#define CFG_PHY_ALWAYS_TX_MASK 0x00000001
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//-----------------------------------
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#define CFG_RO_NTB_TMR_WRAP_ADDR 0x0074
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#define NTB_TMR_WRAP_OFFSET 0
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#define NTB_TMR_WRAP_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_MAC_DUMMY_9_ADDR 0x0078
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//-----------------------------------
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#define CFG_VLAN0_AES_TBL_ADDR 0x0080
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#define CFG_VLAN0_AES_TBL_PTR_OFFSET 0
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#define CFG_VLAN0_AES_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN1_AES_TBL_ADDR 0x0084
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#define CFG_VLAN1_AES_TBL_PTR_OFFSET 0
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#define CFG_VLAN1_AES_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN2_AES_TBL_ADDR 0x0088
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#define CFG_VLAN2_AES_TBL_PTR_OFFSET 0
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#define CFG_VLAN2_AES_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN3_AES_TBL_ADDR 0x008C
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#define CFG_VLAN3_AES_TBL_PTR_OFFSET 0
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#define CFG_VLAN3_AES_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN4_AES_TBL_ADDR 0x0090
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#define CFG_VLAN4_AES_TBL_PTR_OFFSET 0
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#define CFG_VLAN4_AES_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN5_AES_TBL_ADDR 0x0094
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#define CFG_VLAN5_AES_TBL_PTR_OFFSET 0
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#define CFG_VLAN5_AES_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN6_AES_TBL_ADDR 0x0098
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#define CFG_VLAN6_AES_TBL_PTR_OFFSET 0
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#define CFG_VLAN6_AES_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN7_AES_TBL_ADDR 0x009C
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#define CFG_VLAN7_AES_TBL_PTR_OFFSET 0
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#define CFG_VLAN7_AES_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PHASE_BAND_SEL_ADDR 0x00A0
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#define CFG_SW_IDLE_MODE_EN_OFFSET 10
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#define CFG_SW_IDLE_MODE_EN_MASK 0x00000400
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#define CFG_SW_IDLE_MODE_OFFSET 9
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#define CFG_SW_IDLE_MODE_MASK 0x00000200
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#define CFG_SW_RX_RATE_MODE_EN_OFFSET 8
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#define CFG_SW_RX_RATE_MODE_EN_MASK 0x00000100
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#define CFG_SW_RX_RATE_MODE_OFFSET 5
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#define CFG_SW_RX_RATE_MODE_MASK 0x000000E0
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#define CFG_SW_NARROWBAND_EN_OFFSET 4
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#define CFG_SW_NARROWBAND_EN_MASK 0x00000010
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#define CFG_SW_NARROWBAND_OFFSET 3
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#define CFG_SW_NARROWBAND_MASK 0x00000008
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#define CFG_SW_PHASE_EN_OFFSET 2
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#define CFG_SW_PHASE_EN_MASK 0x00000004
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#define CFG_SW_PHASE_OFFSET 0
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#define CFG_SW_PHASE_MASK 0x00000003
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//-----------------------------------
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#define CFG_BEACON_ADDR 0x00A4
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#define CFG_BCN_ALERT_AHEAD_OFFSET 0
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#define CFG_BCN_ALERT_AHEAD_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BCN_START_NTB_ADDR 0x00A8
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#define CFG_BEACON_START_NTB_OFFSET 0
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#define CFG_BEACON_START_NTB_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_MAC_DUMMY17_ADDR 0x00AC
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#define CFG_DUMMY0_OFFSET 0
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#define CFG_DUMMY0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BCN_MISS_MAX_NUM_ADDR 0x00B0
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#define CFG_BCN_MISS_MAX_NUM_OFFSET 0
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#define CFG_BCN_MISS_MAX_NUM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_INT_ENA_MASK_ADDR 0x00B4
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#define CFG_INT_ENABLE_MASK_OFFSET 0
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#define CFG_INT_ENABLE_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_PRI0_MASK_ADDR 0x00B8
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#define CFG_INT_PRI0_MASK_OFFSET 0
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#define CFG_INT_PRI0_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_PRI1_MASK_ADDR 0x00BC
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#define CFG_INT_PRI1_MASK_OFFSET 0
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#define CFG_INT_PRI1_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_PRI2_MASK_ADDR 0x00C0
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#define CFG_INT_PRI2_MASK_OFFSET 0
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#define CFG_INT_PRI2_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_PRI3_MASK_ADDR 0x00C4
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#define CFG_INT_PRI3_MASK_OFFSET 0
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#define CFG_INT_PRI3_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_MAC_INT_STS_ADDR 0x00C8
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#define MAC_INT_STATUS_OFFSET 0
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#define MAC_INT_STATUS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_MAC_INT_CLR_ADDR 0x00CC
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#define MAC_INT_CLR_31_OFFSET 31
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#define MAC_INT_CLR_31_MASK 0x80000000
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#define MAC_INT_CLR_30_OFFSET 30
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#define MAC_INT_CLR_30_MASK 0x40000000
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#define MAC_INT_CLR_29_OFFSET 29
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#define MAC_INT_CLR_29_MASK 0x20000000
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#define MAC_INT_CLR_28_OFFSET 28
|
|
#define MAC_INT_CLR_28_MASK 0x10000000
|
|
#define MAC_INT_CLR_27_OFFSET 27
|
|
#define MAC_INT_CLR_27_MASK 0x08000000
|
|
#define MAC_INT_CLR_26_OFFSET 26
|
|
#define MAC_INT_CLR_26_MASK 0x04000000
|
|
#define MAC_INT_CLR_25_OFFSET 25
|
|
#define MAC_INT_CLR_25_MASK 0x02000000
|
|
#define MAC_INT_CLR_24_OFFSET 24
|
|
#define MAC_INT_CLR_24_MASK 0x01000000
|
|
#define MAC_INT_CLR_23_OFFSET 23
|
|
#define MAC_INT_CLR_23_MASK 0x00800000
|
|
#define MAC_INT_CLR_22_OFFSET 22
|
|
#define MAC_INT_CLR_22_MASK 0x00400000
|
|
#define MAC_INT_CLR_21_OFFSET 21
|
|
#define MAC_INT_CLR_21_MASK 0x00200000
|
|
#define MAC_INT_CLR_20_OFFSET 20
|
|
#define MAC_INT_CLR_20_MASK 0x00100000
|
|
#define MAC_INT_CLR_19_OFFSET 19
|
|
#define MAC_INT_CLR_19_MASK 0x00080000
|
|
#define MAC_INT_CLR_18_OFFSET 18
|
|
#define MAC_INT_CLR_18_MASK 0x00040000
|
|
#define MAC_INT_CLR_17_OFFSET 17
|
|
#define MAC_INT_CLR_17_MASK 0x00020000
|
|
#define MAC_INT_CLR_16_OFFSET 16
|
|
#define MAC_INT_CLR_16_MASK 0x00010000
|
|
#define MAC_INT_CLR_15_OFFSET 15
|
|
#define MAC_INT_CLR_15_MASK 0x00008000
|
|
#define MAC_INT_CLR_14_OFFSET 14
|
|
#define MAC_INT_CLR_14_MASK 0x00004000
|
|
#define MAC_INT_CLR_13_OFFSET 13
|
|
#define MAC_INT_CLR_13_MASK 0x00002000
|
|
#define MAC_INT_CLR_12_OFFSET 12
|
|
#define MAC_INT_CLR_12_MASK 0x00001000
|
|
#define MAC_INT_CLR_11_OFFSET 11
|
|
#define MAC_INT_CLR_11_MASK 0x00000800
|
|
#define MAC_INT_CLR_10_OFFSET 10
|
|
#define MAC_INT_CLR_10_MASK 0x00000400
|
|
#define MAC_INT_CLR_9_OFFSET 9
|
|
#define MAC_INT_CLR_9_MASK 0x00000200
|
|
#define MAC_INT_CLR_8_OFFSET 8
|
|
#define MAC_INT_CLR_8_MASK 0x00000100
|
|
#define MAC_INT_CLR_7_OFFSET 7
|
|
#define MAC_INT_CLR_7_MASK 0x00000080
|
|
#define MAC_INT_CLR_6_OFFSET 6
|
|
#define MAC_INT_CLR_6_MASK 0x00000040
|
|
#define MAC_INT_CLR_5_OFFSET 5
|
|
#define MAC_INT_CLR_5_MASK 0x00000020
|
|
#define MAC_INT_CLR_4_OFFSET 4
|
|
#define MAC_INT_CLR_4_MASK 0x00000010
|
|
#define MAC_INT_CLR_3_OFFSET 3
|
|
#define MAC_INT_CLR_3_MASK 0x00000008
|
|
#define MAC_INT_CLR_2_OFFSET 2
|
|
#define MAC_INT_CLR_2_MASK 0x00000004
|
|
#define MAC_INT_CLR_1_OFFSET 1
|
|
#define MAC_INT_CLR_1_MASK 0x00000002
|
|
#define MAC_INT_CLR_0_OFFSET 0
|
|
#define MAC_INT_CLR_0_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_BTS_DLY_ADDR 0x00D0
|
|
#define CFG_TX_BTS_DELAY_SIGN_OFFSET 28
|
|
#define CFG_TX_BTS_DELAY_SIGN_MASK 0x10000000
|
|
#define CFG_TX_BTS_DELAY_OFFSET 0
|
|
#define CFG_TX_BTS_DELAY_MASK 0x0FFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_NTB_SYNC_0_ADDR 0x00D4
|
|
#define CFG_NTB_GOLDEN_GAP_OFFSET 5
|
|
#define CFG_NTB_GOLDEN_GAP_MASK 0x07FFFFE0
|
|
#define CFG_NTB_SW_SYNC_CLR_OFFSET 4
|
|
#define CFG_NTB_SW_SYNC_CLR_MASK 0x00000010
|
|
#define CFG_NTB_HW_SYNC_CLR_OFFSET 3
|
|
#define CFG_NTB_HW_SYNC_CLR_MASK 0x00000008
|
|
#define CFG_HW_NTB_SYNC_EN_OFFSET 2
|
|
#define CFG_HW_NTB_SYNC_EN_MASK 0x00000004
|
|
#define CFG_MODIFY_NTB_EN_OFFSET 1
|
|
#define CFG_MODIFY_NTB_EN_MASK 0x00000002
|
|
#define CFG_NTB_DELTA_VAL_SIGN_OFFSET 0
|
|
#define CFG_NTB_DELTA_VAL_SIGN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_NTB_SYNC_1_ADDR 0x00D8
|
|
#define CFG_NTB_DELTA_VAL_OFFSET 0
|
|
#define CFG_NTB_DELTA_VAL_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RD_NTB_ADDR 0x00DC
|
|
#define NTB_TMR_OFFSET 0
|
|
#define NTB_TMR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_NTB_GOLDEN_GAP_R0B1_ADDR 0x00e0
|
|
#define CFG_NTB_GOLDEN_GAP_R0B1_OFFSET 0
|
|
#define CFG_NTB_GOLDEN_GAP_R0B1_MASK 0x003FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_NTB_GOLDEN_GAP_R0B2_ADDR 0x00e4
|
|
#define CFG_NTB_GOLDEN_GAP_R0B2_OFFSET 0
|
|
#define CFG_NTB_GOLDEN_GAP_R0B2_MASK 0x003FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_NTB_GOLDEN_GAP_R1B0_ADDR 0x00e8
|
|
#define CFG_NTB_GOLDEN_GAP_R1B0_OFFSET 0
|
|
#define CFG_NTB_GOLDEN_GAP_R1B0_MASK 0x003FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_NTB_GOLDEN_GAP_R1B1_ADDR 0x00ec
|
|
#define CFG_NTB_GOLDEN_GAP_R1B1_OFFSET 0
|
|
#define CFG_NTB_GOLDEN_GAP_R1B1_MASK 0x003FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_NTB_GOLDEN_GAP_R1B2_ADDR 0x00f0
|
|
#define CFG_NTB_GOLDEN_GAP_R1B2_OFFSET 0
|
|
#define CFG_NTB_GOLDEN_GAP_R1B2_MASK 0x003FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_NTB_GOLDEN_GAP_R2B0_ADDR 0x00f4
|
|
#define CFG_NTB_GOLDEN_GAP_R2B0_OFFSET 0
|
|
#define CFG_NTB_GOLDEN_GAP_R2B0_MASK 0x003FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_NTB_GOLDEN_GAP_R2B1_ADDR 0x00f8
|
|
#define CFG_NTB_GOLDEN_GAP_R2B1_OFFSET 0
|
|
#define CFG_NTB_GOLDEN_GAP_R2B1_MASK 0x003FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_NTB_GOLDEN_GAP_R2B2_ADDR 0x00fc
|
|
#define CFG_NTB_GOLDEN_GAP_R2B2_OFFSET 0
|
|
#define CFG_NTB_GOLDEN_GAP_R2B2_MASK 0x003FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SELFGEN_ADDR 0x0100
|
|
#define CFG_RESP_POWER_OFFSET 8
|
|
#define CFG_RESP_POWER_MASK 0x0000FF00
|
|
#define CFG_RESP_PPDU_TYPE_OFFSET 5
|
|
#define CFG_RESP_PPDU_TYPE_MASK 0x000000E0
|
|
#define CFG_RESP_TAMP_OFFSET 0
|
|
#define CFG_RESP_TAMP_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_INT_CTRL_ADDR 0x0104
|
|
#define RO_RX_DESC_OVERFLOW_INT_STATUS_OFFSET 25
|
|
#define RO_RX_DESC_OVERFLOW_INT_STATUS_MASK 0x3E000000
|
|
#define RO_RX_LOW_WATERMARK_INT_STATUS_OFFSET 20
|
|
#define RO_RX_LOW_WATERMARK_INT_STATUS_MASK 0x01F00000
|
|
#define RO_RX_PLD_OVERFLOW_INT_STATUS_OFFSET 15
|
|
#define RO_RX_PLD_OVERFLOW_INT_STATUS_MASK 0x000F8000
|
|
#define RO_RX_MPDU_INT_STATUS_OFFSET 10
|
|
#define RO_RX_MPDU_INT_STATUS_MASK 0x00007C00
|
|
#define RO_RX_PB_INT_STATUS_OFFSET 5
|
|
#define RO_RX_PB_INT_STATUS_MASK 0x000003E0
|
|
#define RO_RX_FC_INT_STATUS_OFFSET 0
|
|
#define RO_RX_FC_INT_STATUS_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_INT_CLR_ADDR 0x0108
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_4_OFFSET 29
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_4_MASK 0x20000000
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_3_OFFSET 28
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_3_MASK 0x10000000
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_2_OFFSET 27
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_2_MASK 0x08000000
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_1_OFFSET 26
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_1_MASK 0x04000000
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_0_OFFSET 25
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_0_MASK 0x02000000
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_4_OFFSET 24
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_4_MASK 0x01000000
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_3_OFFSET 23
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_3_MASK 0x00800000
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_2_OFFSET 22
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_2_MASK 0x00400000
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_1_OFFSET 21
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_1_MASK 0x00200000
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_0_OFFSET 20
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_0_MASK 0x00100000
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_4_OFFSET 19
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_4_MASK 0x00080000
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_3_OFFSET 18
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_3_MASK 0x00040000
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_2_OFFSET 17
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_2_MASK 0x00020000
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_1_OFFSET 16
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_1_MASK 0x00010000
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_0_OFFSET 15
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_0_MASK 0x00008000
|
|
#define CFG_RX_MPDU_INT_CLR_4_OFFSET 14
|
|
#define CFG_RX_MPDU_INT_CLR_4_MASK 0x00004000
|
|
#define CFG_RX_MPDU_INT_CLR_3_OFFSET 13
|
|
#define CFG_RX_MPDU_INT_CLR_3_MASK 0x00002000
|
|
#define CFG_RX_MPDU_INT_CLR_2_OFFSET 12
|
|
#define CFG_RX_MPDU_INT_CLR_2_MASK 0x00001000
|
|
#define CFG_RX_MPDU_INT_CLR_1_OFFSET 11
|
|
#define CFG_RX_MPDU_INT_CLR_1_MASK 0x00000800
|
|
#define CFG_RX_MPDU_INT_CLR_0_OFFSET 10
|
|
#define CFG_RX_MPDU_INT_CLR_0_MASK 0x00000400
|
|
#define CFG_RX_PB_INT_CLR_4_OFFSET 9
|
|
#define CFG_RX_PB_INT_CLR_4_MASK 0x00000200
|
|
#define CFG_RX_PB_INT_CLR_3_OFFSET 8
|
|
#define CFG_RX_PB_INT_CLR_3_MASK 0x00000100
|
|
#define CFG_RX_PB_INT_CLR_2_OFFSET 7
|
|
#define CFG_RX_PB_INT_CLR_2_MASK 0x00000080
|
|
#define CFG_RX_PB_INT_CLR_1_OFFSET 6
|
|
#define CFG_RX_PB_INT_CLR_1_MASK 0x00000040
|
|
#define CFG_RX_PB_INT_CLR_0_OFFSET 5
|
|
#define CFG_RX_PB_INT_CLR_0_MASK 0x00000020
|
|
#define CFG_RX_FC_INT_CLR_4_OFFSET 4
|
|
#define CFG_RX_FC_INT_CLR_4_MASK 0x00000010
|
|
#define CFG_RX_FC_INT_CLR_3_OFFSET 3
|
|
#define CFG_RX_FC_INT_CLR_3_MASK 0x00000008
|
|
#define CFG_RX_FC_INT_CLR_2_OFFSET 2
|
|
#define CFG_RX_FC_INT_CLR_2_MASK 0x00000004
|
|
#define CFG_RX_FC_INT_CLR_1_OFFSET 1
|
|
#define CFG_RX_FC_INT_CLR_1_MASK 0x00000002
|
|
#define CFG_RX_FC_INT_CLR_0_OFFSET 0
|
|
#define CFG_RX_FC_INT_CLR_0_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_GEN_CTRL_ADDR 0x010c
|
|
#define ZERO_CROSS_2_OFFSET 31
|
|
#define ZERO_CROSS_2_MASK 0x80000000
|
|
#define ZERO_CROSS_1_OFFSET 30
|
|
#define ZERO_CROSS_1_MASK 0x40000000
|
|
#define ZERO_CROSS_0_OFFSET 29
|
|
#define ZERO_CROSS_0_MASK 0x20000000
|
|
#define CFG_ZC_CAP_CLR_2_OFFSET 28
|
|
#define CFG_ZC_CAP_CLR_2_MASK 0x10000000
|
|
#define CFG_ZC_CAP_CLR_1_OFFSET 27
|
|
#define CFG_ZC_CAP_CLR_1_MASK 0x08000000
|
|
#define CFG_ZC_CAP_CLR_0_OFFSET 26
|
|
#define CFG_ZC_CAP_CLR_0_MASK 0x04000000
|
|
#define CFG_ZC_GEN_HALF_PERIOD_OFFSET 25
|
|
#define CFG_ZC_GEN_HALF_PERIOD_MASK 0x02000000
|
|
#define CFG_ZC_GEN_PHASE_SEL_OFFSET 23
|
|
#define CFG_ZC_GEN_PHASE_SEL_MASK 0x01800000
|
|
#define CFG_ZC_GEN_CTRL_RSV_OFFSET 22
|
|
#define CFG_ZC_GEN_CTRL_RSV_MASK 0x00400000
|
|
#define CFG_ZC_GEN_TRIG_OFFSET 21
|
|
#define CFG_ZC_GEN_TRIG_MASK 0x00200000
|
|
#define CFG_ZC_DUR_OFFSET 1
|
|
#define CFG_ZC_DUR_MASK 0x001FFFFE
|
|
#define CFG_ZC_GEN_SEL_OFFSET 0
|
|
#define CFG_ZC_GEN_SEL_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_GEN_PERIOD_ADDR 0x0110
|
|
#define CFG_ZC_PERIOD_OFFSET 0
|
|
#define CFG_ZC_PERIOD_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_GEN_TS_ADDR 0x0114
|
|
#define CFG_ZC_TIMESTAMP_OFFSET 0
|
|
#define CFG_ZC_TIMESTAMP_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_LCT_TRACK_CTRL_ADDR 0x0118
|
|
#define CFG_ZC_VIBRATE_PROTECT_OFFSET 10
|
|
#define CFG_ZC_VIBRATE_PROTECT_MASK 0x1FFFFC00
|
|
#define CFG_HW_AC_TRACK_EN_OFFSET 9
|
|
#define CFG_HW_AC_TRACK_EN_MASK 0x00000200
|
|
#define CFG_HW_AC_TRACK_TRIG_OFFSET 8
|
|
#define CFG_HW_AC_TRACK_TRIG_MASK 0x00000100
|
|
#define CFG_PERIOD_WEIGHT_OFFSET 4
|
|
#define CFG_PERIOD_WEIGHT_MASK 0x000000F0
|
|
#define CFG_LCTE_WEIGHT_OFFSET 0
|
|
#define CFG_LCTE_WEIGHT_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_GAIN_CTRL_ADDR 0x011c
|
|
#define CFG_GAIN_LOAD_EN_OFFSET 0
|
|
#define CFG_GAIN_LOAD_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GAIN_PTR_ADDR 0x0120
|
|
#define CFG_GAIN_PTR_OFFSET 0
|
|
#define CFG_GAIN_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_ZC_LCT_DELTA_ADDR 0x0124
|
|
#define DELTA_LCT_VS_LCTE_OFFSET 0
|
|
#define DELTA_LCT_VS_LCTE_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_GEN_OFFSET_ADDR 0x0128
|
|
#define CFG_ZC_GEN_OFFSET_LEFT_OFFSET 19
|
|
#define CFG_ZC_GEN_OFFSET_LEFT_MASK 0x00080000
|
|
#define CFG_ZC_GEN_OFFSET_OFFSET 0
|
|
#define CFG_ZC_GEN_OFFSET_MASK 0x0007FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_0_LOW_ADDR 0x012c
|
|
#define CFG_PTR0_LOW_BOND_OFFSET 0
|
|
#define CFG_PTR0_LOW_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_0_UP_ADDR 0x0130
|
|
#define CFG_PTR0_UP_BOND_OFFSET 0
|
|
#define CFG_PTR0_UP_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_1_LOW_ADDR 0x0134
|
|
#define CFG_PTR1_LOW_BOND_OFFSET 0
|
|
#define CFG_PTR1_LOW_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_1_UP_ADDR 0x0138
|
|
#define CFG_PTR1_UP_BOND_OFFSET 0
|
|
#define CFG_PTR1_UP_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_2_LOW_ADDR 0x013c
|
|
#define CFG_PTR2_LOW_BOND_OFFSET 0
|
|
#define CFG_PTR2_LOW_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_2_UP_ADDR 0x0140
|
|
#define CFG_PTR2_UP_BOND_OFFSET 0
|
|
#define CFG_PTR2_UP_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_3_LOW_ADDR 0x0144
|
|
#define CFG_PTR3_LOW_BOND_OFFSET 0
|
|
#define CFG_PTR3_LOW_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_3_UP_ADDR 0x0148
|
|
#define CFG_PTR3_UP_BOND_OFFSET 0
|
|
#define CFG_PTR3_UP_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_4_LOW_ADDR 0x014c
|
|
#define CFG_PTR4_LOW_BOND_OFFSET 0
|
|
#define CFG_PTR4_LOW_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_4_UP_ADDR 0x0150
|
|
#define CFG_PTR4_UP_BOND_OFFSET 0
|
|
#define CFG_PTR4_UP_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_CTRL_ADDR 0x0154
|
|
#define CFG_MAC_HREADY_FORCE_VAL_OFFSET 19
|
|
#define CFG_MAC_HREADY_FORCE_VAL_MASK 0x00080000
|
|
#define CFG_MAC_HREADY_FORCE_EN_OFFSET 18
|
|
#define CFG_MAC_HREADY_FORCE_EN_MASK 0x00040000
|
|
#define CFG_BUS_ERR_HREADY_FORCE_1_OFFSET 17
|
|
#define CFG_BUS_ERR_HREADY_FORCE_1_MASK 0x00020000
|
|
#define CFG_BUS_ERR_CG_CLR_OFFSET 16
|
|
#define CFG_BUS_ERR_CG_CLR_MASK 0x00010000
|
|
#define CFG_BUS_ERR_CG_EN_OFFSET 15
|
|
#define CFG_BUS_ERR_CG_EN_MASK 0x00008000
|
|
#define CFG_PTR_RANG4_BLACK_OFFSET 14
|
|
#define CFG_PTR_RANG4_BLACK_MASK 0x00004000
|
|
#define CFG_PTR_RANG3_BLACK_OFFSET 13
|
|
#define CFG_PTR_RANG3_BLACK_MASK 0x00002000
|
|
#define CFG_PTR_RANG2_BLACK_OFFSET 12
|
|
#define CFG_PTR_RANG2_BLACK_MASK 0x00001000
|
|
#define CFG_PTR_RANG1_BLACK_OFFSET 11
|
|
#define CFG_PTR_RANG1_BLACK_MASK 0x00000800
|
|
#define CFG_PTR_RANG0_BLACK_OFFSET 10
|
|
#define CFG_PTR_RANG0_BLACK_MASK 0x00000400
|
|
#define CFG_PTR4_CTRL_OFFSET 8
|
|
#define CFG_PTR4_CTRL_MASK 0x00000300
|
|
#define CFG_PTR3_CTRL_OFFSET 6
|
|
#define CFG_PTR3_CTRL_MASK 0x000000C0
|
|
#define CFG_PTR2_CTRL_OFFSET 4
|
|
#define CFG_PTR2_CTRL_MASK 0x00000030
|
|
#define CFG_PTR1_CTRL_OFFSET 2
|
|
#define CFG_PTR1_CTRL_MASK 0x0000000C
|
|
#define CFG_PTR0_CTRL_OFFSET 0
|
|
#define CFG_PTR0_CTRL_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_AHB_DBG_CTRL_ADDR 0x0158
|
|
#define CFG_AHB_TRANS_DONE_SEL0_OFFSET 0
|
|
#define CFG_AHB_TRANS_DONE_SEL0_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_PHY_FORCE_0_ADDR 0x015c
|
|
#define CFG_PHY_RX_ABORT_OFFSET 31
|
|
#define CFG_PHY_RX_ABORT_MASK 0x80000000
|
|
#define CFG_PHY_RX_ABORT_FORCE_EN_OFFSET 30
|
|
#define CFG_PHY_RX_ABORT_FORCE_EN_MASK 0x40000000
|
|
#define CFG_PHY_RX_VERSION_OFFSET 27
|
|
#define CFG_PHY_RX_VERSION_MASK 0x38000000
|
|
#define CFG_PHY_RX_VERSION_FORCE_EN_OFFSET 26
|
|
#define CFG_PHY_RX_VERSION_FORCE_EN_MASK 0x04000000
|
|
#define CFG_PHY_RX_PORT_OFFSET 24
|
|
#define CFG_PHY_RX_PORT_MASK 0x03000000
|
|
#define CFG_PHY_RX_PORT_FORCE_EN_OFFSET 23
|
|
#define CFG_PHY_RX_PORT_FORCE_EN_MASK 0x00800000
|
|
#define CFG_PHY_PB_CRC_DONE_OFFSET 22
|
|
#define CFG_PHY_PB_CRC_DONE_MASK 0x00400000
|
|
#define CFG_PHY_PB_CRC_DONE_FORCE_EN_OFFSET 21
|
|
#define CFG_PHY_PB_CRC_DONE_FORCE_EN_MASK 0x00200000
|
|
#define CFG_PHY_FC_CRC_DONE_OFFSET 20
|
|
#define CFG_PHY_FC_CRC_DONE_MASK 0x00100000
|
|
#define CFG_PHY_FC_CRC_DONE_FORCE_EN_OFFSET 19
|
|
#define CFG_PHY_FC_CRC_DONE_FORCE_EN_MASK 0x00080000
|
|
#define CFG_PHY_RX_PRS_OFFSET 18
|
|
#define CFG_PHY_RX_PRS_MASK 0x00040000
|
|
#define CFG_PHY_RX_PRS_FORCE_EN_OFFSET 17
|
|
#define CFG_PHY_RX_PRS_FORCE_EN_MASK 0x00020000
|
|
#define CFG_PHY_PCS_BUSY_OFFSET 16
|
|
#define CFG_PHY_PCS_BUSY_MASK 0x00010000
|
|
#define CFG_PHY_PCS_BUSY_FORCE_EN_OFFSET 15
|
|
#define CFG_PHY_PCS_BUSY_FORCE_EN_MASK 0x00008000
|
|
#define CFG_PHY_RX_VLD_OFFSET 14
|
|
#define CFG_PHY_RX_VLD_MASK 0x00004000
|
|
#define CFG_PHY_RX_VLD_FORCE_EN_OFFSET 13
|
|
#define CFG_PHY_RX_VLD_FORCE_EN_MASK 0x00002000
|
|
#define CFG_PHY_RX_FRAME_OFFSET 12
|
|
#define CFG_PHY_RX_FRAME_MASK 0x00001000
|
|
#define CFG_PHY_RX_FRAME_FORCE_EN_OFFSET 11
|
|
#define CFG_PHY_RX_FRAME_FORCE_EN_MASK 0x00000800
|
|
#define CFG_PHY_RX_RATE_MODE_OFFSET 8
|
|
#define CFG_PHY_RX_RATE_MODE_MASK 0x00000700
|
|
#define CFG_PHY_RX_RATE_MODE_FORCE_EN_OFFSET 7
|
|
#define CFG_PHY_RX_RATE_MODE_FORCE_EN_MASK 0x00000080
|
|
#define CFG_PHY_RX_READY_OFFSET 6
|
|
#define CFG_PHY_RX_READY_MASK 0x00000040
|
|
#define CFG_PHY_RX_READY_FORCE_EN_OFFSET 5
|
|
#define CFG_PHY_RX_READY_FORCE_EN_MASK 0x00000020
|
|
#define CFG_PHY_RX_ENABLE_OFFSET 4
|
|
#define CFG_PHY_RX_ENABLE_MASK 0x00000010
|
|
#define CFG_PHY_RX_ENABLE_FORCE_EN_OFFSET 3
|
|
#define CFG_PHY_RX_ENABLE_FORCE_EN_MASK 0x00000008
|
|
#define CFG_PHY_RX_PHASE_SEL_OFFSET 1
|
|
#define CFG_PHY_RX_PHASE_SEL_MASK 0x00000006
|
|
#define CFG_PHY_RX_PHASE_SEL_FORCE_EN_OFFSET 0
|
|
#define CFG_PHY_RX_PHASE_SEL_FORCE_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_PHY_FORCE_1_ADDR 0x0160
|
|
#define CFG_PHY_RX_PHASE_DESC_OFFSET 31
|
|
#define CFG_PHY_RX_PHASE_DESC_MASK 0x80000000
|
|
#define CFG_PHY_TX_PLD_MODU_MODE_OFFSET 28
|
|
#define CFG_PHY_TX_PLD_MODU_MODE_MASK 0x70000000
|
|
#define CFG_PHY_TX_PLD_MODU_MODE_FORCE_EN_OFFSET 27
|
|
#define CFG_PHY_TX_PLD_MODU_MODE_FORCE_EN_MASK 0x08000000
|
|
#define CFG_PHY_TX_RATE_MODE_OFFSET 25
|
|
#define CFG_PHY_TX_RATE_MODE_MASK 0x06000000
|
|
#define CFG_PHY_TX_RATE_MODE_FORCE_EN_OFFSET 24
|
|
#define CFG_PHY_TX_RATE_MODE_FORCE_EN_MASK 0x01000000
|
|
#define CFG_PHY_TX_ENABLE_OFFSET 23
|
|
#define CFG_PHY_TX_ENABLE_MASK 0x00800000
|
|
#define CFG_PHY_TX_ENABLE_FORCE_EN_OFFSET 22
|
|
#define CFG_PHY_TX_ENABLE_FORCE_EN_MASK 0x00400000
|
|
#define CFG_PHY_TX_ABORT_OFFSET 21
|
|
#define CFG_PHY_TX_ABORT_MASK 0x00200000
|
|
#define CFG_PHY_TX_ABORT_FORCE_EN_OFFSET 20
|
|
#define CFG_PHY_TX_ABORT_FORCE_EN_MASK 0x00100000
|
|
#define CFG_PHY_TX_START_OFFSET 19
|
|
#define CFG_PHY_TX_START_MASK 0x00080000
|
|
#define CFG_PHY_TX_START_FORCE_EN_OFFSET 18
|
|
#define CFG_PHY_TX_START_FORCE_EN_MASK 0x00040000
|
|
#define CFG_PHY_TX_BANDSEL_OFFSET 16
|
|
#define CFG_PHY_TX_BANDSEL_MASK 0x00030000
|
|
#define CFG_PHY_TX_BANDSEL_FORCE_EN_OFFSET 15
|
|
#define CFG_PHY_TX_BANDSEL_FORCE_EN_MASK 0x00008000
|
|
#define CFG_PHY_TX_VERSION_OFFSET 12
|
|
#define CFG_PHY_TX_VERSION_MASK 0x00007000
|
|
#define CFG_PHY_TX_VERSION_FORCE_EN_OFFSET 11
|
|
#define CFG_PHY_TX_VERSION_FORCE_EN_MASK 0x00000800
|
|
#define CFG_PHY_TX_PRS_OFFSET 10
|
|
#define CFG_PHY_TX_PRS_MASK 0x00000400
|
|
#define CFG_PHY_TX_PRS_FORCE_EN_OFFSET 9
|
|
#define CFG_PHY_TX_PRS_FORCE_EN_MASK 0x00000200
|
|
#define CFG_PHY_TX_VLD_OFFSET 8
|
|
#define CFG_PHY_TX_VLD_MASK 0x00000100
|
|
#define CFG_PHY_TX_VLD_FORCE_EN_OFFSET 7
|
|
#define CFG_PHY_TX_VLD_FORCE_EN_MASK 0x00000080
|
|
#define CFG_PHY_PB_RCV_DONE_OFFSET 6
|
|
#define CFG_PHY_PB_RCV_DONE_MASK 0x00000040
|
|
#define CFG_PHY_PB_RCV_DONE_FORCE_EN_OFFSET 5
|
|
#define CFG_PHY_PB_RCV_DONE_FORCE_EN_MASK 0x00000020
|
|
#define CFG_PHY_FC_RCV_DONE_OFFSET 4
|
|
#define CFG_PHY_FC_RCV_DONE_MASK 0x00000010
|
|
#define CFG_PHY_FC_RCV_DONE_FORCE_EN_OFFSET 3
|
|
#define CFG_PHY_FC_RCV_DONE_FORCE_EN_MASK 0x00000008
|
|
#define CFG_PHY_RX_BANDSEL_OFFSET 1
|
|
#define CFG_PHY_RX_BANDSEL_MASK 0x00000006
|
|
#define CFG_PHY_RX_BANDSEL_FORCE_EN_OFFSET 0
|
|
#define CFG_PHY_RX_BANDSEL_FORCE_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_PHY_FORCE_2_ADDR 0x0164
|
|
#define CFG_TURBO_DEC_ON_LAST_PB_DONE_EN_OFFSET 26
|
|
#define CFG_TURBO_DEC_ON_LAST_PB_DONE_EN_MASK 0x04000000
|
|
#define CFG_TURBO_DEC_ON_LAST_PB_DONE_OFFSET 25
|
|
#define CFG_TURBO_DEC_ON_LAST_PB_DONE_MASK 0x02000000
|
|
#define CFG_PHY_TX_CAP_FORCE_VALUE_OFFSET 23
|
|
#define CFG_PHY_TX_CAP_FORCE_VALUE_MASK 0x01800000
|
|
#define CFG_PHY_TX_CAP_FORCE_EN_OFFSET 22
|
|
#define CFG_PHY_TX_CAP_FORCE_EN_MASK 0x00400000
|
|
#define CFG_PHY_RX_NEED_TX_RESP_OFFSET 21
|
|
#define CFG_PHY_RX_NEED_TX_RESP_MASK 0x00200000
|
|
#define CFG_PHY_RX_NEED_TX_RESP_FORCE_EN_OFFSET 20
|
|
#define CFG_PHY_RX_NEED_TX_RESP_FORCE_EN_MASK 0x00100000
|
|
#define CFG_PHY_TX_TMI_OFFSET 15
|
|
#define CFG_PHY_TX_TMI_MASK 0x000F8000
|
|
#define CFG_PHY_TX_TMI_FORCE_EN_OFFSET 14
|
|
#define CFG_PHY_TX_TMI_FORCE_EN_MASK 0x00004000
|
|
#define CFG_PHY_RX_HSPEED_INV_OFFSET 13
|
|
#define CFG_PHY_RX_HSPEED_INV_MASK 0x00002000
|
|
#define CFG_PHY_RX_HSPEED_RATE_FORCE_EN_OFFSET 12
|
|
#define CFG_PHY_RX_HSPEED_RATE_FORCE_EN_MASK 0x00001000
|
|
#define CFG_PHY_RX_HSPEED_RATE_OFFSET 11
|
|
#define CFG_PHY_RX_HSPEED_RATE_MASK 0x00000800
|
|
#define CFG_PHY_TX_READY_OFFSET 10
|
|
#define CFG_PHY_TX_READY_MASK 0x00000400
|
|
#define CFG_PHY_TX_READY_FORCE_EN_OFFSET 9
|
|
#define CFG_PHY_TX_READY_FORCE_EN_MASK 0x00000200
|
|
#define CFG_PHY_TX_PROCESSING_OFFSET 8
|
|
#define CFG_PHY_TX_PROCESSING_MASK 0x00000100
|
|
#define CFG_PHY_TX_PROCESSING_FORCE_EN_OFFSET 7
|
|
#define CFG_PHY_TX_PROCESSING_FORCE_EN_MASK 0x00000080
|
|
#define CFG_PHY_TX_UNDERFLOW_OFFSET 6
|
|
#define CFG_PHY_TX_UNDERFLOW_MASK 0x00000040
|
|
#define CFG_PHY_TX_UNDERFLOW_FORCE_EN_OFFSET 5
|
|
#define CFG_PHY_TX_UNDERFLOW_FORCE_EN_MASK 0x00000020
|
|
#define CFG_NARROW_BANDSEL_OFFSET 4
|
|
#define CFG_NARROW_BANDSEL_MASK 0x00000010
|
|
#define CFG_NARROW_BANDSEL_FORCE_EN_OFFSET 3
|
|
#define CFG_NARROW_BANDSEL_FORCE_EN_MASK 0x00000008
|
|
#define CFG_PHY_TX_PHASE_SEL_OFFSET 1
|
|
#define CFG_PHY_TX_PHASE_SEL_MASK 0x00000006
|
|
#define CFG_PHY_TX_PHASE_SEL_FORCE_EN_OFFSET 0
|
|
#define CFG_PHY_TX_PHASE_SEL_FORCE_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_RD_MACPHY_INTF_0_ADDR 0x0168
|
|
#define PHY_RX_BANDSEL_OFFSET 30
|
|
#define PHY_RX_BANDSEL_MASK 0xC0000000
|
|
#define PHY_RX_PORT_OFFSET 28
|
|
#define PHY_RX_PORT_MASK 0x30000000
|
|
#define PHY_RX_PRS_OFFSET 27
|
|
#define PHY_RX_PRS_MASK 0x08000000
|
|
#define PHY_RX_VLD_OFFSET 26
|
|
#define PHY_RX_VLD_MASK 0x04000000
|
|
#define PHY_RX_FRAME_OFFSET 25
|
|
#define PHY_RX_FRAME_MASK 0x02000000
|
|
#define PHY_RX_PHASE_SEL_OFFSET 23
|
|
#define PHY_RX_PHASE_SEL_MASK 0x01800000
|
|
#define PHY_RX_RATE_MODE_OFFSET 20
|
|
#define PHY_RX_RATE_MODE_MASK 0x00700000
|
|
#define PHY_RX_ENABLE_OFFSET 19
|
|
#define PHY_RX_ENABLE_MASK 0x00080000
|
|
#define PHY_RX_READY_OFFSET 18
|
|
#define PHY_RX_READY_MASK 0x00040000
|
|
#define TX_SW_FC_VLD_OFFSET 17
|
|
#define TX_SW_FC_VLD_MASK 0x00020000
|
|
#define PHY_TX_READY_OFFSET 16
|
|
#define PHY_TX_READY_MASK 0x00010000
|
|
#define PHY_TX_PROCESSING_OFFSET 15
|
|
#define PHY_TX_PROCESSING_MASK 0x00008000
|
|
#define PHY_TX_PHASE_SEL_OFFSET 13
|
|
#define PHY_TX_PHASE_SEL_MASK 0x00006000
|
|
#define PHY_TX_PLD_MODU_MODE_OFFSET 10
|
|
#define PHY_TX_PLD_MODU_MODE_MASK 0x00001C00
|
|
#define PHY_TX_RATE_MODE_OFFSET 8
|
|
#define PHY_TX_RATE_MODE_MASK 0x00000300
|
|
#define PHY_TX_ENABLE_OFFSET 7
|
|
#define PHY_TX_ENABLE_MASK 0x00000080
|
|
#define PHY_TX_BANDSEL_OFFSET 5
|
|
#define PHY_TX_BANDSEL_MASK 0x00000060
|
|
#define PHY_TX_VERSION_OFFSET 2
|
|
#define PHY_TX_VERSION_MASK 0x0000001C
|
|
#define PHY_TX_PRS_OFFSET 1
|
|
#define PHY_TX_PRS_MASK 0x00000002
|
|
#define PHY_TX_VLD_OFFSET 0
|
|
#define PHY_TX_VLD_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_RD_MACPHY_INTF_1_ADDR 0x016c
|
|
#define RX_SW_FC_VLD_OFFSET 5
|
|
#define RX_SW_FC_VLD_MASK 0x00000020
|
|
#define PHY_PB_RCV_DONE_OFFSET 4
|
|
#define PHY_PB_RCV_DONE_MASK 0x00000010
|
|
#define PHY_FC_RCV_DONE_OFFSET 3
|
|
#define PHY_FC_RCV_DONE_MASK 0x00000008
|
|
#define PHY_RX_VERSION_OFFSET 0
|
|
#define PHY_RX_VERSION_MASK 0x00000007
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_CAP_ADDR 0x0170
|
|
#define CFG_ZC_DETECT_SEL_OFFSET 27
|
|
#define CFG_ZC_DETECT_SEL_MASK 0x38000000
|
|
#define CFG_ZC2_CAP_ENABLE_OFFSET 26
|
|
#define CFG_ZC2_CAP_ENABLE_MASK 0x04000000
|
|
#define CFG_ZC2_TRIG_OFFSET 25
|
|
#define CFG_ZC2_TRIG_MASK 0x02000000
|
|
#define CFG_ZC1_CAP_ENABLE_OFFSET 24
|
|
#define CFG_ZC1_CAP_ENABLE_MASK 0x01000000
|
|
#define CFG_ZC1_TRIG_OFFSET 23
|
|
#define CFG_ZC1_TRIG_MASK 0x00800000
|
|
#define CFG_ZC_CAP_ENABLE_OFFSET 22
|
|
#define CFG_ZC_CAP_ENABLE_MASK 0x00400000
|
|
#define CFG_ZC_TRIG_OFFSET 21
|
|
#define CFG_ZC_TRIG_MASK 0x00200000
|
|
#define CFG_ZC_CAP_HALF_PERIOD_OFFSET 20
|
|
#define CFG_ZC_CAP_HALF_PERIOD_MASK 0x00100000
|
|
#define CFG_ZC_CAP_INTERVAL_OFFSET 4
|
|
#define CFG_ZC_CAP_INTERVAL_MASK 0x000FFFF0
|
|
#define CFG_ZC_INT_NUM_OFFSET 1
|
|
#define CFG_ZC_INT_NUM_MASK 0x0000000E
|
|
#define CFG_ZC_FALL_OFFSET 0
|
|
#define CFG_ZC_FALL_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC0_TS0_ADDR 0x0174
|
|
#define ZC0_TS0_OFFSET 0
|
|
#define ZC0_TS0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC0_TS1_ADDR 0x0178
|
|
#define ZC0_TS1_OFFSET 0
|
|
#define ZC0_TS1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC0_TS2_ADDR 0x017c
|
|
#define ZC0_TS2_OFFSET 0
|
|
#define ZC0_TS2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC0_TS3_ADDR 0x0180
|
|
#define ZC0_TS3_OFFSET 0
|
|
#define ZC0_TS3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC0_TS4_ADDR 0x0184
|
|
#define ZC0_TS4_OFFSET 0
|
|
#define ZC0_TS4_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC0_TS5_ADDR 0x0188
|
|
#define ZC0_TS5_OFFSET 0
|
|
#define ZC0_TS5_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC0_TS6_ADDR 0x018c
|
|
#define ZC0_TS6_OFFSET 0
|
|
#define ZC0_TS6_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC0_TS7_ADDR 0x0190
|
|
#define ZC0_TS7_OFFSET 0
|
|
#define ZC0_TS7_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC1_TS0_ADDR 0x0194
|
|
#define ZC1_TS0_OFFSET 0
|
|
#define ZC1_TS0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC1_TS1_ADDR 0x0198
|
|
#define ZC1_TS1_OFFSET 0
|
|
#define ZC1_TS1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC1_TS2_ADDR 0x019c
|
|
#define ZC1_TS2_OFFSET 0
|
|
#define ZC1_TS2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC1_TS3_ADDR 0x0200
|
|
#define ZC1_TS3_OFFSET 0
|
|
#define ZC1_TS3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC1_TS4_ADDR 0x0204
|
|
#define ZC1_TS4_OFFSET 0
|
|
#define ZC1_TS4_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC1_TS5_ADDR 0x0208
|
|
#define ZC1_TS5_OFFSET 0
|
|
#define ZC1_TS5_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC1_TS6_ADDR 0x020c
|
|
#define ZC1_TS6_OFFSET 0
|
|
#define ZC1_TS6_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC1_TS7_ADDR 0x0210
|
|
#define ZC1_TS7_OFFSET 0
|
|
#define ZC1_TS7_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC2_TS0_ADDR 0x0214
|
|
#define ZC2_TS0_OFFSET 0
|
|
#define ZC2_TS0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC2_TS1_ADDR 0x0218
|
|
#define ZC2_TS1_OFFSET 0
|
|
#define ZC2_TS1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC2_TS2_ADDR 0x021c
|
|
#define ZC2_TS2_OFFSET 0
|
|
#define ZC2_TS2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC2_TS3_ADDR 0x0220
|
|
#define ZC2_TS3_OFFSET 0
|
|
#define ZC2_TS3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC2_TS4_ADDR 0x0224
|
|
#define ZC2_TS4_OFFSET 0
|
|
#define ZC2_TS4_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC2_TS5_ADDR 0x0228
|
|
#define ZC2_TS5_OFFSET 0
|
|
#define ZC2_TS5_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC2_TS6_ADDR 0x022c
|
|
#define ZC2_TS6_OFFSET 0
|
|
#define ZC2_TS6_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC2_TS7_ADDR 0x0230
|
|
#define ZC2_TS7_OFFSET 0
|
|
#define ZC2_TS7_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC0_PERIOD_ADDR 0x0234
|
|
#define HW_ZC0_PERIOD_OFFSET 0
|
|
#define HW_ZC0_PERIOD_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC1_PERIOD_ADDR 0x0238
|
|
#define HW_ZC1_PERIOD_OFFSET 0
|
|
#define HW_ZC1_PERIOD_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC2_PERIOD_ADDR 0x023c
|
|
#define HW_ZC2_PERIOD_OFFSET 0
|
|
#define HW_ZC2_PERIOD_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ECO_REG_ADDR 0x0240
|
|
#define CFG_ECO_DUMMY_OFFSET 7
|
|
#define CFG_ECO_DUMMY_MASK 0xFFFFFF80
|
|
#define CFG_SCH_FIX_QUEUE_ENABLE_START_NTB2_OFFSET 6
|
|
#define CFG_SCH_FIX_QUEUE_ENABLE_START_NTB2_MASK 0x00000040
|
|
#define CFG_MAC_DMA_NEW_OFFSET 5
|
|
#define CFG_MAC_DMA_NEW_MASK 0x00000020
|
|
#define CFG_NO_DROP_NEED_RX_OFFSET 4
|
|
#define CFG_NO_DROP_NEED_RX_MASK 0x00000010
|
|
#define CFG_ALWAYS_RX_OFFSET 3
|
|
#define CFG_ALWAYS_RX_MASK 0x00000008
|
|
#define CFG_BC_RETRY_EN_OFFSET 2
|
|
#define CFG_BC_RETRY_EN_MASK 0x00000004
|
|
#define CFG_SCH_FIX_QUEUE0_STOP_OFFSET 1
|
|
#define CFG_SCH_FIX_QUEUE0_STOP_MASK 0x00000002
|
|
#define CFG_SCH_FIX_QUEUE_ENABLE_START_NTB_OFFSET 0
|
|
#define CFG_SCH_FIX_QUEUE_ENABLE_START_NTB_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC0_LCTE_ADDR 0x0244
|
|
#define ZC0_LCTE_OFFSET 0
|
|
#define ZC0_LCTE_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC1_LCTE_ADDR 0x0248
|
|
#define ZC1_LCTE_OFFSET 0
|
|
#define ZC1_LCTE_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC2_LCTE_ADDR 0x024C
|
|
#define ZC2_LCTE_OFFSET 0
|
|
#define ZC2_LCTE_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BEACON_PERIOD_GOLDEN_ADDR 0x0250
|
|
#define CFG_BEACON_PERIOD_GOLDEN_OFFSET 0
|
|
#define CFG_BEACON_PERIOD_GOLDEN_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GP_BTO_0_ADDR 0x0254
|
|
#define CFG_GP_BTO_0_EN_OFFSET 16
|
|
#define CFG_GP_BTO_0_EN_MASK 0x00010000
|
|
#define CFG_GP_BTO_0_OFFSET 0
|
|
#define CFG_GP_BTO_0_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GP_BTO_1_ADDR 0x0258
|
|
#define CFG_GP_BTO_1_EN_OFFSET 16
|
|
#define CFG_GP_BTO_1_EN_MASK 0x00010000
|
|
#define CFG_GP_BTO_1_OFFSET 0
|
|
#define CFG_GP_BTO_1_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GP_BTO_2_ADDR 0x025C
|
|
#define CFG_GP_BTO_2_EN_OFFSET 16
|
|
#define CFG_GP_BTO_2_EN_MASK 0x00010000
|
|
#define CFG_GP_BTO_2_OFFSET 0
|
|
#define CFG_GP_BTO_2_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GP_BTO_3_ADDR 0x0260
|
|
#define CFG_GP_BTO_3_EN_OFFSET 16
|
|
#define CFG_GP_BTO_3_EN_MASK 0x00010000
|
|
#define CFG_GP_BTO_3_OFFSET 0
|
|
#define CFG_GP_BTO_3_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GP_INIT_VEC_0_ADDR 0x0264
|
|
#define CFG_GP_INITIAL_VEC_0_OFFSET 0
|
|
#define CFG_GP_INITIAL_VEC_0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GP_INIT_VEC_1_ADDR 0x0268
|
|
#define CFG_GP_INITIAL_VEC_1_OFFSET 0
|
|
#define CFG_GP_INITIAL_VEC_1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GP_INIT_VEC_2_ADDR 0x026C
|
|
#define CFG_GP_INITIAL_VEC_2_OFFSET 0
|
|
#define CFG_GP_INITIAL_VEC_2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GP_INIT_VEC_3_ADDR 0x0270
|
|
#define CFG_GP_INITIAL_VEC_3_OFFSET 0
|
|
#define CFG_GP_INITIAL_VEC_3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CRC_CTRL_0_ADDR 0x0274
|
|
#define CFG_PBCS_CRC_INIT_VALUE_OFFSET 29
|
|
#define CFG_PBCS_CRC_INIT_VALUE_MASK 0x20000000
|
|
#define CFG_PBCS_CRC_INVERT_OFFSET 28
|
|
#define CFG_PBCS_CRC_INVERT_MASK 0x10000000
|
|
#define CFG_24BIT_MAGIC_NUMBER_OFFSET 4
|
|
#define CFG_24BIT_MAGIC_NUMBER_MASK 0x0FFFFFF0
|
|
#define CFG_FC_CRC_INIT_VALUE_OFFSET 3
|
|
#define CFG_FC_CRC_INIT_VALUE_MASK 0x00000008
|
|
#define CFG_FC_CRC_INVERT_OFFSET 2
|
|
#define CFG_FC_CRC_INVERT_MASK 0x00000004
|
|
#define CFG_PB_CRC_INIT_VALUE_OFFSET 1
|
|
#define CFG_PB_CRC_INIT_VALUE_MASK 0x00000002
|
|
#define CFG_PB_CRC_INVERT_OFFSET 0
|
|
#define CFG_PB_CRC_INVERT_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_CRC_CTRL_1_ADDR 0x0278
|
|
#define CFG_32BIT_MAGIC_NUMBER_OFFSET 0
|
|
#define CFG_32BIT_MAGIC_NUMBER_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKD_CTRL_ADDR 0x027c
|
|
#define CFG_SACKI_LENGTH_OFFSET 16
|
|
#define CFG_SACKI_LENGTH_MASK 0x007F0000
|
|
#define CFG_SACKT_OFFSET 8
|
|
#define CFG_SACKT_MASK 0x0000FF00
|
|
#define CFG_SACK_VLD_PLS_OFFSET 2
|
|
#define CFG_SACK_VLD_PLS_MASK 0x00000004
|
|
#define CFG_SACKD_START_OFFSET 1
|
|
#define CFG_SACKD_START_MASK 0x00000002
|
|
#define CFG_SW_SACKD_EN_OFFSET 0
|
|
#define CFG_SW_SACKD_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKD_SACKI_0_ADDR 0x0280
|
|
#define CFG_SACKI_31_0_OFFSET 0
|
|
#define CFG_SACKI_31_0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKD_SACKI_1_ADDR 0x0284
|
|
#define CFG_SACKI_63_32_OFFSET 0
|
|
#define CFG_SACKI_63_32_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKD_SACKI_2_ADDR 0x0288
|
|
#define CFG_SACKI_71_64_OFFSET 0
|
|
#define CFG_SACKI_71_64_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKD_MPDU_INFO_0_ADDR 0x028c
|
|
#define CFG_MPDU_3_INFO_VLD_PLS_OFFSET 3
|
|
#define CFG_MPDU_3_INFO_VLD_PLS_MASK 0x00000008
|
|
#define CFG_MPDU_2_INFO_VLD_PLS_OFFSET 2
|
|
#define CFG_MPDU_2_INFO_VLD_PLS_MASK 0x00000004
|
|
#define CFG_MPDU_1_INFO_VLD_PLS_OFFSET 1
|
|
#define CFG_MPDU_1_INFO_VLD_PLS_MASK 0x00000002
|
|
#define CFG_MPDU_0_INFO_VLD_PLS_OFFSET 0
|
|
#define CFG_MPDU_0_INFO_VLD_PLS_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKD_MPDU_INFO_1_ADDR 0x0290
|
|
#define CFG_MPDU_1_TX_PB_NUM_OFFSET 16
|
|
#define CFG_MPDU_1_TX_PB_NUM_MASK 0x03FF0000
|
|
#define CFG_MPDU_0_TX_PB_NUM_OFFSET 0
|
|
#define CFG_MPDU_0_TX_PB_NUM_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKD_MPDU_INFO_2_ADDR 0x0294
|
|
#define CFG_MPDU_3_TX_PB_NUM_OFFSET 16
|
|
#define CFG_MPDU_3_TX_PB_NUM_MASK 0x03FF0000
|
|
#define CFG_MPDU_2_TX_PB_NUM_OFFSET 0
|
|
#define CFG_MPDU_2_TX_PB_NUM_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKD_MPDU_INFO_3_ADDR 0x0298
|
|
#define CFG_MPDU_0_BIT_MAP_PTR_OFFSET 0
|
|
#define CFG_MPDU_0_BIT_MAP_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKD_MPDU_INFO_4_ADDR 0x029c
|
|
#define CFG_MPDU_1_BIT_MAP_PTR_OFFSET 0
|
|
#define CFG_MPDU_1_BIT_MAP_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKD_MPDU_INFO_5_ADDR 0x02a0
|
|
#define CFG_MPDU_2_BIT_MAP_PTR_OFFSET 0
|
|
#define CFG_MPDU_2_BIT_MAP_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKD_MPDU_INFO_6_ADDR 0x02a4
|
|
#define CFG_MPDU_3_BIT_MAP_PTR_OFFSET 0
|
|
#define CFG_MPDU_3_BIT_MAP_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKD_DEBUG_STS_0_ADDR 0x02a8
|
|
#define SACKD_DEBUG_0_OFFSET 0
|
|
#define SACKD_DEBUG_0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKD_DEBUG_STS_1_ADDR 0x02ac
|
|
#define SACKD_DEBUG_1_OFFSET 0
|
|
#define SACKD_DEBUG_1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_PHY_FORCE_3_ADDR 0x0328
|
|
#define CFG_PHY_TMAP_PTR_OFFSET 0
|
|
#define CFG_PHY_TMAP_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_PHY_FORCE_4_ADDR 0x032c
|
|
#define CFG_PHY_RX_PB_NUM_FORCE_EN_OFFSET 20
|
|
#define CFG_PHY_RX_PB_NUM_FORCE_EN_MASK 0x00100000
|
|
#define CFG_PHY_RX_PB_NUM_OFFSET 8
|
|
#define CFG_PHY_RX_PB_NUM_MASK 0x0003FF00
|
|
#define CFG_PHY_TMAP_PTR_FORCE_EN_OFFSET 2
|
|
#define CFG_PHY_TMAP_PTR_FORCE_EN_MASK 0x00000004
|
|
#define CFG_PHY_TMAP_PTR_VLD_OFFSET 1
|
|
#define CFG_PHY_TMAP_PTR_VLD_MASK 0x00000002
|
|
#define CFG_PHY_TMAP_PTR_VLD_FORCE_EN_OFFSET 0
|
|
#define CFG_PHY_TMAP_PTR_VLD_FORCE_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_TONE_MAP_DMA_CTRL_ADDR 0x0330
|
|
#define CFG_TMAP_LOAD_EN_OFFSET 8
|
|
#define CFG_TMAP_LOAD_EN_MASK 0x00000100
|
|
#define CFG_PHY_TMAP_RAM_BASE_ADDR_OFFSET 0
|
|
#define CFG_PHY_TMAP_RAM_BASE_ADDR_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SOUND_RESP_CTRL_ADDR 0x0334
|
|
#define CFG_SCF_CLR_EN_OFFSET 1
|
|
#define CFG_SCF_CLR_EN_MASK 0x00000002
|
|
#define CFG_SCF_OFFSET 0
|
|
#define CFG_SCF_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_FC_FORCE_CTRL_0_ADDR 0x0338
|
|
#define CFG_SW_FC_WORD_0_OFFSET 0
|
|
#define CFG_SW_FC_WORD_0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_FC_FORCE_CTRL_1_ADDR 0x033c
|
|
#define CFG_SW_FC_WORD_1_OFFSET 0
|
|
#define CFG_SW_FC_WORD_1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_FC_FORCE_CTRL_2_ADDR 0x0340
|
|
#define CFG_SW_FC_WORD_2_OFFSET 0
|
|
#define CFG_SW_FC_WORD_2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_FC_FORCE_CTRL_3_ADDR 0x0344
|
|
#define CFG_SW_FC_WORD_3_OFFSET 0
|
|
#define CFG_SW_FC_WORD_3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_FC_FORCE_CTRL_EN_ADDR 0x0348
|
|
#define CFG_SW_FC_WORD_FORCE_EN_OFFSET 0
|
|
#define CFG_SW_FC_WORD_FORCE_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_INT_EXT_0_CLR_ADDR 0x0360
|
|
#define CFG_INT_EXT_0_CLR_OFFSET 0
|
|
#define CFG_INT_EXT_0_CLR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_INT_EXT_0_ENA_ADDR 0x0364
|
|
#define CFG_INT_EXT_0_ENA_OFFSET 0
|
|
#define CFG_INT_EXT_0_ENA_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_INT_EXT_0_RAW_ADDR 0x0368
|
|
#define CFG_INT_EXT_0_RAW_OFFSET 0
|
|
#define CFG_INT_EXT_0_RAW_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_INT_EXT_0_STS_ADDR 0x036c
|
|
#define CFG_INT_EXT_0_STS_OFFSET 0
|
|
#define CFG_INT_EXT_0_STS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_INT_EXT_1_CLR_ADDR 0x0370
|
|
#define CFG_INT_EXT_1_CLR_OFFSET 0
|
|
#define CFG_INT_EXT_1_CLR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_INT_EXT_1_ENA_ADDR 0x0374
|
|
#define CFG_INT_EXT_1_ENA_OFFSET 0
|
|
#define CFG_INT_EXT_1_ENA_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_INT_EXT_1_RAW_ADDR 0x0378
|
|
#define CFG_INT_EXT_1_RAW_OFFSET 0
|
|
#define CFG_INT_EXT_1_RAW_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_INT_EXT_1_STS_ADDR 0x037c
|
|
#define CFG_INT_EXT_1_STS_OFFSET 0
|
|
#define CFG_INT_EXT_1_STS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_INT_EXT_2_CLR_ADDR 0x0380
|
|
#define CFG_INT_EXT_2_CLR_OFFSET 0
|
|
#define CFG_INT_EXT_2_CLR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_INT_EXT_2_ENA_ADDR 0x0384
|
|
#define CFG_INT_EXT_2_ENA_OFFSET 0
|
|
#define CFG_INT_EXT_2_ENA_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_INT_EXT_2_RAW_ADDR 0x0388
|
|
#define CFG_INT_EXT_2_RAW_OFFSET 0
|
|
#define CFG_INT_EXT_2_RAW_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_INT_EXT_2_STS_ADDR 0x038c
|
|
#define CFG_INT_EXT_2_STS_OFFSET 0
|
|
#define CFG_INT_EXT_2_STS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_INT_EXT_3_CLR_ADDR 0x0390
|
|
#define CFG_INT_EXT_3_CLR_OFFSET 0
|
|
#define CFG_INT_EXT_3_CLR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_INT_EXT_3_ENA_ADDR 0x0394
|
|
#define CFG_INT_EXT_3_ENA_OFFSET 0
|
|
#define CFG_INT_EXT_3_ENA_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_INT_EXT_3_RAW_ADDR 0x0398
|
|
#define CFG_INT_EXT_3_RAW_OFFSET 0
|
|
#define CFG_INT_EXT_3_RAW_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_INT_EXT_3_STS_ADDR 0x039c
|
|
#define CFG_INT_EXT_3_STS_OFFSET 0
|
|
#define CFG_INT_EXT_3_STS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COLLECT_CTRL_ADDR 0x03a0
|
|
#define CFG_RAW_BIT_MAP_MPDU_3_CLR_OFFSET 15
|
|
#define CFG_RAW_BIT_MAP_MPDU_3_CLR_MASK 0x00008000
|
|
#define CFG_RAW_BIT_MAP_MPDU_2_CLR_OFFSET 14
|
|
#define CFG_RAW_BIT_MAP_MPDU_2_CLR_MASK 0x00004000
|
|
#define CFG_RAW_BIT_MAP_MPDU_1_CLR_OFFSET 13
|
|
#define CFG_RAW_BIT_MAP_MPDU_1_CLR_MASK 0x00002000
|
|
#define CFG_RAW_BIT_MAP_MPDU_0_CLR_OFFSET 12
|
|
#define CFG_RAW_BIT_MAP_MPDU_0_CLR_MASK 0x00001000
|
|
#define MPDU_3_RAW_BIT_MAP_VLD_OFFSET 11
|
|
#define MPDU_3_RAW_BIT_MAP_VLD_MASK 0x00000800
|
|
#define MPDU_2_RAW_BIT_MAP_VLD_OFFSET 10
|
|
#define MPDU_2_RAW_BIT_MAP_VLD_MASK 0x00000400
|
|
#define MPDU_1_RAW_BIT_MAP_VLD_OFFSET 9
|
|
#define MPDU_1_RAW_BIT_MAP_VLD_MASK 0x00000200
|
|
#define MPDU_0_RAW_BIT_MAP_VLD_OFFSET 8
|
|
#define MPDU_0_RAW_BIT_MAP_VLD_MASK 0x00000100
|
|
#define MPDU_3_COLLECT_DONE_STS_OFFSET 7
|
|
#define MPDU_3_COLLECT_DONE_STS_MASK 0x00000080
|
|
#define MPDU_2_COLLECT_DONE_STS_OFFSET 6
|
|
#define MPDU_2_COLLECT_DONE_STS_MASK 0x00000040
|
|
#define MPDU_1_COLLECT_DONE_STS_OFFSET 5
|
|
#define MPDU_1_COLLECT_DONE_STS_MASK 0x00000020
|
|
#define MPDU_0_COLLECT_DONE_STS_OFFSET 4
|
|
#define MPDU_0_COLLECT_DONE_STS_MASK 0x00000010
|
|
#define CFG_BIT_MAP_HW_COLLECT_EN_OFFSET 0
|
|
#define CFG_BIT_MAP_HW_COLLECT_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_3_BTMP_0_ADDR 0x03a4
|
|
#define SACKC_MPDU_3_UDATA0_OFFSET 0
|
|
#define SACKC_MPDU_3_UDATA0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_3_BTMP_1_ADDR 0x03a8
|
|
#define SACKC_MPDU_3_UDATA1_OFFSET 0
|
|
#define SACKC_MPDU_3_UDATA1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_3_BTMP_2_ADDR 0x03ac
|
|
#define SACKC_MPDU_3_UDATA2_OFFSET 0
|
|
#define SACKC_MPDU_3_UDATA2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_3_BTMP_3_ADDR 0x03b0
|
|
#define SACKC_MPDU_3_UDATA3_OFFSET 0
|
|
#define SACKC_MPDU_3_UDATA3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_3_BTMP_4_ADDR 0x03b4
|
|
#define SACKC_MPDU_3_UDATA4_OFFSET 0
|
|
#define SACKC_MPDU_3_UDATA4_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_3_BTMP_5_ADDR 0x03b8
|
|
#define SACKC_MPDU_3_UDATA5_OFFSET 0
|
|
#define SACKC_MPDU_3_UDATA5_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_3_BTMP_6_ADDR 0x03bc
|
|
#define SACKC_MPDU_3_UDATA6_OFFSET 0
|
|
#define SACKC_MPDU_3_UDATA6_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_3_BTMP_7_ADDR 0x03c0
|
|
#define SACKC_MPDU_3_UDATA7_OFFSET 0
|
|
#define SACKC_MPDU_3_UDATA7_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_3_BTMP_8_ADDR 0x03c4
|
|
#define SACKC_MPDU_3_UDATA8_OFFSET 0
|
|
#define SACKC_MPDU_3_UDATA8_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_2_BTMP_0_ADDR 0x03c8
|
|
#define SACKC_MPDU_2_UDATA0_OFFSET 0
|
|
#define SACKC_MPDU_2_UDATA0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_2_BTMP_1_ADDR 0x03cc
|
|
#define SACKC_MPDU_2_UDATA1_OFFSET 0
|
|
#define SACKC_MPDU_2_UDATA1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_2_BTMP_2_ADDR 0x03d0
|
|
#define SACKC_MPDU_2_UDATA2_OFFSET 0
|
|
#define SACKC_MPDU_2_UDATA2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_2_BTMP_3_ADDR 0x03d4
|
|
#define SACKC_MPDU_2_UDATA3_OFFSET 0
|
|
#define SACKC_MPDU_2_UDATA3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_2_BTMP_4_ADDR 0x03d8
|
|
#define SACKC_MPDU_2_UDATA4_OFFSET 0
|
|
#define SACKC_MPDU_2_UDATA4_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_2_BTMP_5_ADDR 0x03dc
|
|
#define SACKC_MPDU_2_UDATA5_OFFSET 0
|
|
#define SACKC_MPDU_2_UDATA5_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_2_BTMP_6_ADDR 0x03e0
|
|
#define SACKC_MPDU_2_UDATA6_OFFSET 0
|
|
#define SACKC_MPDU_2_UDATA6_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_2_BTMP_7_ADDR 0x03e4
|
|
#define SACKC_MPDU_2_UDATA7_OFFSET 0
|
|
#define SACKC_MPDU_2_UDATA7_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_2_BTMP_8_ADDR 0x03e8
|
|
#define SACKC_MPDU_2_UDATA8_OFFSET 0
|
|
#define SACKC_MPDU_2_UDATA8_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_1_BTMP_0_ADDR 0x03ec
|
|
#define SACKC_MPDU_1_UDATA0_OFFSET 0
|
|
#define SACKC_MPDU_1_UDATA0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_1_BTMP_1_ADDR 0x03f0
|
|
#define SACKC_MPDU_1_UDATA1_OFFSET 0
|
|
#define SACKC_MPDU_1_UDATA1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_1_BTMP_2_ADDR 0x03f4
|
|
#define SACKC_MPDU_1_UDATA2_OFFSET 0
|
|
#define SACKC_MPDU_1_UDATA2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_1_BTMP_3_ADDR 0x03f8
|
|
#define SACKC_MPDU_1_UDATA3_OFFSET 0
|
|
#define SACKC_MPDU_1_UDATA3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_1_BTMP_4_ADDR 0x03fc
|
|
#define SACKC_MPDU_1_UDATA4_OFFSET 0
|
|
#define SACKC_MPDU_1_UDATA4_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_1_BTMP_5_ADDR 0x0400
|
|
#define SACKC_MPDU_1_UDATA5_OFFSET 0
|
|
#define SACKC_MPDU_1_UDATA5_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_1_BTMP_6_ADDR 0x0404
|
|
#define SACKC_MPDU_1_UDATA6_OFFSET 0
|
|
#define SACKC_MPDU_1_UDATA6_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_1_BTMP_7_ADDR 0x0408
|
|
#define SACKC_MPDU_1_UDATA7_OFFSET 0
|
|
#define SACKC_MPDU_1_UDATA7_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_1_BTMP_8_ADDR 0x040c
|
|
#define SACKC_MPDU_1_UDATA8_OFFSET 0
|
|
#define SACKC_MPDU_1_UDATA8_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_0_BTMP_0_ADDR 0x0410
|
|
#define SACKC_MPDU_0_UDATA0_OFFSET 0
|
|
#define SACKC_MPDU_0_UDATA0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_0_BTMP_1_ADDR 0x0414
|
|
#define SACKC_MPDU_0_UDATA1_OFFSET 0
|
|
#define SACKC_MPDU_0_UDATA1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_0_BTMP_2_ADDR 0x0418
|
|
#define SACKC_MPDU_0_UDATA2_OFFSET 0
|
|
#define SACKC_MPDU_0_UDATA2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_0_BTMP_3_ADDR 0x041c
|
|
#define SACKC_MPDU_0_UDATA3_OFFSET 0
|
|
#define SACKC_MPDU_0_UDATA3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_0_BTMP_4_ADDR 0x0420
|
|
#define SACKC_MPDU_0_UDATA4_OFFSET 0
|
|
#define SACKC_MPDU_0_UDATA4_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_0_BTMP_5_ADDR 0x0424
|
|
#define SACKC_MPDU_0_UDATA5_OFFSET 0
|
|
#define SACKC_MPDU_0_UDATA5_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_0_BTMP_6_ADDR 0x0428
|
|
#define SACKC_MPDU_0_UDATA6_OFFSET 0
|
|
#define SACKC_MPDU_0_UDATA6_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_0_BTMP_7_ADDR 0x042c
|
|
#define SACKC_MPDU_0_UDATA7_OFFSET 0
|
|
#define SACKC_MPDU_0_UDATA7_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_MPDU_0_BTMP_8_ADDR 0x0430
|
|
#define SACKC_MPDU_0_UDATA8_OFFSET 0
|
|
#define SACKC_MPDU_0_UDATA8_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_CTRL_ADDR 0x0434
|
|
#define CFG_SACKI_BITS_ALIGN_EN_OFFSET 31
|
|
#define CFG_SACKI_BITS_ALIGN_EN_MASK 0x80000000
|
|
#define CFG_SACKC_SIZE_OFFSET 24
|
|
#define CFG_SACKC_SIZE_MASK 0x7F000000
|
|
#define CFG_SOF_END_LID_OFFSET 16
|
|
#define CFG_SOF_END_LID_MASK 0x00FF0000
|
|
#define CFG_SOF_START_LID_OFFSET 8
|
|
#define CFG_SOF_START_LID_MASK 0x0000FF00
|
|
#define CFG_MPDU_3_COMPRESS_EN_OFFSET 7
|
|
#define CFG_MPDU_3_COMPRESS_EN_MASK 0x00000080
|
|
#define CFG_MPDU_2_COMPRESS_EN_OFFSET 6
|
|
#define CFG_MPDU_2_COMPRESS_EN_MASK 0x00000040
|
|
#define CFG_MPDU_1_COMPRESS_EN_OFFSET 5
|
|
#define CFG_MPDU_1_COMPRESS_EN_MASK 0x00000020
|
|
#define CFG_MPDU_0_COMPRESS_EN_OFFSET 4
|
|
#define CFG_MPDU_0_COMPRESS_EN_MASK 0x00000010
|
|
#define CFG_SOF_LID_FILTER_EN_OFFSET 1
|
|
#define CFG_SOF_LID_FILTER_EN_MASK 0x00000002
|
|
#define CFG_SOF_RRTF_FILTER_EN_OFFSET 0
|
|
#define CFG_SOF_RRTF_FILTER_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_SPEC_COMFORMANCE_0_ADDR 0x0438
|
|
#define CFG_LESS_BIT_MAP_10_CODE_LENGTH_OFFSET 24
|
|
#define CFG_LESS_BIT_MAP_10_CODE_LENGTH_MASK 0x07000000
|
|
#define CFG_LESS_BIT_MAP_10_CODE_VALUE_OFFSET 16
|
|
#define CFG_LESS_BIT_MAP_10_CODE_VALUE_MASK 0x003F0000
|
|
#define CFG_LESS_BIT_MAP_1_CODE_LENGTH_OFFSET 8
|
|
#define CFG_LESS_BIT_MAP_1_CODE_LENGTH_MASK 0x00000700
|
|
#define CFG_LESS_BIT_MAP_1_CODE_VALUE_OFFSET 0
|
|
#define CFG_LESS_BIT_MAP_1_CODE_VALUE_MASK 0x0000003F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_SPEC_COMFORMANCE_1_ADDR 0x043c
|
|
#define CFG_LESS_BIT_MAP_01_CODE_LENGTH_OFFSET 24
|
|
#define CFG_LESS_BIT_MAP_01_CODE_LENGTH_MASK 0x07000000
|
|
#define CFG_LESS_BIT_MAP_01_CODE_VALUE_OFFSET 16
|
|
#define CFG_LESS_BIT_MAP_01_CODE_VALUE_MASK 0x003F0000
|
|
#define CFG_LESS_BIT_MAP_0_CODE_LENGTH_OFFSET 8
|
|
#define CFG_LESS_BIT_MAP_0_CODE_LENGTH_MASK 0x00000700
|
|
#define CFG_LESS_BIT_MAP_0_CODE_VALUE_OFFSET 0
|
|
#define CFG_LESS_BIT_MAP_0_CODE_VALUE_MASK 0x0000003F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_SPEC_COMFORMANCE_2_ADDR 0x0440
|
|
#define CFG_LESS_BIT_MAP_000_CODE_LENGTH_OFFSET 24
|
|
#define CFG_LESS_BIT_MAP_000_CODE_LENGTH_MASK 0x07000000
|
|
#define CFG_LESS_BIT_MAP_000_CODE_VALUE_OFFSET 16
|
|
#define CFG_LESS_BIT_MAP_000_CODE_VALUE_MASK 0x003F0000
|
|
#define CFG_LESS_BIT_MAP_00_CODE_LENGTH_OFFSET 8
|
|
#define CFG_LESS_BIT_MAP_00_CODE_LENGTH_MASK 0x00000700
|
|
#define CFG_LESS_BIT_MAP_00_CODE_VALUE_OFFSET 0
|
|
#define CFG_LESS_BIT_MAP_00_CODE_VALUE_MASK 0x0000003F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_STS_0_ADDR 0x0444
|
|
#define SACKC_STS_MPDU_3_FC_LID_OFFSET 16
|
|
#define SACKC_STS_MPDU_3_FC_LID_MASK 0x00FF0000
|
|
#define SACKC_STS_MPDU_3_PB_NUM_OFFSET 0
|
|
#define SACKC_STS_MPDU_3_PB_NUM_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_STS_1_ADDR 0x0448
|
|
#define SACKC_STS_MPDU_3_RX_SOF_EKS_OFFSET 24
|
|
#define SACKC_STS_MPDU_3_RX_SOF_EKS_MASK 0x0F000000
|
|
#define SACKC_STS_MPDU_3_RX_SOF_TMI_OFFSET 16
|
|
#define SACKC_STS_MPDU_3_RX_SOF_TMI_MASK 0x001F0000
|
|
#define SACKC_STS_MPDU_3_RX_SOF_STEI_OFFSET 0
|
|
#define SACKC_STS_MPDU_3_RX_SOF_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_STS_2_ADDR 0x044c
|
|
#define SACKC_STS_MPDU_2_FC_LID_OFFSET 16
|
|
#define SACKC_STS_MPDU_2_FC_LID_MASK 0x00FF0000
|
|
#define SACKC_STS_MPDU_2_PB_NUM_OFFSET 0
|
|
#define SACKC_STS_MPDU_2_PB_NUM_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_STS_3_ADDR 0x0450
|
|
#define SACKC_STS_MPDU_2_RX_SOF_EKS_OFFSET 24
|
|
#define SACKC_STS_MPDU_2_RX_SOF_EKS_MASK 0x0F000000
|
|
#define SACKC_STS_MPDU_2_RX_SOF_TMI_OFFSET 16
|
|
#define SACKC_STS_MPDU_2_RX_SOF_TMI_MASK 0x001F0000
|
|
#define SACKC_STS_MPDU_2_RX_SOF_STEI_OFFSET 0
|
|
#define SACKC_STS_MPDU_2_RX_SOF_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_STS_4_ADDR 0x0454
|
|
#define SACKC_STS_MPDU_1_FC_LID_OFFSET 16
|
|
#define SACKC_STS_MPDU_1_FC_LID_MASK 0x00FF0000
|
|
#define SACKC_STS_MPDU_1_PB_NUM_OFFSET 0
|
|
#define SACKC_STS_MPDU_1_PB_NUM_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_STS_5_ADDR 0x0458
|
|
#define SACKC_STS_MPDU_1_RX_SOF_EKS_OFFSET 24
|
|
#define SACKC_STS_MPDU_1_RX_SOF_EKS_MASK 0x0F000000
|
|
#define SACKC_STS_MPDU_1_RX_SOF_TMI_OFFSET 16
|
|
#define SACKC_STS_MPDU_1_RX_SOF_TMI_MASK 0x001F0000
|
|
#define SACKC_STS_MPDU_1_RX_SOF_STEI_OFFSET 0
|
|
#define SACKC_STS_MPDU_1_RX_SOF_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_STS_6_ADDR 0x045c
|
|
#define SACKC_STS_MPDU_0_FC_LID_OFFSET 16
|
|
#define SACKC_STS_MPDU_0_FC_LID_MASK 0x00FF0000
|
|
#define SACKC_STS_MPDU_0_PB_NUM_OFFSET 0
|
|
#define SACKC_STS_MPDU_0_PB_NUM_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_STS_7_ADDR 0x0460
|
|
#define SACKC_STS_MPDU_0_RX_SOF_EKS_OFFSET 24
|
|
#define SACKC_STS_MPDU_0_RX_SOF_EKS_MASK 0x0F000000
|
|
#define SACKC_STS_MPDU_0_RX_SOF_TMI_OFFSET 16
|
|
#define SACKC_STS_MPDU_0_RX_SOF_TMI_MASK 0x001F0000
|
|
#define SACKC_STS_MPDU_0_RX_SOF_STEI_OFFSET 0
|
|
#define SACKC_STS_MPDU_0_RX_SOF_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_RESULT_0_ADDR 0x0464
|
|
#define SACKC_CDATA0_OFFSET 0
|
|
#define SACKC_CDATA0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_RESULT_1_ADDR 0x0468
|
|
#define SACKC_CDATA1_OFFSET 0
|
|
#define SACKC_CDATA1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_RESULT_2_ADDR 0x046c
|
|
#define SACKC_CDATA2_OFFSET 0
|
|
#define SACKC_CDATA2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_STS_8_ADDR 0x0470
|
|
#define SACKC_STS_MPDU_3_COMPRESS_LENGTH_OFFSET 16
|
|
#define SACKC_STS_MPDU_3_COMPRESS_LENGTH_MASK 0x007F0000
|
|
#define SACKC_STS_MPDU_3_COMPRESS_PB_NUM_OFFSET 0
|
|
#define SACKC_STS_MPDU_3_COMPRESS_PB_NUM_MASK 0x000001FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_STS_9_ADDR 0x0474
|
|
#define SACKC_STS_MPDU_2_COMPRESS_LENGTH_OFFSET 16
|
|
#define SACKC_STS_MPDU_2_COMPRESS_LENGTH_MASK 0x007F0000
|
|
#define SACKC_STS_MPDU_2_COMPRESS_PB_NUM_OFFSET 0
|
|
#define SACKC_STS_MPDU_2_COMPRESS_PB_NUM_MASK 0x000001FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_STS_10_ADDR 0x0478
|
|
#define SACKC_STS_MPDU_1_COMPRESS_LENGTH_OFFSET 16
|
|
#define SACKC_STS_MPDU_1_COMPRESS_LENGTH_MASK 0x007F0000
|
|
#define SACKC_STS_MPDU_1_COMPRESS_PB_NUM_OFFSET 0
|
|
#define SACKC_STS_MPDU_1_COMPRESS_PB_NUM_MASK 0x000001FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_STS_11_ADDR 0x047c
|
|
#define SACKC_STS_MPDU_0_COMPRESS_LENGTH_OFFSET 16
|
|
#define SACKC_STS_MPDU_0_COMPRESS_LENGTH_MASK 0x007F0000
|
|
#define SACKC_STS_MPDU_0_COMPRESS_PB_NUM_OFFSET 0
|
|
#define SACKC_STS_MPDU_0_COMPRESS_PB_NUM_MASK 0x000001FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_STS_12_ADDR 0x0480
|
|
#define SACKC_STS_MPDU_3_BUF_WR_IDX_OFFSET 8
|
|
#define SACKC_STS_MPDU_3_BUF_WR_IDX_MASK 0x0003FF00
|
|
#define SACKC_STS_MPDU_3_IN_RX_RING_OFFSET 0
|
|
#define SACKC_STS_MPDU_3_IN_RX_RING_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_STS_13_ADDR 0x0484
|
|
#define SACKC_STS_MPDU_2_BUF_WR_IDX_OFFSET 8
|
|
#define SACKC_STS_MPDU_2_BUF_WR_IDX_MASK 0x0003FF00
|
|
#define SACKC_STS_MPDU_2_IN_RX_RING_OFFSET 0
|
|
#define SACKC_STS_MPDU_2_IN_RX_RING_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_STS_14_ADDR 0x0488
|
|
#define SACKC_STS_MPDU_1_BUF_WR_IDX_OFFSET 8
|
|
#define SACKC_STS_MPDU_1_BUF_WR_IDX_MASK 0x0003FF00
|
|
#define SACKC_STS_MPDU_1_IN_RX_RING_OFFSET 0
|
|
#define SACKC_STS_MPDU_1_IN_RX_RING_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_STS_15_ADDR 0x048c
|
|
#define SACKC_STS_MPDU_0_BUF_WR_IDX_OFFSET 8
|
|
#define SACKC_STS_MPDU_0_BUF_WR_IDX_MASK 0x0003FF00
|
|
#define SACKC_STS_MPDU_0_IN_RX_RING_OFFSET 0
|
|
#define SACKC_STS_MPDU_0_IN_RX_RING_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACKC_COMPRESS_PB_NUM_CTRL_ADDR 0x0490
|
|
#define CFG_FORCE_SACKC_PB_NUM_EN_OFFSET 16
|
|
#define CFG_FORCE_SACKC_PB_NUM_EN_MASK 0x00010000
|
|
#define CFG_FORCE_SACKC_PB_NUM_OFFSET 0
|
|
#define CFG_FORCE_SACKC_PB_NUM_MASK 0x000001FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_RESP_SACK_FORCE_0_ADDR 0x0500
|
|
#define CFG_FORCE_GP_SACK_SACKT_OFFSET 24
|
|
#define CFG_FORCE_GP_SACK_SACKT_MASK 0xFF000000
|
|
#define CFG_FORCE_GP_SACK_MFSRESPMGMT_OFFSET 22
|
|
#define CFG_FORCE_GP_SACK_MFSRESPMGMT_MASK 0x00C00000
|
|
#define CFG_FORCE_GP_SACK_MFSRSPDATA_OFFSET 20
|
|
#define CFG_FORCE_GP_SACK_MFSRSPDATA_MASK 0x00300000
|
|
#define CFG_FORCE_GP_SACK_RRTF_OFFSET 19
|
|
#define CFG_FORCE_GP_SACK_RRTF_MASK 0x00080000
|
|
#define CFG_FORCE_GP_SACK_SVN_OFFSET 18
|
|
#define CFG_FORCE_GP_SACK_SVN_MASK 0x00040000
|
|
#define CFG_FORCE_GP_SACK_BDF_OFFSET 17
|
|
#define CFG_FORCE_GP_SACK_BDF_MASK 0x00020000
|
|
#define CFG_FORCE_GP_SACK_CFS_OFFSET 16
|
|
#define CFG_FORCE_GP_SACK_CFS_MASK 0x00010000
|
|
#define CFG_FORCE_GP_SACK_DTEI_OFFSET 8
|
|
#define CFG_FORCE_GP_SACK_DTEI_MASK 0x0000FF00
|
|
#define CFG_FORCE_GP_SACK_SNID_OFFSET 4
|
|
#define CFG_FORCE_GP_SACK_SNID_MASK 0x000000F0
|
|
#define CFG_FORCE_GP_SACK_ACCESS_OFFSET 3
|
|
#define CFG_FORCE_GP_SACK_ACCESS_MASK 0x00000008
|
|
#define CFG_FORCE_GP_SACK_DTAV_OFFSET 0
|
|
#define CFG_FORCE_GP_SACK_DTAV_MASK 0x00000007
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_RESP_SACK_FORCE_1_ADDR 0x0504
|
|
#define CFG_FORCE_GP_SACK_DATA_LOW_OFFSET 0
|
|
#define CFG_FORCE_GP_SACK_DATA_LOW_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_RESP_SACK_FORCE_2_ADDR 0x0508
|
|
#define CFG_FORCE_GP_SACK_DATA_HIGH_OFFSET 0
|
|
#define CFG_FORCE_GP_SACK_DATA_HIGH_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_RESP_SACK_FORCE_3_ADDR 0x050c
|
|
#define CFG_FORCE_GP_SACK_FCCS_AV_OFFSET 8
|
|
#define CFG_FORCE_GP_SACK_FCCS_AV_MASK 0xFFFFFF00
|
|
#define CFG_FORCE_GP_SACK_RRTL_OFFSET 4
|
|
#define CFG_FORCE_GP_SACK_RRTL_MASK 0x000000F0
|
|
#define CFG_FORCE_GP_SACK_RXWSZ_OFFSET 0
|
|
#define CFG_FORCE_GP_SACK_RXWSZ_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_RESP_SACK_FORCE_EN_ADDR 0x0510
|
|
#define CFG_FORCE_GP_SACK_FCCS_AV_EN_OFFSET 14
|
|
#define CFG_FORCE_GP_SACK_FCCS_AV_EN_MASK 0x00004000
|
|
#define CFG_FORCE_GP_SACK_RRTL_EN_OFFSET 13
|
|
#define CFG_FORCE_GP_SACK_RRTL_EN_MASK 0x00002000
|
|
#define CFG_FORCE_GP_SACK_RXWSZ_EN_OFFSET 12
|
|
#define CFG_FORCE_GP_SACK_RXWSZ_EN_MASK 0x00001000
|
|
#define CFG_FORCE_GP_SACK_SACKD_EN_OFFSET 11
|
|
#define CFG_FORCE_GP_SACK_SACKD_EN_MASK 0x00000800
|
|
#define CFG_FORCE_GP_SACK_SACKT_EN_OFFSET 10
|
|
#define CFG_FORCE_GP_SACK_SACKT_EN_MASK 0x00000400
|
|
#define CFG_FORCE_GP_SACK_MFSRESPMGMT_EN_OFFSET 9
|
|
#define CFG_FORCE_GP_SACK_MFSRESPMGMT_EN_MASK 0x00000200
|
|
#define CFG_FORCE_GP_SACK_MFSRSPDATA_EN_OFFSET 8
|
|
#define CFG_FORCE_GP_SACK_MFSRSPDATA_EN_MASK 0x00000100
|
|
#define CFG_FORCE_GP_SACK_RRTF_EN_OFFSET 7
|
|
#define CFG_FORCE_GP_SACK_RRTF_EN_MASK 0x00000080
|
|
#define CFG_FORCE_GP_SACK_SVN_EN_OFFSET 6
|
|
#define CFG_FORCE_GP_SACK_SVN_EN_MASK 0x00000040
|
|
#define CFG_FORCE_GP_SACK_BDF_EN_OFFSET 5
|
|
#define CFG_FORCE_GP_SACK_BDF_EN_MASK 0x00000020
|
|
#define CFG_FORCE_GP_SACK_CFS_EN_OFFSET 4
|
|
#define CFG_FORCE_GP_SACK_CFS_EN_MASK 0x00000010
|
|
#define CFG_FORCE_GP_SACK_DTEI_EN_OFFSET 3
|
|
#define CFG_FORCE_GP_SACK_DTEI_EN_MASK 0x00000008
|
|
#define CFG_FORCE_GP_SACK_SNID_EN_OFFSET 2
|
|
#define CFG_FORCE_GP_SACK_SNID_EN_MASK 0x00000004
|
|
#define CFG_FORCE_GP_SACK_ACCESS_EN_OFFSET 1
|
|
#define CFG_FORCE_GP_SACK_ACCESS_EN_MASK 0x00000002
|
|
#define CFG_FORCE_GP_SACK_DTAV_EN_OFFSET 0
|
|
#define CFG_FORCE_GP_SACK_DTAV_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_RESP_SACK_FORCE_4_ADDR 0x0514
|
|
#define CFG_HW_DEFAULT_GP_SACKT_OFFSET 0
|
|
#define CFG_HW_DEFAULT_GP_SACKT_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_RESP_SOUND_ACK_FORCE_0_ADDR 0x0520
|
|
#define CFG_FORCE_GP_SOUND_ACK_LID_OFFSET 24
|
|
#define CFG_FORCE_GP_SOUND_ACK_LID_MASK 0xFF000000
|
|
#define CFG_FORCE_GP_SOUND_ACK_DTEI_OFFSET 16
|
|
#define CFG_FORCE_GP_SOUND_ACK_DTEI_MASK 0x00FF0000
|
|
#define CFG_FORCE_GP_SOUND_ACK_STEI_OFFSET 8
|
|
#define CFG_FORCE_GP_SOUND_ACK_STEI_MASK 0x0000FF00
|
|
#define CFG_FORCE_GP_SOUND_ACK_SNID_OFFSET 4
|
|
#define CFG_FORCE_GP_SOUND_ACK_SNID_MASK 0x000000F0
|
|
#define CFG_FORCE_GP_SOUND_ACK_ACCESS_OFFSET 3
|
|
#define CFG_FORCE_GP_SOUND_ACK_ACCESS_MASK 0x00000008
|
|
#define CFG_FORCE_GP_SOUND_ACK_DT_AV_OFFSET 0
|
|
#define CFG_FORCE_GP_SOUND_ACK_DT_AV_MASK 0x00000007
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_RESP_SOUND_ACK_FORCE_1_ADDR 0x0524
|
|
#define CFG_FORCE_GP_SOUND_ACK_PPB_OFFSET 24
|
|
#define CFG_FORCE_GP_SOUND_ACK_PPB_MASK 0xFF000000
|
|
#define CFG_FORCE_GP_SOUND_ACK_RSVD_OFFSET 22
|
|
#define CFG_FORCE_GP_SOUND_ACK_RSVD_MASK 0x00C00000
|
|
#define CFG_FORCE_GP_SOUND_ACK_MPDUCNT_OFFSET 20
|
|
#define CFG_FORCE_GP_SOUND_ACK_MPDUCNT_MASK 0x00300000
|
|
#define CFG_FORCE_GP_SOUND_ACK_FL_AV_OFFSET 8
|
|
#define CFG_FORCE_GP_SOUND_ACK_FL_AV_MASK 0x000FFF00
|
|
#define CFG_FORCE_GP_SOUND_ACK_REQ_TM_OFFSET 5
|
|
#define CFG_FORCE_GP_SOUND_ACK_REQ_TM_MASK 0x000000E0
|
|
#define CFG_FORCE_GP_SOUND_ACK_SCF_OFFSET 4
|
|
#define CFG_FORCE_GP_SOUND_ACK_SCF_MASK 0x00000010
|
|
#define CFG_FORCE_GP_SOUND_ACK_SAF_OFFSET 3
|
|
#define CFG_FORCE_GP_SOUND_ACK_SAF_MASK 0x00000008
|
|
#define CFG_FORCE_GP_SOUND_ACK_BDF_OFFSET 2
|
|
#define CFG_FORCE_GP_SOUND_ACK_BDF_MASK 0x00000004
|
|
#define CFG_FORCE_GP_SOUND_ACK_PBSZ_OFFSET 1
|
|
#define CFG_FORCE_GP_SOUND_ACK_PBSZ_MASK 0x00000002
|
|
#define CFG_FORCE_GP_SOUND_ACK_CFS_OFFSET 0
|
|
#define CFG_FORCE_GP_SOUND_ACK_CFS_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_RESP_SOUND_ACK_FORCE_2_ADDR 0x0528
|
|
#define CFG_FORCE_GP_SOUND_ACK_SRC_OFFSET 24
|
|
#define CFG_FORCE_GP_SOUND_ACK_SRC_MASK 0xFF000000
|
|
#define CFG_FORCE_GP_SOUND_ACK_FCCS_AV_OFFSET 0
|
|
#define CFG_FORCE_GP_SOUND_ACK_FCCS_AV_MASK 0x00FFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_RESP_SOUND_ACK_FORCE_EN_ADDR 0x052c
|
|
#define CFG_FORCE_GP_SOUND_ACK_LID_EN_OFFSET 17
|
|
#define CFG_FORCE_GP_SOUND_ACK_LID_EN_MASK 0x00020000
|
|
#define CFG_FORCE_GP_SOUND_ACK_DTEI_EN_OFFSET 16
|
|
#define CFG_FORCE_GP_SOUND_ACK_DTEI_EN_MASK 0x00010000
|
|
#define CFG_FORCE_GP_SOUND_ACK_STEI_EN_OFFSET 15
|
|
#define CFG_FORCE_GP_SOUND_ACK_STEI_EN_MASK 0x00008000
|
|
#define CFG_FORCE_GP_SOUND_ACK_SNID_EN_OFFSET 14
|
|
#define CFG_FORCE_GP_SOUND_ACK_SNID_EN_MASK 0x00004000
|
|
#define CFG_FORCE_GP_SOUND_ACK_ACCESS_EN_OFFSET 13
|
|
#define CFG_FORCE_GP_SOUND_ACK_ACCESS_EN_MASK 0x00002000
|
|
#define CFG_FORCE_GP_SOUND_ACK_DT_AV_EN_OFFSET 12
|
|
#define CFG_FORCE_GP_SOUND_ACK_DT_AV_EN_MASK 0x00001000
|
|
#define CFG_FORCE_GP_SOUND_ACK_PPB_EN_OFFSET 11
|
|
#define CFG_FORCE_GP_SOUND_ACK_PPB_EN_MASK 0x00000800
|
|
#define CFG_FORCE_GP_SOUND_ACK_RSVD_EN_OFFSET 10
|
|
#define CFG_FORCE_GP_SOUND_ACK_RSVD_EN_MASK 0x00000400
|
|
#define CFG_FORCE_GP_SOUND_ACK_MPDUCNT_EN_OFFSET 9
|
|
#define CFG_FORCE_GP_SOUND_ACK_MPDUCNT_EN_MASK 0x00000200
|
|
#define CFG_FORCE_GP_SOUND_ACK_FL_AV_EN_OFFSET 8
|
|
#define CFG_FORCE_GP_SOUND_ACK_FL_AV_EN_MASK 0x00000100
|
|
#define CFG_FORCE_GP_SOUND_ACK_REQ_TM_EN_OFFSET 7
|
|
#define CFG_FORCE_GP_SOUND_ACK_REQ_TM_EN_MASK 0x00000080
|
|
#define CFG_FORCE_GP_SOUND_ACK_SCF_EN_OFFSET 6
|
|
#define CFG_FORCE_GP_SOUND_ACK_SCF_EN_MASK 0x00000040
|
|
#define CFG_FORCE_GP_SOUND_ACK_SAF_EN_OFFSET 5
|
|
#define CFG_FORCE_GP_SOUND_ACK_SAF_EN_MASK 0x00000020
|
|
#define CFG_FORCE_GP_SOUND_ACK_BDF_EN_OFFSET 4
|
|
#define CFG_FORCE_GP_SOUND_ACK_BDF_EN_MASK 0x00000010
|
|
#define CFG_FORCE_GP_SOUND_ACK_PBSZ_EN_OFFSET 3
|
|
#define CFG_FORCE_GP_SOUND_ACK_PBSZ_EN_MASK 0x00000008
|
|
#define CFG_FORCE_GP_SOUND_ACK_CFS_EN_OFFSET 2
|
|
#define CFG_FORCE_GP_SOUND_ACK_CFS_EN_MASK 0x00000004
|
|
#define CFG_FORCE_GP_SOUND_ACK_SRC_EN_OFFSET 1
|
|
#define CFG_FORCE_GP_SOUND_ACK_SRC_EN_MASK 0x00000002
|
|
#define CFG_FORCE_GP_SOUND_ACK_FCCS_AV_EN_OFFSET 0
|
|
#define CFG_FORCE_GP_SOUND_ACK_FCCS_AV_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_RESP_CTS_FORCE_0_ADDR 0x0530
|
|
#define CFG_FORCE_GP_CTS_LID_OFFSET 24
|
|
#define CFG_FORCE_GP_CTS_LID_MASK 0xFF000000
|
|
#define CFG_FORCE_GP_CTS_DTEI_OFFSET 16
|
|
#define CFG_FORCE_GP_CTS_DTEI_MASK 0x00FF0000
|
|
#define CFG_FORCE_GP_CTS_STEI_OFFSET 8
|
|
#define CFG_FORCE_GP_CTS_STEI_MASK 0x0000FF00
|
|
#define CFG_FORCE_GP_CTS_SNID_OFFSET 4
|
|
#define CFG_FORCE_GP_CTS_SNID_MASK 0x000000F0
|
|
#define CFG_FORCE_GP_CTS_ACCESS_OFFSET 3
|
|
#define CFG_FORCE_GP_CTS_ACCESS_MASK 0x00000008
|
|
#define CFG_FORCE_GP_CTS_DT_AV_OFFSET 0
|
|
#define CFG_FORCE_GP_CTS_DT_AV_MASK 0x00000007
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_RESP_CTS_FORCE_1_ADDR 0x0534
|
|
#define CFG_FORCE_GP_CTS_DUR_OFFSET 8
|
|
#define CFG_FORCE_GP_CTS_DUR_MASK 0x003FFF00
|
|
#define CFG_FORCE_GP_CTS_MCF_OFFSET 7
|
|
#define CFG_FORCE_GP_CTS_MCF_MASK 0x00000080
|
|
#define CFG_FORCE_GP_CTS_MNBF_OFFSET 6
|
|
#define CFG_FORCE_GP_CTS_MNBF_MASK 0x00000040
|
|
#define CFG_FORCE_GP_CTS_IGF_OFFSET 5
|
|
#define CFG_FORCE_GP_CTS_IGF_MASK 0x00000020
|
|
#define CFG_FORCE_GP_CTS_RTSF_OFFSET 4
|
|
#define CFG_FORCE_GP_CTS_RTSF_MASK 0x00000010
|
|
#define CFG_FORCE_GP_CTS_HP11DF_OFFSET 3
|
|
#define CFG_FORCE_GP_CTS_HP11DF_MASK 0x00000008
|
|
#define CFG_FORCE_GP_CTS_HP10DF_OFFSET 2
|
|
#define CFG_FORCE_GP_CTS_HP10DF_MASK 0x00000004
|
|
#define CFG_FORCE_GP_CTS_BDF_OFFSET 1
|
|
#define CFG_FORCE_GP_CTS_BDF_MASK 0x00000002
|
|
#define CFG_FORCE_GP_CTS_CFS_OFFSET 0
|
|
#define CFG_FORCE_GP_CTS_CFS_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_RESP_CTS_FORCE_2_ADDR 0x0538
|
|
#define CFG_FORCE_GP_CTS_FCCS_AV_OFFSET 0
|
|
#define CFG_FORCE_GP_CTS_FCCS_AV_MASK 0x00FFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_RESP_CTS_FORCE_EN_ADDR 0x053c
|
|
#define CFG_FORCE_GP_CTS_LID_EN_OFFSET 15
|
|
#define CFG_FORCE_GP_CTS_LID_EN_MASK 0x00008000
|
|
#define CFG_FORCE_GP_CTS_DTEI_EN_OFFSET 14
|
|
#define CFG_FORCE_GP_CTS_DTEI_EN_MASK 0x00004000
|
|
#define CFG_FORCE_GP_CTS_STEI_EN_OFFSET 13
|
|
#define CFG_FORCE_GP_CTS_STEI_EN_MASK 0x00002000
|
|
#define CFG_FORCE_GP_CTS_SNID_EN_OFFSET 12
|
|
#define CFG_FORCE_GP_CTS_SNID_EN_MASK 0x00001000
|
|
#define CFG_FORCE_GP_CTS_ACCESS_EN_OFFSET 11
|
|
#define CFG_FORCE_GP_CTS_ACCESS_EN_MASK 0x00000800
|
|
#define CFG_FORCE_GP_CTS_DT_AV_EN_OFFSET 10
|
|
#define CFG_FORCE_GP_CTS_DT_AV_EN_MASK 0x00000400
|
|
#define CFG_FORCE_GP_CTS_DUR_EN_OFFSET 9
|
|
#define CFG_FORCE_GP_CTS_DUR_EN_MASK 0x00000200
|
|
#define CFG_FORCE_GP_CTS_MCF_EN_OFFSET 8
|
|
#define CFG_FORCE_GP_CTS_MCF_EN_MASK 0x00000100
|
|
#define CFG_FORCE_GP_CTS_MNBF_EN_OFFSET 7
|
|
#define CFG_FORCE_GP_CTS_MNBF_EN_MASK 0x00000080
|
|
#define CFG_FORCE_GP_CTS_IGF_EN_OFFSET 6
|
|
#define CFG_FORCE_GP_CTS_IGF_EN_MASK 0x00000040
|
|
#define CFG_FORCE_GP_CTS_RTSF_EN_OFFSET 5
|
|
#define CFG_FORCE_GP_CTS_RTSF_EN_MASK 0x00000020
|
|
#define CFG_FORCE_GP_CTS_HP11DF_EN_OFFSET 4
|
|
#define CFG_FORCE_GP_CTS_HP11DF_EN_MASK 0x00000010
|
|
#define CFG_FORCE_GP_CTS_HP10DF_EN_OFFSET 3
|
|
#define CFG_FORCE_GP_CTS_HP10DF_EN_MASK 0x00000008
|
|
#define CFG_FORCE_GP_CTS_BDF_EN_OFFSET 2
|
|
#define CFG_FORCE_GP_CTS_BDF_EN_MASK 0x00000004
|
|
#define CFG_FORCE_GP_CTS_CFS_EN_OFFSET 1
|
|
#define CFG_FORCE_GP_CTS_CFS_EN_MASK 0x00000002
|
|
#define CFG_FORCE_GP_CTS_FCCS_AV_EN_OFFSET 0
|
|
#define CFG_FORCE_GP_CTS_FCCS_AV_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_LOCK_DBG_BUS_ADDR 0x0540
|
|
#define LOCK_DBG_BUS_OFFSET 0
|
|
#define LOCK_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_CTRL_0_ADDR 0x0600
|
|
#define CFG_DBG_RX_BUF_0_PTR_START_ADDR_OFFSET 0
|
|
#define CFG_DBG_RX_BUF_0_PTR_START_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_CTRL_1_ADDR 0x0604
|
|
#define CFG_DBG_RX_BUF_0_PTR_END_ADDR_OFFSET 0
|
|
#define CFG_DBG_RX_BUF_0_PTR_END_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_CTRL_2_ADDR 0x0608
|
|
#define CFG_DBG_RX_BUF_0_OFFSET_EACH_PB_OFFSET 0
|
|
#define CFG_DBG_RX_BUF_0_OFFSET_EACH_PB_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_CTRL_3_ADDR 0x0610
|
|
#define CFG_DBG_RX_BUF_1_PTR_START_ADDR_OFFSET 0
|
|
#define CFG_DBG_RX_BUF_1_PTR_START_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_CTRL_4_ADDR 0x0614
|
|
#define CFG_DBG_RX_BUF_1_PTR_END_ADDR_OFFSET 0
|
|
#define CFG_DBG_RX_BUF_1_PTR_END_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_CTRL_5_ADDR 0x0618
|
|
#define CFG_DBG_RX_BUF_1_OFFSET_EACH_PB_OFFSET 0
|
|
#define CFG_DBG_RX_BUF_1_OFFSET_EACH_PB_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_CTRL_6_ADDR 0x0620
|
|
#define CFG_DBG_RX_BUF_2_PTR_START_ADDR_OFFSET 0
|
|
#define CFG_DBG_RX_BUF_2_PTR_START_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_CTRL_7_ADDR 0x0624
|
|
#define CFG_DBG_RX_BUF_2_PTR_END_ADDR_OFFSET 0
|
|
#define CFG_DBG_RX_BUF_2_PTR_END_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_CTRL_8_ADDR 0x0628
|
|
#define CFG_DBG_RX_BUF_2_OFFSET_EACH_PB_OFFSET 0
|
|
#define CFG_DBG_RX_BUF_2_OFFSET_EACH_PB_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_CTRL_9_ADDR 0x0630
|
|
#define CFG_DBG_RX_BUF_3_PTR_START_ADDR_OFFSET 0
|
|
#define CFG_DBG_RX_BUF_3_PTR_START_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_CTRL_10_ADDR 0x0634
|
|
#define CFG_DBG_RX_BUF_3_PTR_END_ADDR_OFFSET 0
|
|
#define CFG_DBG_RX_BUF_3_PTR_END_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_CTRL_11_ADDR 0x0638
|
|
#define CFG_DBG_RX_BUF_3_OFFSET_EACH_PB_OFFSET 0
|
|
#define CFG_DBG_RX_BUF_3_OFFSET_EACH_PB_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_CTRL_12_ADDR 0x0640
|
|
#define CFG_DBG_RX_BUF_4_PTR_START_ADDR_OFFSET 0
|
|
#define CFG_DBG_RX_BUF_4_PTR_START_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_CTRL_13_ADDR 0x0644
|
|
#define CFG_DBG_RX_BUF_4_PTR_END_ADDR_OFFSET 0
|
|
#define CFG_DBG_RX_BUF_4_PTR_END_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_CTRL_14_ADDR 0x0648
|
|
#define CFG_DBG_RX_BUF_4_OFFSET_EACH_PB_OFFSET 0
|
|
#define CFG_DBG_RX_BUF_4_OFFSET_EACH_PB_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_INT_CTRL_0_ADDR 0x0650
|
|
#define MAC_RX_BUF_DBG_FAKE_INT_CLR_OFFSET 0
|
|
#define MAC_RX_BUF_DBG_FAKE_INT_CLR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_INT_CTRL_1_ADDR 0x0654
|
|
#define MAC_RX_BUF_DBG_FAKE_INT_EN_OFFSET 0
|
|
#define MAC_RX_BUF_DBG_FAKE_INT_EN_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_INT_CTRL_2_ADDR 0x0658
|
|
#define MAC_RX_BUF_DBG_FAKE_INT_STS_OFFSET 0
|
|
#define MAC_RX_BUF_DBG_FAKE_INT_STS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_DBG_INT_CTRL_3_ADDR 0x065c
|
|
#define MAC_RX_BUF_DBG_FAKE_INT_RAW_OFFSET 0
|
|
#define MAC_RX_BUF_DBG_FAKE_INT_RAW_MASK 0xFFFFFFFF
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|
|
|
//-----------------------------------
|
|
#define CFG_CFG_METER0_CTRL_ADDR 0x0700
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#define CFG_METER_TRG_CNT0_OFFSET 2
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#define CFG_METER_TRG_CNT0_MASK 0x003FFFFC
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#define CFG_METER_TRG0_OFFSET 1
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|
#define CFG_METER_TRG0_MASK 0x00000002
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#define CFG_METER_EN0_OFFSET 0
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#define CFG_METER_EN0_MASK 0x00000001
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|
|
//-----------------------------------
|
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#define CFG_CFG_METER0_DAT_ADDR 0x0704
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#define METER_SUM0_OFFSET 16
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#define METER_SUM0_MASK 0x3FFF0000
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#define CFG_METER_THSOLD0_OFFSET 0
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#define CFG_METER_THSOLD0_MASK 0x00003FFF
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|
|
//-----------------------------------
|
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#define CFG_CFG_METER1_CTRL_ADDR 0x0708
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#define CFG_METER_TRG_CNT1_OFFSET 2
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#define CFG_METER_TRG_CNT1_MASK 0x003FFFFC
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#define CFG_METER_TRG1_OFFSET 1
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#define CFG_METER_TRG1_MASK 0x00000002
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#define CFG_METER_EN1_OFFSET 0
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#define CFG_METER_EN1_MASK 0x00000001
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|
|
//-----------------------------------
|
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#define CFG_CFG_METER1_DAT_ADDR 0x070c
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#define METER_SUM1_OFFSET 16
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#define METER_SUM1_MASK 0x3FFF0000
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#define CFG_METER_THSOLD1_OFFSET 0
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#define CFG_METER_THSOLD1_MASK 0x00003FFF
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|
|
//-----------------------------------
|
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#define CFG_CFG_METER2_CTRL_ADDR 0x0710
|
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#define CFG_METER_TRG_CNT2_OFFSET 2
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#define CFG_METER_TRG_CNT2_MASK 0x003FFFFC
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#define CFG_METER_TRG2_OFFSET 1
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#define CFG_METER_TRG2_MASK 0x00000002
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#define CFG_METER_EN2_OFFSET 0
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#define CFG_METER_EN2_MASK 0x00000001
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|
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//-----------------------------------
|
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#define CFG_CFG_METER2_DAT_ADDR 0x0714
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#define METER_SUM2_OFFSET 16
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#define METER_SUM2_MASK 0x3FFF0000
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#define CFG_METER_THSOLD2_OFFSET 0
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#define CFG_METER_THSOLD2_MASK 0x00003FFF
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|
|
//-----------------------------------
|
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#define CFG_CFG_METER3_CTRL_ADDR 0x0718
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#define CFG_METER_TRG_CNT3_OFFSET 2
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#define CFG_METER_TRG_CNT3_MASK 0x003FFFFC
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|
#define CFG_METER_TRG3_OFFSET 1
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#define CFG_METER_TRG3_MASK 0x00000002
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#define CFG_METER_EN3_OFFSET 0
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#define CFG_METER_EN3_MASK 0x00000001
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|
|
//-----------------------------------
|
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#define CFG_CFG_METER3_DAT_ADDR 0x071c
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|
#define METER_SUM3_OFFSET 16
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#define METER_SUM3_MASK 0x3FFF0000
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#define CFG_METER_THSOLD3_OFFSET 0
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#define CFG_METER_THSOLD3_MASK 0x00003FFF
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|
|
//-----------------------------------
|
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#define CFG_CFG_METER4_CTRL_ADDR 0x0720
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|
#define CFG_METER_TRG_CNT4_OFFSET 2
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|
#define CFG_METER_TRG_CNT4_MASK 0x003FFFFC
|
|
#define CFG_METER_TRG4_OFFSET 1
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|
#define CFG_METER_TRG4_MASK 0x00000002
|
|
#define CFG_METER_EN4_OFFSET 0
|
|
#define CFG_METER_EN4_MASK 0x00000001
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|
|
|
//-----------------------------------
|
|
#define CFG_CFG_METER4_DAT_ADDR 0x0724
|
|
#define METER_SUM4_OFFSET 16
|
|
#define METER_SUM4_MASK 0x3FFF0000
|
|
#define CFG_METER_THSOLD4_OFFSET 0
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|
#define CFG_METER_THSOLD4_MASK 0x00003FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CFG_METER5_CTRL_ADDR 0x0728
|
|
#define CFG_METER_TRG_CNT5_OFFSET 2
|
|
#define CFG_METER_TRG_CNT5_MASK 0x003FFFFC
|
|
#define CFG_METER_TRG5_OFFSET 1
|
|
#define CFG_METER_TRG5_MASK 0x00000002
|
|
#define CFG_METER_EN5_OFFSET 0
|
|
#define CFG_METER_EN5_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_CFG_METER5_DAT_ADDR 0x072c
|
|
#define METER_SUM5_OFFSET 16
|
|
#define METER_SUM5_MASK 0x3FFF0000
|
|
#define CFG_METER_THSOLD5_OFFSET 0
|
|
#define CFG_METER_THSOLD5_MASK 0x00003FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CFG_METER6_CTRL_ADDR 0x0730
|
|
#define CFG_METER_TRG_CNT6_OFFSET 2
|
|
#define CFG_METER_TRG_CNT6_MASK 0x003FFFFC
|
|
#define CFG_METER_TRG6_OFFSET 1
|
|
#define CFG_METER_TRG6_MASK 0x00000002
|
|
#define CFG_METER_EN6_OFFSET 0
|
|
#define CFG_METER_EN6_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_CFG_METER6_DAT_ADDR 0x0734
|
|
#define METER_SUM6_OFFSET 16
|
|
#define METER_SUM6_MASK 0x3FFF0000
|
|
#define CFG_METER_THSOLD6_OFFSET 0
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|
#define CFG_METER_THSOLD6_MASK 0x00003FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CFG_METER7_CTRL_ADDR 0x0738
|
|
#define CFG_METER_TRG_CNT7_OFFSET 2
|
|
#define CFG_METER_TRG_CNT7_MASK 0x003FFFFC
|
|
#define CFG_METER_TRG7_OFFSET 1
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|
#define CFG_METER_TRG7_MASK 0x00000002
|
|
#define CFG_METER_EN7_OFFSET 0
|
|
#define CFG_METER_EN7_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_CFG_METER7_DAT_ADDR 0x073c
|
|
#define METER_SUM7_OFFSET 16
|
|
#define METER_SUM7_MASK 0x3FFF0000
|
|
#define CFG_METER_THSOLD7_OFFSET 0
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|
#define CFG_METER_THSOLD7_MASK 0x00003FFF
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|
|
|
//-----------------------------------
|
|
#define CFG_RX_PHASE_PROTECT_ADDR 0x0740
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|
#define CFG_RESP_SAME_PHASE_EN_OFFSET 5
|
|
#define CFG_RESP_SAME_PHASE_EN_MASK 0x00000020
|
|
#define CFG_ZC_IN_SEL_MAC_OFFSET 4
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|
#define CFG_ZC_IN_SEL_MAC_MASK 0x00000010
|
|
#define CFG_SG_RIFS_SEL_OFFSET 3
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|
#define CFG_SG_RIFS_SEL_MASK 0x00000008
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|
#define CFG_ZC_EN_BYPASS_MAC_OFFSET 2
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|
#define CFG_ZC_EN_BYPASS_MAC_MASK 0x00000004
|
|
#define CFG_RX_PHASE_FOR_PHY_PROTECT_EN_OFFSET 1
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|
#define CFG_RX_PHASE_FOR_PHY_PROTECT_EN_MASK 0x00000002
|
|
#define CFG_RX_PHASE_FOR_MAC_PROTECT_EN_OFFSET 0
|
|
#define CFG_RX_PHASE_FOR_MAC_PROTECT_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_SOLID_CNT_ADDR 0x0744
|
|
#define CFG_SOLID_LOW_CNT_OFFSET 0
|
|
#define CFG_SOLID_LOW_CNT_MASK 0x0000FFFF
|
|
#define CFG_SOLID_HIGH_CNT_OFFSET 0
|
|
#define CFG_SOLID_HIGH_CNT_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SACK_RAW_BIT_MAP_ADDR 0x0748
|
|
#define SACKC_RAW_BIT_MAP_A_WORD_OFFSET 0
|
|
#define SACKC_RAW_BIT_MAP_A_WORD_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_SYS_OPTION_CTRL_ADDR 0x074c
|
|
#define CFG_MAC_STANDARD_OFFSET 4
|
|
#define CFG_MAC_STANDARD_MASK 0x00000070
|
|
#define CFG_FORCE_MAC_STANDARD_OFFSET 3
|
|
#define CFG_FORCE_MAC_STANDARD_MASK 0x00000008
|
|
#define TX_RESP_EXP_ACK_SEL_OFFSET 2
|
|
#define TX_RESP_EXP_ACK_SEL_MASK 0x00000004
|
|
#define CFG_FD_FC_DONE_NTB_LOCK_OPT_OFFSET 1
|
|
#define CFG_FD_FC_DONE_NTB_LOCK_OPT_MASK 0x00000002
|
|
#define CFG_MPRX_RD_OPT_OFFSET 0
|
|
#define CFG_MPRX_RD_OPT_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC0_FIFO_DAT0_ADDR 0x0750
|
|
#define ZC0_FIFO_RDATA_OFFSET 0
|
|
#define ZC0_FIFO_RDATA_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC1_FIFO_DAT0_ADDR 0x0754
|
|
#define ZC1_FIFO_RDATA_OFFSET 0
|
|
#define ZC1_FIFO_RDATA_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC2_FIFO_DAT0_ADDR 0x0758
|
|
#define ZC2_FIFO_RDATA_OFFSET 0
|
|
#define ZC2_FIFO_RDATA_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC0_FIFO_DAT1_ADDR 0x075c
|
|
#define CFG_ZC0_NUM_TRG_OFFSET 14
|
|
#define CFG_ZC0_NUM_TRG_MASK 0x0001C000
|
|
#define ZC0_FIFO_FULL_OFFSET 13
|
|
#define ZC0_FIFO_FULL_MASK 0x00002000
|
|
#define ZC0_FIFO_EMPTY_OFFSET 12
|
|
#define ZC0_FIFO_EMPTY_MASK 0x00001000
|
|
#define ZC0_FIFO_DATA_NUM_OFFSET 8
|
|
#define ZC0_FIFO_DATA_NUM_MASK 0x00000F00
|
|
#define ZC0_FIFO_WR_PTR_OFFSET 4
|
|
#define ZC0_FIFO_WR_PTR_MASK 0x000000F0
|
|
#define ZC0_FIFO_RD_PTR_OFFSET 0
|
|
#define ZC0_FIFO_RD_PTR_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC1_FIFO_DAT1_ADDR 0x0760
|
|
#define CFG_ZC1_NUM_TRG_OFFSET 14
|
|
#define CFG_ZC1_NUM_TRG_MASK 0x0001C000
|
|
#define ZC1_FIFO_FULL_OFFSET 13
|
|
#define ZC1_FIFO_FULL_MASK 0x00002000
|
|
#define ZC1_FIFO_EMPTY_OFFSET 12
|
|
#define ZC1_FIFO_EMPTY_MASK 0x00001000
|
|
#define ZC1_FIFO_DATA_NUM_OFFSET 8
|
|
#define ZC1_FIFO_DATA_NUM_MASK 0x00000F00
|
|
#define ZC1_FIFO_WR_PTR_OFFSET 4
|
|
#define ZC1_FIFO_WR_PTR_MASK 0x000000F0
|
|
#define ZC1_FIFO_RD_PTR_OFFSET 0
|
|
#define ZC1_FIFO_RD_PTR_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC2_FIFO_DAT1_ADDR 0x0764
|
|
#define CFG_ZC2_NUM_TRG_OFFSET 14
|
|
#define CFG_ZC2_NUM_TRG_MASK 0x0001C000
|
|
#define ZC2_FIFO_FULL_OFFSET 13
|
|
#define ZC2_FIFO_FULL_MASK 0x00002000
|
|
#define ZC2_FIFO_EMPTY_OFFSET 12
|
|
#define ZC2_FIFO_EMPTY_MASK 0x00001000
|
|
#define ZC2_FIFO_DATA_NUM_OFFSET 8
|
|
#define ZC2_FIFO_DATA_NUM_MASK 0x00000F00
|
|
#define ZC2_FIFO_WR_PTR_OFFSET 4
|
|
#define ZC2_FIFO_WR_PTR_MASK 0x000000F0
|
|
#define ZC2_FIFO_RD_PTR_OFFSET 0
|
|
#define ZC2_FIFO_RD_PTR_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_FC_XOR_FACTOR_0_ADDR 0x0780
|
|
#define CFG_TX_FC_XOR_FACTOR_0_OFFSET 0
|
|
#define CFG_TX_FC_XOR_FACTOR_0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_FC_XOR_FACTOR_1_ADDR 0x0784
|
|
#define CFG_TX_FC_XOR_FACTOR_1_OFFSET 0
|
|
#define CFG_TX_FC_XOR_FACTOR_1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_FC_XOR_FACTOR_2_ADDR 0x0788
|
|
#define CFG_TX_FC_XOR_FACTOR_2_OFFSET 0
|
|
#define CFG_TX_FC_XOR_FACTOR_2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_FC_XOR_FACTOR_3_ADDR 0x078c
|
|
#define CFG_TX_FC_XOR_FACTOR_3_OFFSET 0
|
|
#define CFG_TX_FC_XOR_FACTOR_3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_PCS_VCS_TIMEOUT_VALUE_ADDR 0x079c
|
|
#define CFG_PCS_IDLE_TIMEOUT_VALUE_OFFSET 16
|
|
#define CFG_PCS_IDLE_TIMEOUT_VALUE_MASK 0xFFFF0000
|
|
#define CFG_VCS_BUSY_TIMEOUT_VALUE_OFFSET 0
|
|
#define CFG_VCS_BUSY_TIMEOUT_VALUE_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_PCS_VCS_TIMEOUT_CTRL_ADDR 0x07a0
|
|
#define CFG_PCS_BUSY_TIMEOUT_VALUE_OFFSET 16
|
|
#define CFG_PCS_BUSY_TIMEOUT_VALUE_MASK 0xFFFF0000
|
|
#define CFG_PCS_BUSY_CNT_EN_OFFSET 2
|
|
#define CFG_PCS_BUSY_CNT_EN_MASK 0x00000004
|
|
#define CFG_PCS_IDLE_CNT_EN_OFFSET 1
|
|
#define CFG_PCS_IDLE_CNT_EN_MASK 0x00000002
|
|
#define CFG_VCS_BUSY_CNT_EN_OFFSET 0
|
|
#define CFG_VCS_BUSY_CNT_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_TX_DATA0_ADDR 0x07a4
|
|
#define MAC_TX_DATA0_OFFSET 0
|
|
#define MAC_TX_DATA0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_TX_DATA1_ADDR 0x07a8
|
|
#define MAC_TX_DATA1_OFFSET 0
|
|
#define MAC_TX_DATA1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_TX_DATA2_ADDR 0x07ac
|
|
#define MAC_TX_DATA2_OFFSET 0
|
|
#define MAC_TX_DATA2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_TX_DATA3_ADDR 0x07b0
|
|
#define MAC_TX_DATA3_OFFSET 0
|
|
#define MAC_TX_DATA3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_TX_DATA4_ADDR 0x07b4
|
|
#define MAC_TX_DATA4_OFFSET 0
|
|
#define MAC_TX_DATA4_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_TX_DATA5_ADDR 0x07b8
|
|
#define MAC_TX_DATA5_OFFSET 0
|
|
#define MAC_TX_DATA5_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_HWQ_OPT_ADDR 0x07e0
|
|
#define CMD_PCS_BUSY_LAT_OFFSET 2
|
|
#define CMD_PCS_BUSY_LAT_MASK 0x00000004
|
|
#define CMD_VCS_BUSY_LAT_OFFSET 1
|
|
#define CMD_VCS_BUSY_LAT_MASK 0x00000002
|
|
#define CFG_START_RD_DESC_0_CHOS_OFFSET 0
|
|
#define CFG_START_RD_DESC_0_CHOS_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_MAC_DESIGN_OPT_CTRL_ADDR 0x07e4
|
|
#define CFG_TX_START_FILTER_EN_OFFSET 7
|
|
#define CFG_TX_START_FILTER_EN_MASK 0x00000080
|
|
#define CFG_TX_START_FILTER_CNT_MAX_OFFSET 2
|
|
#define CFG_TX_START_FILTER_CNT_MAX_MASK 0x0000007C
|
|
#define CFG_PHY_ERR_UPDATE_1_EN_OFFSET 1
|
|
#define CFG_PHY_ERR_UPDATE_1_EN_MASK 0x00000002
|
|
#define CFG_PHY_ERR_UPDATE_0_EN_OFFSET 0
|
|
#define CFG_PHY_ERR_UPDATE_0_EN_MASK 0x00000001
|
|
|
|
//HW module read/write macro
|
|
#define RGF_MAC_READ_REG(addr) SOC_READ_REG(RGF_MAC_BASEADDR + addr)
|
|
#define RGF_MAC_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_MAC_BASEADDR + addr,value)
|