70 lines
2.3 KiB
C
70 lines
2.3 KiB
C
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//-----------------------------------
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#define CFG_MAC_INT_ADDR 0x0000
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#define ZC2_REPORT_OFFSET 30
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#define ZC2_REPORT_MASK 0x40000000
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#define ZC1_REPORT_OFFSET 29
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#define ZC1_REPORT_MASK 0x20000000
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#define SCH_REQ_INT_OFFSET 28
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#define SCH_REQ_INT_MASK 0x10000000
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#define NTB_COMM_INT3_OFFSET 27
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#define NTB_COMM_INT3_MASK 0x08000000
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#define NTB_COMM_INT2_OFFSET 26
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#define NTB_COMM_INT2_MASK 0x04000000
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#define NTB_COMM_INT1_OFFSET 25
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#define NTB_COMM_INT1_MASK 0x02000000
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#define NTB_COMM_INT0_OFFSET 24
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#define NTB_COMM_INT0_MASK 0x01000000
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#define PHY_RX_TIMEOUT_OFFSET 23
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#define PHY_RX_TIMEOUT_MASK 0x00800000
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#define MAC_RX_ABORT_OFFSET 22
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#define MAC_RX_ABORT_MASK 0x00400000
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#define TX_RD_PB_BUF_ERR_OFFSET 21
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#define TX_RD_PB_BUF_ERR_MASK 0x00200000
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#define TX_RD_PB_DESC_ERR_OFFSET 20
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#define TX_RD_PB_DESC_ERR_MASK 0x00100000
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#define ZC_UP_BOUND_OFFSET 19
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#define ZC_UP_BOUND_MASK 0x00080000
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#define ZC_LOW_BOUND_OFFSET 18
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#define ZC_LOW_BOUND_MASK 0x00040000
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#define TX_AES_ERR_OFFSET 17
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#define TX_AES_ERR_MASK 0x00020000
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#define ZC_REPORT_OFFSET 16
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#define ZC_REPORT_MASK 0x00010000
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#define LOW_WATERMARK_OFFSET 15
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#define LOW_WATERMARK_MASK 0x00008000
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#define RX_PAYLOAD_OVERFLOW_OFFSET 14
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#define RX_PAYLOAD_OVERFLOW_MASK 0x00004000
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#define RX_DESC_OVERFLOW_OFFSET 13
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#define RX_DESC_OVERFLOW_MASK 0x00002000
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#define FC_RX_OFFSET 12
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#define FC_RX_MASK 0x00001000
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#define PB_RX_OFFSET 11
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#define PB_RX_MASK 0x00000800
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#define MPDU_RX_OFFSET 10
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#define MPDU_RX_MASK 0x00000400
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#define TX_UNDERRUN_OFFSET 9
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#define TX_UNDERRUN_MASK 0x00000200
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#define END_DESC_ERR_OFFSET 8
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#define END_DESC_ERR_MASK 0x00000100
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#define START_DESCERR_OFFSET 7
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#define START_DESCERR_MASK 0x00000080
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#define MAC_BUS_ERROR_OFFSET 6
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#define MAC_BUS_ERROR_MASK 0x00000040
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#define MPDU_TX_DONE_OFFSET 5
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#define MPDU_TX_DONE_MASK 0x00000020
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#define HWQ_STOPPED_OFFSET 4
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#define HWQ_STOPPED_MASK 0x00000010
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#define SCH_STOP_OFFSET 3
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#define SCH_STOP_MASK 0x00000008
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#define BEACON_RECEIVED_OFFSET 2
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#define BEACON_RECEIVED_MASK 0x00000004
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#define BEACON_MISSED_OFFSET 1
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#define BEACON_MISSED_MASK 0x00000002
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#define BEACON_ALERT_OFFSET 0
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#define BEACON_ALERT_MASK 0x00000001
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//HW module read/write macro
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#define RGF_MAC_INT_READ_REG(addr) SOC_READ_REG(RGF_MAC_INT_BASEADDR + addr)
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#define RGF_MAC_INT_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_MAC_INT_BASEADDR + addr,value)
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