76 lines
2.3 KiB
C
76 lines
2.3 KiB
C
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//-----------------------------------
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#define CFG_SMC_RVER_ADDR 0x0000
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#define SMC_RF_VER_OFFSET 0
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#define SMC_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SMC_CMD0_ADDR 0x0004
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#define SW_SMC_ENA_OFFSET 31
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#define SW_SMC_ENA_MASK 0x80000000
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#define SW_SMC_DLEN_OFFSET 16
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#define SW_SMC_DLEN_MASK 0x01FF0000
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#define SW_SMC_CMODE_OFFSET 8
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#define SW_SMC_CMODE_MASK 0x0000FF00
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#define SW_SMC_MODE_OFFSET 0
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#define SW_SMC_MODE_MASK 0x00000003
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//-----------------------------------
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#define CFG_SMC_CMD1_ADDR 0x0008
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#define SW_SMC_CMD_OFFSET 24
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#define SW_SMC_CMD_MASK 0xFF000000
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#define SW_SMC_ADDR_OFFSET 0
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#define SW_SMC_ADDR_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_SMC_CFG0_ADDR 0x000c
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#define SMC_DUMMY_NUM_OFFSET 20
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#define SMC_DUMMY_NUM_MASK 0x00300000
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#define SMC_CLK_SPI_DIV2_OFFSET 16
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#define SMC_CLK_SPI_DIV2_MASK 0x00010000
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#define SMC_SPI_QPI_MODE_OFFSET 12
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#define SMC_SPI_QPI_MODE_MASK 0x00001000
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#define SMC_CACHE_WR_MODE_OFFSET 8
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#define SMC_CACHE_WR_MODE_MASK 0x00000700
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#define SMC_CRYPT_MODE_OFFSET 4
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#define SMC_CRYPT_MODE_MASK 0x00000010
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#define SMC_CACHE_RD_MODE_OFFSET 0
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#define SMC_CACHE_RD_MODE_MASK 0x00000007
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//-----------------------------------
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#define CFG_SMC_CLK0_ADDR 0x0010
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#define CLK_SPI_SMC_ENA_OFFSET 4
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#define CLK_SPI_SMC_ENA_MASK 0x00000010
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#define CLK_SPI_SMC_DIV_OFFSET 0
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#define CLK_SPI_SMC_DIV_MASK 0x00000007
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//-----------------------------------
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#define CFG_SMC_STS0_ADDR 0x0018
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#define SMC_FSM_STATE_OFFSET 4
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#define SMC_FSM_STATE_MASK 0x000001F0
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#define SPI_FSM_STATE_OFFSET 0
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#define SPI_FSM_STATE_MASK 0x00000007
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//-----------------------------------
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#define CFG_SMC_RDATA_ADDR 0x001c
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#define SW_SMC_RDATA_OFFSET 0
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#define SW_SMC_RDATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SMC_WDATA_ADDR 0x0020
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#define SW_SMC_WDATA_OFFSET 0
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#define SW_SMC_WDATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SMC_DBG0_ADDR 0x0024
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#define SMC_CLK_FORCE_OUT_OFFSET 2
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#define SMC_CLK_FORCE_OUT_MASK 0x00000004
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#define SMC_TX_EDGE_SEL_OFFSET 1
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#define SMC_TX_EDGE_SEL_MASK 0x00000002
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#define SMC_RX_EDGE_SEL_OFFSET 0
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#define SMC_RX_EDGE_SEL_MASK 0x00000001
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//HW module read/write macro
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#define SMC_RF_READ_REG(addr) SOC_READ_REG(SMC_RF_BASEADDR + addr)
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#define SMC_RF_WRITE_REG(addr,value) SOC_WRITE_REG(SMC_RF_BASEADDR + addr,value)
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