147 lines
4.6 KiB
C
147 lines
4.6 KiB
C
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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/* os shim includes */
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#include "os_types.h"
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#include "apb.h"
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#include "hw_reg_api.h"
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void apb_enable(uint32_t module)
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{
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uint32_t tmp;
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uint32_t i = 0;
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volatile uint32_t delay = 100;
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volatile uint32_t addr_eb_reg, addr_rst_reg, module_eb, module_rst;
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if (module < APB_GLB_GEN0_END) {
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addr_eb_reg = CFG_APB_GLB_GEN0_ADDR;
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addr_rst_reg = CFG_APB_GLB_GRST0_ADDR;
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module_eb = module;
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module_rst = module;
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} else if (module < APB_GLB_GEN1_END) {
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addr_eb_reg = CFG_APB_GLB_GEN1_ADDR;
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addr_rst_reg = CFG_APB_GLB_GRST1_ADDR;
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module_eb = module - APB_GLB_GEN0_END;
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module_rst = module - APB_GLB_GEN0_END;
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} else if (module < APB_PWM_CTRL0_END) {
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addr_eb_reg = CFG_PWM_CTRL0_ADDR;
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addr_rst_reg = CFG_PWM_CTRL0_ADDR;
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module_eb = module - APB_GLB_GEN1_END;
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module_rst = APB_MODULE_PWM_NUM_EB2RST(module_eb);
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} else if(module < APB_LEDC1_END) {
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addr_eb_reg = CFG_LEDC1_CTRL_ADDR;
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addr_rst_reg = CFG_LEDC1_CTRL_ADDR;
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module_eb = module - APB_PWM_CTRL0_END;
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module_rst = module_eb - 1;
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} else {
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return;
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}
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//enable module;
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tmp = APB_REG_LITE0_READ_REG(addr_eb_reg);
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if(tmp & (1 << module_eb))
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return;
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tmp |= (1 << module_eb);
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APB_REG_LITE0_WRITE_REG(addr_eb_reg, tmp);
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//soft reset module;
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tmp = APB_REG_LITE0_READ_REG(addr_rst_reg);
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tmp |= (1 << module_rst);
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APB_REG_LITE0_WRITE_REG(addr_rst_reg, tmp);
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//delay
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for(i = 0; i < delay; i++);
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//reset done
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tmp = APB_REG_LITE0_READ_REG(addr_rst_reg);
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tmp &= ~(1 << module_rst);
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APB_REG_LITE0_WRITE_REG(addr_rst_reg, tmp);
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}
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void apb_disable(uint32_t module)
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{
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uint32_t tmp;
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uint32_t i = 0;
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volatile uint32_t delay = 100;
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volatile uint32_t addr_eb_reg, addr_rst_reg, module_eb, module_rst;
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if (module < APB_GLB_GEN0_END) {
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addr_eb_reg = CFG_APB_GLB_GEN0_ADDR;
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addr_rst_reg = CFG_APB_GLB_GRST0_ADDR;
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module_eb = module;
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module_rst = module;
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} else if (module < APB_GLB_GEN1_END) {
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addr_eb_reg = CFG_APB_GLB_GEN1_ADDR;
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addr_rst_reg = CFG_APB_GLB_GRST1_ADDR;
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module_eb = module - APB_GLB_GEN0_END;
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module_rst = module - APB_GLB_GEN0_END;
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} else if (module < APB_PWM_CTRL0_END) {
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addr_eb_reg = CFG_PWM_CTRL0_ADDR;
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addr_rst_reg = CFG_PWM_CTRL0_ADDR;
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module_eb = module - APB_GLB_GEN1_END;
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module_rst = APB_MODULE_PWM_NUM_EB2RST(module_eb);
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} else {
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return;
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}
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//disable module;
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tmp = APB_REG_LITE0_READ_REG(addr_eb_reg);
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if(!(tmp & (1 << module_eb)))
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return;
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tmp &= ~(1 << module_eb);
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APB_REG_LITE0_WRITE_REG(addr_eb_reg, tmp);
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//soft reset module;
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tmp = APB_REG_LITE0_READ_REG(addr_rst_reg);
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tmp |= (1 << module_rst);
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APB_REG_LITE0_WRITE_REG(addr_rst_reg, tmp);
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//delay
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for(i = 0; i < delay; i++);
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//reset done
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tmp = APB_REG_LITE0_READ_REG(addr_rst_reg);
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tmp &= ~(1 << module_rst);
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APB_REG_LITE0_WRITE_REG(addr_rst_reg, tmp);
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}
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void apb_glb_chip_rst()
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{
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uint32_t tmp;
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/* unlock protected register */
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tmp = APB_REG_LITE0_READ_REG(CFG_APB_REG_PROT_ADDR);
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REG_FIELD_SET(CHIP_CRITICAL_REG_PROT_PATTERN, tmp, 0x125a34);
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REG_FIELD_SET(CHIP_CRITICAL_REG_PROT_VALID, tmp, 1);
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APB_REG_LITE0_WRITE_REG(CFG_APB_REG_PROT_ADDR, tmp);
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tmp = APB_REG_LITE0_READ_REG(CFG_APB_GLB_CFG0_ADDR);
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REG_FIELD_SET(CHIP_SOFT_RST, tmp, 1);
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APB_REG_LITE0_WRITE_REG(CFG_APB_GLB_CFG0_ADDR, tmp);
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}
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void apb_sadc_start(bool_t en)
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{
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uint32_t tmp;
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tmp = APB_REG_LITE0_READ_REG(CFG_SADC_CTRL0_ADDR);
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if (en) {
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REG_FIELD_SET(SADC_GLB_START, tmp, 1);
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} else {
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REG_FIELD_SET(SADC_GLB_START, tmp, 0);
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}
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APB_REG_LITE0_WRITE_REG(CFG_SADC_CTRL0_ADDR, tmp);
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}
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