172 lines
3.8 KiB
C
172 lines
3.8 KiB
C
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "os_types.h"
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#include "sec_glb.h"
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#if 0
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#include "hw_reg_api.h"
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#include "sec_glb_rf.h"
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void sec_glb_enable(uint32_t module)
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{
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volatile uint32_t delay = 100;
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uint32_t i = 0;
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uint32_t tmp;
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//read moudle's status;
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tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_ENA_ADDR);
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if(tmp & (1<< module))
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return;
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//enable module;
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tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_ENA_ADDR);
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tmp |= (1<< module);
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SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_ENA_ADDR, tmp);
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//soft reset module;
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tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_RST_ADDR);
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tmp |= (1<< module);
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SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_RST_ADDR, tmp);
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//delay
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for(i = 0; i < delay; i++);
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//reset done
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tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_RST_ADDR);
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tmp &= ~(1<< module);
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SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_RST_ADDR, tmp);
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}
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void sec_glb_disable(uint32_t module)
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{
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uint32_t tmp;
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//disable module;
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tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_ENA_ADDR);
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tmp &= ~(1<< module);
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SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_ENA_ADDR, tmp);
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}
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void sec_glb_chip_rst()
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{
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uint32_t tmp;
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tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_RST_ADDR);
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REG_FIELD_SET(CHIP_SOFT_RST, tmp, 1);
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SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_RST_ADDR, tmp);
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}
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void sec_glb_core1_enable(void)
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{
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uint32_t tmp;
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tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_ENA_ADDR);
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REG_FIELD_SET(RV5_CORE1_EB, tmp, 1);
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SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_ENA_ADDR, tmp);
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}
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void sec_glb_core1_disable(void)
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{
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uint32_t tmp;
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tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_ENA_ADDR);
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REG_FIELD_SET(RV5_CORE1_EB, tmp, 0);
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SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_ENA_ADDR, tmp);
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}
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void sec_glb_core1_reset(uint8_t reset)
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{
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uint32_t tmp;
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tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_RST_ADDR);
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REG_FIELD_SET(RV5_CORE1_SOFT_RST_P, tmp, reset);
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SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_RST_ADDR, tmp);
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}
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void sec_glb_core1_set_start(uint32_t addr)
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{
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uint32_t tmp;
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tmp = SEC_GLB_RF_READ_REG(CFG_CPU1_START_PC_ADDR);
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REG_FIELD_SET(CORE1_START_PC, tmp, addr);
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SEC_GLB_RF_WRITE_REG(CFG_CPU1_START_PC_ADDR, tmp);
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}
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void sec_glb_core1_branch_pred_enable(bool_t enable)
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{
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uint32_t tmp;
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tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_ENA_ADDR);
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REG_FIELD_SET(RV5_CORE1_BTB_EB, tmp, enable);
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SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_ENA_ADDR, tmp);
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}
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void sec_glb_mtx_mst_acc(uint8_t master, uint8_t slave, bool_t enable)
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{
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uint32_t tmp;
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tmp = SEC_GLB_RF_READ_REG(CFG_MTX_MST0_ACC_ADDR + master * 4);
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if(enable)
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tmp |= 1 << slave;
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else
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tmp &= ~(1 << slave);
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SEC_GLB_RF_WRITE_REG(CFG_MTX_MST0_ACC_ADDR + master * 4, tmp);
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}
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#endif
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void sec_glb_enable(uint32_t module)
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{
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}
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void sec_glb_disable(uint32_t module)
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{
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}
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void sec_glb_core1_reset(uint8_t reset)
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{
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}
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void sec_glb_core1_set_start(uint32_t addr)
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{
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}
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void sec_glb_core1_disable(void)
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{
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}
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void sec_glb_core1_enable(void)
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{
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}
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void sec_glb_core1_branch_pred_enable(bool_t enable)
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{
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}
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void sec_glb_mtx_mst_acc(uint8_t master, uint8_t slave, bool_t enable)
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{
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}
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