1173 lines
45 KiB
C
Executable File
1173 lines
45 KiB
C
Executable File
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//-----------------------------------
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#define CFG_DMC_REG_RVER_ADDR 0x0
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#define DMC_RF_VER_OFFSET 0
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#define DMC_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DMC_RST_CFG_ADDR 0x4
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#define ARBIT_SOFT_RST_OFFSET 1
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#define ARBIT_SOFT_RST_MASK 0x00000002
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#define DMC_CHN_SOFT_RST_OFFSET 0
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#define DMC_CHN_SOFT_RST_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMC_INF_CFG_ADDR 0x8
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#define CHN7_MASK_QUEUE_OFFSET 24
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#define CHN7_MASK_QUEUE_MASK 0xFF000000
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#define CHN4_MASK_QUEUE_OFFSET 16
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#define CHN4_MASK_QUEUE_MASK 0x00FF0000
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#define CHN3_MASK_QUEUE_OFFSET 8
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#define CHN3_MASK_QUEUE_MASK 0x0000FF00
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#define DMC_TOTAL_SIZE_OFFSET 4
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#define DMC_TOTAL_SIZE_MASK 0x000000F0
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#define RX_MEM_CLK_FRC_ON_OFFSET 1
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#define RX_MEM_CLK_FRC_ON_MASK 0x00000002
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#define TX_MEM_CLK_FRC_ON_OFFSET 0
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#define TX_MEM_CLK_FRC_ON_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMC_TIMEOUT_CNT_DIV_ADDR 0xC
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#define TIMEOUT_WR_CNT_DIV_OFFSET 8
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#define TIMEOUT_WR_CNT_DIV_MASK 0x0000FF00
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#define TIMEOUT_RD_CNT_DIV_OFFSET 0
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#define TIMEOUT_RD_CNT_DIV_MASK 0x000000FF
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//-----------------------------------
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#define CFG_DMC_INF_DBG_BUS0_ADDR 0x10
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#define DMC_INF_DBG_BUS0_OFFSET 0
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#define DMC_INF_DBG_BUS0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMC_INF_DBG_BUS1_ADDR 0x14
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#define DMC_INF_DBG_BUS1_OFFSET 0
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#define DMC_INF_DBG_BUS1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMC_INF_DBG_BUS2_ADDR 0x18
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#define DMC_INF_DBG_BUS2_OFFSET 0
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#define DMC_INF_DBG_BUS2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DDR_PAD_WPU_CFG_ADDR 0x20
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#define DDR_DUMMY1_WPU_OFFSET 23
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#define DDR_DUMMY1_WPU_MASK 0x00800000
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#define DDR_DUMMY0_WPU_OFFSET 22
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#define DDR_DUMMY0_WPU_MASK 0x00400000
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#define DDR_CLK1_WPU_OFFSET 21
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#define DDR_CLK1_WPU_MASK 0x00200000
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#define DDR_CLK0_WPU_OFFSET 20
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#define DDR_CLK0_WPU_MASK 0x00100000
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#define DDR_CEN1_WPU_OFFSET 19
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#define DDR_CEN1_WPU_MASK 0x00080000
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#define DDR_CEN0_WPU_OFFSET 18
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#define DDR_CEN0_WPU_MASK 0x00040000
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#define DDR_DQS1_WPU_OFFSET 17
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#define DDR_DQS1_WPU_MASK 0x00020000
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#define DDR_DQS0_WPU_OFFSET 16
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#define DDR_DQS0_WPU_MASK 0x00010000
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#define DDR_DQ15_WPU_OFFSET 15
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#define DDR_DQ15_WPU_MASK 0x00008000
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#define DDR_DQ14_WPU_OFFSET 14
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#define DDR_DQ14_WPU_MASK 0x00004000
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#define DDR_DQ13_WPU_OFFSET 13
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#define DDR_DQ13_WPU_MASK 0x00002000
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#define DDR_DQ12_WPU_OFFSET 12
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#define DDR_DQ12_WPU_MASK 0x00001000
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#define DDR_DQ11_WPU_OFFSET 11
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#define DDR_DQ11_WPU_MASK 0x00000800
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#define DDR_DQ10_WPU_OFFSET 10
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#define DDR_DQ10_WPU_MASK 0x00000400
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#define DDR_DQ9_WPU_OFFSET 9
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#define DDR_DQ9_WPU_MASK 0x00000200
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#define DDR_DQ8_WPU_OFFSET 8
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#define DDR_DQ8_WPU_MASK 0x00000100
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#define DDR_DQ7_WPU_OFFSET 7
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#define DDR_DQ7_WPU_MASK 0x00000080
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#define DDR_DQ6_WPU_OFFSET 6
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#define DDR_DQ6_WPU_MASK 0x00000040
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#define DDR_DQ5_WPU_OFFSET 5
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#define DDR_DQ5_WPU_MASK 0x00000020
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#define DDR_DQ4_WPU_OFFSET 4
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#define DDR_DQ4_WPU_MASK 0x00000010
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#define DDR_DQ3_WPU_OFFSET 3
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#define DDR_DQ3_WPU_MASK 0x00000008
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#define DDR_DQ2_WPU_OFFSET 2
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#define DDR_DQ2_WPU_MASK 0x00000004
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#define DDR_DQ1_WPU_OFFSET 1
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#define DDR_DQ1_WPU_MASK 0x00000002
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#define DDR_DQ0_WPU_OFFSET 0
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#define DDR_DQ0_WPU_MASK 0x00000001
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//-----------------------------------
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#define CFG_DDR_PAD_WPD_CFG_ADDR 0x24
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#define DDR_DUMMY1_WPD_OFFSET 23
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#define DDR_DUMMY1_WPD_MASK 0x00800000
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#define DDR_DUMMY0_WPD_OFFSET 22
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#define DDR_DUMMY0_WPD_MASK 0x00400000
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#define DDR_CLK1_WPD_OFFSET 21
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#define DDR_CLK1_WPD_MASK 0x00200000
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#define DDR_CLK0_WPD_OFFSET 20
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#define DDR_CLK0_WPD_MASK 0x00100000
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#define DDR_CEN1_WPD_OFFSET 19
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#define DDR_CEN1_WPD_MASK 0x00080000
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#define DDR_CEN0_WPD_OFFSET 18
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#define DDR_CEN0_WPD_MASK 0x00040000
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#define DDR_DQS1_WPD_OFFSET 17
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#define DDR_DQS1_WPD_MASK 0x00020000
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#define DDR_DQS0_WPD_OFFSET 16
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#define DDR_DQS0_WPD_MASK 0x00010000
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#define DDR_DQ15_WPD_OFFSET 15
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#define DDR_DQ15_WPD_MASK 0x00008000
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#define DDR_DQ14_WPD_OFFSET 14
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#define DDR_DQ14_WPD_MASK 0x00004000
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#define DDR_DQ13_WPD_OFFSET 13
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#define DDR_DQ13_WPD_MASK 0x00002000
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#define DDR_DQ12_WPD_OFFSET 12
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#define DDR_DQ12_WPD_MASK 0x00001000
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#define DDR_DQ11_WPD_OFFSET 11
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#define DDR_DQ11_WPD_MASK 0x00000800
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#define DDR_DQ10_WPD_OFFSET 10
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#define DDR_DQ10_WPD_MASK 0x00000400
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#define DDR_DQ9_WPD_OFFSET 9
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#define DDR_DQ9_WPD_MASK 0x00000200
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#define DDR_DQ8_WPD_OFFSET 8
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#define DDR_DQ8_WPD_MASK 0x00000100
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#define DDR_DQ7_WPD_OFFSET 7
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#define DDR_DQ7_WPD_MASK 0x00000080
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#define DDR_DQ6_WPD_OFFSET 6
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#define DDR_DQ6_WPD_MASK 0x00000040
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#define DDR_DQ5_WPD_OFFSET 5
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#define DDR_DQ5_WPD_MASK 0x00000020
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#define DDR_DQ4_WPD_OFFSET 4
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#define DDR_DQ4_WPD_MASK 0x00000010
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#define DDR_DQ3_WPD_OFFSET 3
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#define DDR_DQ3_WPD_MASK 0x00000008
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#define DDR_DQ2_WPD_OFFSET 2
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#define DDR_DQ2_WPD_MASK 0x00000004
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#define DDR_DQ1_WPD_OFFSET 1
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#define DDR_DQ1_WPD_MASK 0x00000002
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#define DDR_DQ0_WPD_OFFSET 0
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#define DDR_DQ0_WPD_MASK 0x00000001
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//-----------------------------------
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#define CFG_DDR_PAD_DRV_CFG0_ADDR 0x28
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#define DDR_DQ15_DRV_OFFSET 30
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#define DDR_DQ15_DRV_MASK 0xC0000000
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#define DDR_DQ14_DRV_OFFSET 28
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#define DDR_DQ14_DRV_MASK 0x30000000
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#define DDR_DQ13_DRV_OFFSET 26
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#define DDR_DQ13_DRV_MASK 0x0C000000
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#define DDR_DQ12_DRV_OFFSET 24
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#define DDR_DQ12_DRV_MASK 0x03000000
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#define DDR_DQ11_DRV_OFFSET 22
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#define DDR_DQ11_DRV_MASK 0x00C00000
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#define DDR_DQ10_DRV_OFFSET 20
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#define DDR_DQ10_DRV_MASK 0x00300000
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#define DDR_DQ9_DRV_OFFSET 18
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#define DDR_DQ9_DRV_MASK 0x000C0000
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#define DDR_DQ8_DRV_OFFSET 16
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#define DDR_DQ8_DRV_MASK 0x00030000
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#define DDR_DQ7_DRV_OFFSET 14
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#define DDR_DQ7_DRV_MASK 0x0000C000
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#define DDR_DQ6_DRV_OFFSET 12
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#define DDR_DQ6_DRV_MASK 0x00003000
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#define DDR_DQ5_DRV_OFFSET 10
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#define DDR_DQ5_DRV_MASK 0x00000C00
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#define DDR_DQ4_DRV_OFFSET 8
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#define DDR_DQ4_DRV_MASK 0x00000300
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#define DDR_DQ3_DRV_OFFSET 6
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#define DDR_DQ3_DRV_MASK 0x000000C0
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#define DDR_DQ2_DRV_OFFSET 4
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#define DDR_DQ2_DRV_MASK 0x00000030
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#define DDR_DQ1_DRV_OFFSET 2
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#define DDR_DQ1_DRV_MASK 0x0000000C
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#define DDR_DQ0_DRV_OFFSET 0
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#define DDR_DQ0_DRV_MASK 0x00000003
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//-----------------------------------
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#define CFG_DDR_PAD_DRV_CFG1_ADDR 0x2C
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#define DDR_DUMMY1_DRV_OFFSET 14
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#define DDR_DUMMY1_DRV_MASK 0x0000C000
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#define DDR_DUMMY0_DRV_OFFSET 12
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#define DDR_DUMMY0_DRV_MASK 0x00003000
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#define DDR_CLK1_DRV_OFFSET 10
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#define DDR_CLK1_DRV_MASK 0x00000C00
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#define DDR_CLK0_DRV_OFFSET 8
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#define DDR_CLK0_DRV_MASK 0x00000300
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#define DDR_CEN1_DRV_OFFSET 6
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#define DDR_CEN1_DRV_MASK 0x000000C0
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#define DDR_CEN0_DRV_OFFSET 4
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#define DDR_CEN0_DRV_MASK 0x00000030
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#define DDR_DQS1_DRV_OFFSET 2
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#define DDR_DQS1_DRV_MASK 0x0000000C
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#define DDR_DQS0_DRV_OFFSET 0
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#define DDR_DQS0_DRV_MASK 0x00000003
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//-----------------------------------
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#define CFG_SDR_PAD_WPU_CFG_ADDR 0x30
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#define SDR_SPI_CLK_WPU_OFFSET 5
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#define SDR_SPI_CLK_WPU_MASK 0x00000020
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#define SDR_SPI_CS_WPU_OFFSET 4
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#define SDR_SPI_CS_WPU_MASK 0x00000010
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#define SDR_SPI_SIO3_WPU_OFFSET 3
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#define SDR_SPI_SIO3_WPU_MASK 0x00000008
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#define SDR_SPI_SIO2_WPU_OFFSET 2
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#define SDR_SPI_SIO2_WPU_MASK 0x00000004
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#define SDR_SPI_SIO1_WPU_OFFSET 1
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#define SDR_SPI_SIO1_WPU_MASK 0x00000002
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#define SDR_SPI_SIO0_WPU_OFFSET 0
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#define SDR_SPI_SIO0_WPU_MASK 0x00000001
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//-----------------------------------
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#define CFG_SDR_PAD_WPD_CFG_ADDR 0x34
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#define SDR_SPI_CLK_WPD_OFFSET 5
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#define SDR_SPI_CLK_WPD_MASK 0x00000020
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#define SDR_SPI_CS_WPD_OFFSET 4
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#define SDR_SPI_CS_WPD_MASK 0x00000010
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#define SDR_SPI_SIO3_WPD_OFFSET 3
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#define SDR_SPI_SIO3_WPD_MASK 0x00000008
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#define SDR_SPI_SIO2_WPD_OFFSET 2
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#define SDR_SPI_SIO2_WPD_MASK 0x00000004
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#define SDR_SPI_SIO1_WPD_OFFSET 1
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#define SDR_SPI_SIO1_WPD_MASK 0x00000002
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#define SDR_SPI_SIO0_WPD_OFFSET 0
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#define SDR_SPI_SIO0_WPD_MASK 0x00000001
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//-----------------------------------
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#define CFG_SDR_PAD_DRV_CFG_ADDR 0x38
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#define SDR_SPI_CLK_DRV_OFFSET 10
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#define SDR_SPI_CLK_DRV_MASK 0x00000C00
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#define SDR_SPI_CS_DRV_OFFSET 8
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#define SDR_SPI_CS_DRV_MASK 0x00000300
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#define SDR_SPI_SIO3_DRV_OFFSET 6
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#define SDR_SPI_SIO3_DRV_MASK 0x000000C0
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#define SDR_SPI_SIO2_DRV_OFFSET 4
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#define SDR_SPI_SIO2_DRV_MASK 0x00000030
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#define SDR_SPI_SIO1_DRV_OFFSET 2
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#define SDR_SPI_SIO1_DRV_MASK 0x0000000C
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#define SDR_SPI_SIO0_DRV_OFFSET 0
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#define SDR_SPI_SIO0_DRV_MASK 0x00000003
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//-----------------------------------
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#define CFG_DMC_PAD_SEL0_ADDR 0x3C
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#define DQ7_PAD_SEL_OFFSET 20
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#define DQ7_PAD_SEL_MASK 0x00300000
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#define DQ6_PAD_SEL_OFFSET 18
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#define DQ6_PAD_SEL_MASK 0x000C0000
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#define DQ5_PAD_SEL_OFFSET 16
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#define DQ5_PAD_SEL_MASK 0x00030000
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#define DQ4_PAD_SEL_OFFSET 14
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#define DQ4_PAD_SEL_MASK 0x0000C000
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#define DQ3_PAD_SEL_OFFSET 12
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#define DQ3_PAD_SEL_MASK 0x00003000
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#define DQ2_PAD_SEL_OFFSET 10
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#define DQ2_PAD_SEL_MASK 0x00000C00
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#define DQ1_PAD_SEL_OFFSET 8
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#define DQ1_PAD_SEL_MASK 0x00000300
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#define DQ0_PAD_SEL_OFFSET 6
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#define DQ0_PAD_SEL_MASK 0x000000C0
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#define DQS0_PAD_SEL_OFFSET 4
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#define DQS0_PAD_SEL_MASK 0x00000030
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#define CEN0_PAD_SEL_OFFSET 2
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#define CEN0_PAD_SEL_MASK 0x0000000C
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#define CLK0_PAD_SEL_OFFSET 0
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#define CLK0_PAD_SEL_MASK 0x00000003
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//-----------------------------------
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#define CFG_DMC_PAD_SEL1_ADDR 0x40
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#define DUMMY1_PAD_SEL_OFFSET 24
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#define DUMMY1_PAD_SEL_MASK 0x03000000
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#define DUMMY0_PAD_SEL_OFFSET 22
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#define DUMMY0_PAD_SEL_MASK 0x00C00000
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#define DQ15_PAD_SEL_OFFSET 20
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#define DQ15_PAD_SEL_MASK 0x00300000
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#define DQ14_PAD_SEL_OFFSET 18
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#define DQ14_PAD_SEL_MASK 0x000C0000
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#define DQ13_PAD_SEL_OFFSET 16
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#define DQ13_PAD_SEL_MASK 0x00030000
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#define DQ12_PAD_SEL_OFFSET 14
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#define DQ12_PAD_SEL_MASK 0x0000C000
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#define DQ11_PAD_SEL_OFFSET 12
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#define DQ11_PAD_SEL_MASK 0x00003000
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#define DQ10_PAD_SEL_OFFSET 10
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#define DQ10_PAD_SEL_MASK 0x00000C00
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#define DQ9_PAD_SEL_OFFSET 8
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#define DQ9_PAD_SEL_MASK 0x00000300
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#define DQ8_PAD_SEL_OFFSET 6
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#define DQ8_PAD_SEL_MASK 0x000000C0
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#define DQS1_PAD_SEL_OFFSET 4
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#define DQS1_PAD_SEL_MASK 0x00000030
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#define CEN1_PAD_SEL_OFFSET 2
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#define CEN1_PAD_SEL_MASK 0x0000000C
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#define CLK1_PAD_SEL_OFFSET 0
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#define CLK1_PAD_SEL_MASK 0x00000003
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//-----------------------------------
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#define CFG_DMC_EXSIZE_INFO_WORD0_ADDR 0x50
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#define EXSIZE_INFO_REG0_OFFSET 0
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#define EXSIZE_INFO_REG0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMC_EXSIZE_INFO_WORD1_ADDR 0x54
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#define EXSIZE_INFO_REG1_OFFSET 0
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#define EXSIZE_INFO_REG1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_RGMII_RX_DL_CFG_ADDR 0x58
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#define RGMII_RX_DL_EB_OFFSET 8
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#define RGMII_RX_DL_EB_MASK 0x00000100
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#define RGMII_RX_DL_CFG_DATA_OFFSET 0
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#define RGMII_RX_DL_CFG_DATA_MASK 0x000000FF
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//-----------------------------------
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#define CFG_RGMII_TX_DL_CFG_ADDR 0x5C
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#define RGMII_TX_DL_EB_OFFSET 8
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#define RGMII_TX_DL_EB_MASK 0x00000100
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#define RGMII_TX_DL_CFG_DATA_OFFSET 0
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#define RGMII_TX_DL_CFG_DATA_MASK 0x000000FF
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//-----------------------------------
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#define CFG_DMC_CHN0_CFG_ADDR 0x80
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#define CHN0_TIMEOUT_THRD_OFFSET 16
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#define CHN0_TIMEOUT_THRD_MASK 0xFFFF0000
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#define CHN0_WR_WAIT_LOAD_DONE_OFFSET 12
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#define CHN0_WR_WAIT_LOAD_DONE_MASK 0x00001000
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#define CHN0_OUT_BIT_ORDER_SEL_OFFSET 11
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#define CHN0_OUT_BIT_ORDER_SEL_MASK 0x00000800
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#define CHN0_OUT_BYTE_ORDER_SEL_OFFSET 10
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#define CHN0_OUT_BYTE_ORDER_SEL_MASK 0x00000400
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#define CHN0_IN_BIT_ORDER_SEL_OFFSET 9
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#define CHN0_IN_BIT_ORDER_SEL_MASK 0x00000200
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#define CHN0_IN_BYTE_ORDER_SEL_OFFSET 8
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#define CHN0_IN_BYTE_ORDER_SEL_MASK 0x00000100
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#define CHN0_EXSIZE_HANGING_STRATEGY_SEL_OFFSET 7
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#define CHN0_EXSIZE_HANGING_STRATEGY_SEL_MASK 0x00000080
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#define CHN0_WR_DONE_SEL_OFFSET 6
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#define CHN0_WR_DONE_SEL_MASK 0x00000040
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#define CHN0_PRIORITY_OFFSET 4
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#define CHN0_PRIORITY_MASK 0x00000030
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#define CHN0_WEIGHT_OFFSET 0
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#define CHN0_WEIGHT_MASK 0x0000000F
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//-----------------------------------
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#define CFG_DMC_CHN1_CFG_ADDR 0x84
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#define CHN1_TIMEOUT_THRD_OFFSET 16
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#define CHN1_TIMEOUT_THRD_MASK 0xFFFF0000
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#define CHN1_WR_WAIT_LOAD_DONE_OFFSET 12
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#define CHN1_WR_WAIT_LOAD_DONE_MASK 0x00001000
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#define CHN1_OUT_BIT_ORDER_SEL_OFFSET 11
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#define CHN1_OUT_BIT_ORDER_SEL_MASK 0x00000800
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#define CHN1_OUT_BYTE_ORDER_SEL_OFFSET 10
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#define CHN1_OUT_BYTE_ORDER_SEL_MASK 0x00000400
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#define CHN1_IN_BIT_ORDER_SEL_OFFSET 9
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#define CHN1_IN_BIT_ORDER_SEL_MASK 0x00000200
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#define CHN1_IN_BYTE_ORDER_SEL_OFFSET 8
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#define CHN1_IN_BYTE_ORDER_SEL_MASK 0x00000100
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#define CHN1_EXSIZE_HANGING_STRATEGY_SEL_OFFSET 7
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#define CHN1_EXSIZE_HANGING_STRATEGY_SEL_MASK 0x00000080
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#define CHN1_WR_DONE_SEL_OFFSET 6
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#define CHN1_WR_DONE_SEL_MASK 0x00000040
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#define CHN1_PRIORITY_OFFSET 4
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#define CHN1_PRIORITY_MASK 0x00000030
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#define CHN1_WEIGHT_OFFSET 0
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#define CHN1_WEIGHT_MASK 0x0000000F
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//-----------------------------------
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#define CFG_DMC_CHN2_CFG_ADDR 0x88
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#define CHN2_TIMEOUT_THRD_OFFSET 16
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#define CHN2_TIMEOUT_THRD_MASK 0xFFFF0000
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#define CHN2_WR_WAIT_LOAD_DONE_OFFSET 12
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#define CHN2_WR_WAIT_LOAD_DONE_MASK 0x00001000
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#define CHN2_OUT_BIT_ORDER_SEL_OFFSET 11
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#define CHN2_OUT_BIT_ORDER_SEL_MASK 0x00000800
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#define CHN2_OUT_BYTE_ORDER_SEL_OFFSET 10
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#define CHN2_OUT_BYTE_ORDER_SEL_MASK 0x00000400
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#define CHN2_IN_BIT_ORDER_SEL_OFFSET 9
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#define CHN2_IN_BIT_ORDER_SEL_MASK 0x00000200
|
|
#define CHN2_IN_BYTE_ORDER_SEL_OFFSET 8
|
|
#define CHN2_IN_BYTE_ORDER_SEL_MASK 0x00000100
|
|
#define CHN2_EXSIZE_HANGING_STRATEGY_SEL_OFFSET 7
|
|
#define CHN2_EXSIZE_HANGING_STRATEGY_SEL_MASK 0x00000080
|
|
#define CHN2_WR_DONE_SEL_OFFSET 6
|
|
#define CHN2_WR_DONE_SEL_MASK 0x00000040
|
|
#define CHN2_PRIORITY_OFFSET 4
|
|
#define CHN2_PRIORITY_MASK 0x00000030
|
|
#define CHN2_WEIGHT_OFFSET 0
|
|
#define CHN2_WEIGHT_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN3_CFG_ADDR 0x8C
|
|
#define CHN3_TIMEOUT_THRD_OFFSET 16
|
|
#define CHN3_TIMEOUT_THRD_MASK 0xFFFF0000
|
|
#define CHN3_WR_WAIT_LOAD_DONE_OFFSET 12
|
|
#define CHN3_WR_WAIT_LOAD_DONE_MASK 0x00001000
|
|
#define CHN3_OUT_BIT_ORDER_SEL_OFFSET 11
|
|
#define CHN3_OUT_BIT_ORDER_SEL_MASK 0x00000800
|
|
#define CHN3_OUT_BYTE_ORDER_SEL_OFFSET 10
|
|
#define CHN3_OUT_BYTE_ORDER_SEL_MASK 0x00000400
|
|
#define CHN3_IN_BIT_ORDER_SEL_OFFSET 9
|
|
#define CHN3_IN_BIT_ORDER_SEL_MASK 0x00000200
|
|
#define CHN3_IN_BYTE_ORDER_SEL_OFFSET 8
|
|
#define CHN3_IN_BYTE_ORDER_SEL_MASK 0x00000100
|
|
#define CHN3_EXSIZE_HANGING_STRATEGY_SEL_OFFSET 7
|
|
#define CHN3_EXSIZE_HANGING_STRATEGY_SEL_MASK 0x00000080
|
|
#define CHN3_WR_DONE_SEL_OFFSET 6
|
|
#define CHN3_WR_DONE_SEL_MASK 0x00000040
|
|
#define CHN3_PRIORITY_OFFSET 4
|
|
#define CHN3_PRIORITY_MASK 0x00000030
|
|
#define CHN3_WEIGHT_OFFSET 0
|
|
#define CHN3_WEIGHT_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN4_CFG_ADDR 0x90
|
|
#define CHN4_TIMEOUT_THRD_OFFSET 16
|
|
#define CHN4_TIMEOUT_THRD_MASK 0xFFFF0000
|
|
#define CHN4_WR_WAIT_LOAD_DONE_OFFSET 12
|
|
#define CHN4_WR_WAIT_LOAD_DONE_MASK 0x00001000
|
|
#define CHN4_OUT_BIT_ORDER_SEL_OFFSET 11
|
|
#define CHN4_OUT_BIT_ORDER_SEL_MASK 0x00000800
|
|
#define CHN4_OUT_BYTE_ORDER_SEL_OFFSET 10
|
|
#define CHN4_OUT_BYTE_ORDER_SEL_MASK 0x00000400
|
|
#define CHN4_IN_BIT_ORDER_SEL_OFFSET 9
|
|
#define CHN4_IN_BIT_ORDER_SEL_MASK 0x00000200
|
|
#define CHN4_IN_BYTE_ORDER_SEL_OFFSET 8
|
|
#define CHN4_IN_BYTE_ORDER_SEL_MASK 0x00000100
|
|
#define CHN4_EXSIZE_HANGING_STRATEGY_SEL_OFFSET 7
|
|
#define CHN4_EXSIZE_HANGING_STRATEGY_SEL_MASK 0x00000080
|
|
#define CHN4_WR_DONE_SEL_OFFSET 6
|
|
#define CHN4_WR_DONE_SEL_MASK 0x00000040
|
|
#define CHN4_PRIORITY_OFFSET 4
|
|
#define CHN4_PRIORITY_MASK 0x00000030
|
|
#define CHN4_WEIGHT_OFFSET 0
|
|
#define CHN4_WEIGHT_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN5_CFG_ADDR 0x94
|
|
#define CHN5_TIMEOUT_THRD_OFFSET 16
|
|
#define CHN5_TIMEOUT_THRD_MASK 0xFFFF0000
|
|
#define CHN5_WR_WAIT_LOAD_DONE_OFFSET 12
|
|
#define CHN5_WR_WAIT_LOAD_DONE_MASK 0x00001000
|
|
#define CHN5_OUT_BIT_ORDER_SEL_OFFSET 11
|
|
#define CHN5_OUT_BIT_ORDER_SEL_MASK 0x00000800
|
|
#define CHN5_OUT_BYTE_ORDER_SEL_OFFSET 10
|
|
#define CHN5_OUT_BYTE_ORDER_SEL_MASK 0x00000400
|
|
#define CHN5_IN_BIT_ORDER_SEL_OFFSET 9
|
|
#define CHN5_IN_BIT_ORDER_SEL_MASK 0x00000200
|
|
#define CHN5_IN_BYTE_ORDER_SEL_OFFSET 8
|
|
#define CHN5_IN_BYTE_ORDER_SEL_MASK 0x00000100
|
|
#define CHN5_EXSIZE_HANGING_STRATEGY_SEL_OFFSET 7
|
|
#define CHN5_EXSIZE_HANGING_STRATEGY_SEL_MASK 0x00000080
|
|
#define CHN5_WR_DONE_SEL_OFFSET 6
|
|
#define CHN5_WR_DONE_SEL_MASK 0x00000040
|
|
#define CHN5_PRIORITY_OFFSET 4
|
|
#define CHN5_PRIORITY_MASK 0x00000030
|
|
#define CHN5_WEIGHT_OFFSET 0
|
|
#define CHN5_WEIGHT_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN6_CFG_ADDR 0x98
|
|
#define CHN6_TIMEOUT_THRD_OFFSET 16
|
|
#define CHN6_TIMEOUT_THRD_MASK 0xFFFF0000
|
|
#define CHN6_WR_WAIT_LOAD_DONE_OFFSET 12
|
|
#define CHN6_WR_WAIT_LOAD_DONE_MASK 0x00001000
|
|
#define CHN6_OUT_BIT_ORDER_SEL_OFFSET 11
|
|
#define CHN6_OUT_BIT_ORDER_SEL_MASK 0x00000800
|
|
#define CHN6_OUT_BYTE_ORDER_SEL_OFFSET 10
|
|
#define CHN6_OUT_BYTE_ORDER_SEL_MASK 0x00000400
|
|
#define CHN6_IN_BIT_ORDER_SEL_OFFSET 9
|
|
#define CHN6_IN_BIT_ORDER_SEL_MASK 0x00000200
|
|
#define CHN6_IN_BYTE_ORDER_SEL_OFFSET 8
|
|
#define CHN6_IN_BYTE_ORDER_SEL_MASK 0x00000100
|
|
#define CHN6_EXSIZE_HANGING_STRATEGY_SEL_OFFSET 7
|
|
#define CHN6_EXSIZE_HANGING_STRATEGY_SEL_MASK 0x00000080
|
|
#define CHN6_WR_DONE_SEL_OFFSET 6
|
|
#define CHN6_WR_DONE_SEL_MASK 0x00000040
|
|
#define CHN6_PRIORITY_OFFSET 4
|
|
#define CHN6_PRIORITY_MASK 0x00000030
|
|
#define CHN6_WEIGHT_OFFSET 0
|
|
#define CHN6_WEIGHT_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN7_CFG_ADDR 0x9C
|
|
#define CHN7_TIMEOUT_THRD_OFFSET 16
|
|
#define CHN7_TIMEOUT_THRD_MASK 0xFFFF0000
|
|
#define CHN7_WR_WAIT_LOAD_DONE_OFFSET 12
|
|
#define CHN7_WR_WAIT_LOAD_DONE_MASK 0x00001000
|
|
#define CHN7_OUT_BIT_ORDER_SEL_OFFSET 11
|
|
#define CHN7_OUT_BIT_ORDER_SEL_MASK 0x00000800
|
|
#define CHN7_OUT_BYTE_ORDER_SEL_OFFSET 10
|
|
#define CHN7_OUT_BYTE_ORDER_SEL_MASK 0x00000400
|
|
#define CHN7_IN_BIT_ORDER_SEL_OFFSET 9
|
|
#define CHN7_IN_BIT_ORDER_SEL_MASK 0x00000200
|
|
#define CHN7_IN_BYTE_ORDER_SEL_OFFSET 8
|
|
#define CHN7_IN_BYTE_ORDER_SEL_MASK 0x00000100
|
|
#define CHN7_EXSIZE_HANGING_STRATEGY_SEL_OFFSET 7
|
|
#define CHN7_EXSIZE_HANGING_STRATEGY_SEL_MASK 0x00000080
|
|
#define CHN7_WR_DONE_SEL_OFFSET 6
|
|
#define CHN7_WR_DONE_SEL_MASK 0x00000040
|
|
#define CHN7_PRIORITY_OFFSET 4
|
|
#define CHN7_PRIORITY_MASK 0x00000030
|
|
#define CHN7_WEIGHT_OFFSET 0
|
|
#define CHN7_WEIGHT_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN8_CFG_ADDR 0xA0
|
|
#define CHN8_TIMEOUT_THRD_OFFSET 16
|
|
#define CHN8_TIMEOUT_THRD_MASK 0xFFFF0000
|
|
#define CHN8_WR_WAIT_LOAD_DONE_OFFSET 12
|
|
#define CHN8_WR_WAIT_LOAD_DONE_MASK 0x00001000
|
|
#define CHN8_OUT_BIT_ORDER_SEL_OFFSET 11
|
|
#define CHN8_OUT_BIT_ORDER_SEL_MASK 0x00000800
|
|
#define CHN8_OUT_BYTE_ORDER_SEL_OFFSET 10
|
|
#define CHN8_OUT_BYTE_ORDER_SEL_MASK 0x00000400
|
|
#define CHN8_IN_BIT_ORDER_SEL_OFFSET 9
|
|
#define CHN8_IN_BIT_ORDER_SEL_MASK 0x00000200
|
|
#define CHN8_IN_BYTE_ORDER_SEL_OFFSET 8
|
|
#define CHN8_IN_BYTE_ORDER_SEL_MASK 0x00000100
|
|
#define CHN8_EXSIZE_HANGING_STRATEGY_SEL_OFFSET 7
|
|
#define CHN8_EXSIZE_HANGING_STRATEGY_SEL_MASK 0x00000080
|
|
#define CHN8_WR_DONE_SEL_OFFSET 6
|
|
#define CHN8_WR_DONE_SEL_MASK 0x00000040
|
|
#define CHN8_PRIORITY_OFFSET 4
|
|
#define CHN8_PRIORITY_MASK 0x00000030
|
|
#define CHN8_WEIGHT_OFFSET 0
|
|
#define CHN8_WEIGHT_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN9_CFG_ADDR 0xA4
|
|
#define CHN9_TIMEOUT_THRD_OFFSET 16
|
|
#define CHN9_TIMEOUT_THRD_MASK 0xFFFF0000
|
|
#define CHN9_WR_WAIT_LOAD_DONE_OFFSET 12
|
|
#define CHN9_WR_WAIT_LOAD_DONE_MASK 0x00001000
|
|
#define CHN9_OUT_BIT_ORDER_SEL_OFFSET 11
|
|
#define CHN9_OUT_BIT_ORDER_SEL_MASK 0x00000800
|
|
#define CHN9_OUT_BYTE_ORDER_SEL_OFFSET 10
|
|
#define CHN9_OUT_BYTE_ORDER_SEL_MASK 0x00000400
|
|
#define CHN9_IN_BIT_ORDER_SEL_OFFSET 9
|
|
#define CHN9_IN_BIT_ORDER_SEL_MASK 0x00000200
|
|
#define CHN9_IN_BYTE_ORDER_SEL_OFFSET 8
|
|
#define CHN9_IN_BYTE_ORDER_SEL_MASK 0x00000100
|
|
#define CHN9_EXSIZE_HANGING_STRATEGY_SEL_OFFSET 7
|
|
#define CHN9_EXSIZE_HANGING_STRATEGY_SEL_MASK 0x00000080
|
|
#define CHN9_WR_DONE_SEL_OFFSET 6
|
|
#define CHN9_WR_DONE_SEL_MASK 0x00000040
|
|
#define CHN9_PRIORITY_OFFSET 4
|
|
#define CHN9_PRIORITY_MASK 0x00000030
|
|
#define CHN9_WEIGHT_OFFSET 0
|
|
#define CHN9_WEIGHT_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN_INTR_ST0_ADDR 0xF0
|
|
#define DMC_CHN_INT_ST0_OFFSET 0
|
|
#define DMC_CHN_INT_ST0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN_INTR_ST1_ADDR 0xF4
|
|
#define DMC_CHN_INT_ST1_OFFSET 0
|
|
#define DMC_CHN_INT_ST1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN0_INTR_RAW_ADDR 0x100
|
|
#define DMC_CHN0_EXCEED_SIZE_INT_RAW_OFFSET 5
|
|
#define DMC_CHN0_EXCEED_SIZE_INT_RAW_MASK 0x00000020
|
|
#define DMC_CHN0_PUSH_EXCEED_INT_RAW_OFFSET 4
|
|
#define DMC_CHN0_PUSH_EXCEED_INT_RAW_MASK 0x00000010
|
|
#define DMC_CHN0_WR_DONE_INT_RAW_OFFSET 3
|
|
#define DMC_CHN0_WR_DONE_INT_RAW_MASK 0x00000008
|
|
#define DMC_CHN0_RD_DONE_INT_RAW_OFFSET 2
|
|
#define DMC_CHN0_RD_DONE_INT_RAW_MASK 0x00000004
|
|
#define DMC_CHN0_WR_TIMEOUT_INT_RAW_OFFSET 1
|
|
#define DMC_CHN0_WR_TIMEOUT_INT_RAW_MASK 0x00000002
|
|
#define DMC_CHN0_RD_TIMEOUT_INT_RAW_OFFSET 0
|
|
#define DMC_CHN0_RD_TIMEOUT_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN0_INTR_ST_ADDR 0x104
|
|
#define DMC_CHN0_EXCEED_SIZE_INT_ST_OFFSET 5
|
|
#define DMC_CHN0_EXCEED_SIZE_INT_ST_MASK 0x00000020
|
|
#define DMC_CHN0_PUSH_EXCEED_INT_ST_OFFSET 4
|
|
#define DMC_CHN0_PUSH_EXCEED_INT_ST_MASK 0x00000010
|
|
#define DMC_CHN0_WR_DONE_INT_ST_OFFSET 3
|
|
#define DMC_CHN0_WR_DONE_INT_ST_MASK 0x00000008
|
|
#define DMC_CHN0_RD_DONE_INT_ST_OFFSET 2
|
|
#define DMC_CHN0_RD_DONE_INT_ST_MASK 0x00000004
|
|
#define DMC_CHN0_WR_TIMEOUT_INT_ST_OFFSET 1
|
|
#define DMC_CHN0_WR_TIMEOUT_INT_ST_MASK 0x00000002
|
|
#define DMC_CHN0_RD_TIMEOUT_INT_ST_OFFSET 0
|
|
#define DMC_CHN0_RD_TIMEOUT_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN0_INTR_ENA_ADDR 0x108
|
|
#define DMC_CHN0_EXCEED_SIZE_INT_ENA_OFFSET 5
|
|
#define DMC_CHN0_EXCEED_SIZE_INT_ENA_MASK 0x00000020
|
|
#define DMC_CHN0_PUSH_EXCEED_INT_ENA_OFFSET 4
|
|
#define DMC_CHN0_PUSH_EXCEED_INT_ENA_MASK 0x00000010
|
|
#define DMC_CHN0_WR_DONE_INT_ENA_OFFSET 3
|
|
#define DMC_CHN0_WR_DONE_INT_ENA_MASK 0x00000008
|
|
#define DMC_CHN0_RD_DONE_INT_ENA_OFFSET 2
|
|
#define DMC_CHN0_RD_DONE_INT_ENA_MASK 0x00000004
|
|
#define DMC_CHN0_WR_TIMEOUT_INT_ENA_OFFSET 1
|
|
#define DMC_CHN0_WR_TIMEOUT_INT_ENA_MASK 0x00000002
|
|
#define DMC_CHN0_RD_TIMEOUT_INT_ENA_OFFSET 0
|
|
#define DMC_CHN0_RD_TIMEOUT_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN0_INTR_CLR_ADDR 0x10C
|
|
#define DMC_CHN0_EXCEED_SIZE_INT_CLR_OFFSET 5
|
|
#define DMC_CHN0_EXCEED_SIZE_INT_CLR_MASK 0x00000020
|
|
#define DMC_CHN0_PUSH_EXCEED_INT_CLR_OFFSET 4
|
|
#define DMC_CHN0_PUSH_EXCEED_INT_CLR_MASK 0x00000010
|
|
#define DMC_CHN0_WR_DONE_INT_CLR_OFFSET 3
|
|
#define DMC_CHN0_WR_DONE_INT_CLR_MASK 0x00000008
|
|
#define DMC_CHN0_RD_DONE_INT_CLR_OFFSET 2
|
|
#define DMC_CHN0_RD_DONE_INT_CLR_MASK 0x00000004
|
|
#define DMC_CHN0_WR_TIMEOUT_INT_CLR_OFFSET 1
|
|
#define DMC_CHN0_WR_TIMEOUT_INT_CLR_MASK 0x00000002
|
|
#define DMC_CHN0_RD_TIMEOUT_INT_CLR_OFFSET 0
|
|
#define DMC_CHN0_RD_TIMEOUT_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN1_INTR_RAW_ADDR 0x110
|
|
#define DMC_CHN1_EXCEED_SIZE_INT_RAW_OFFSET 5
|
|
#define DMC_CHN1_EXCEED_SIZE_INT_RAW_MASK 0x00000020
|
|
#define DMC_CHN1_PUSH_EXCEED_INT_RAW_OFFSET 4
|
|
#define DMC_CHN1_PUSH_EXCEED_INT_RAW_MASK 0x00000010
|
|
#define DMC_CHN1_WR_DONE_INT_RAW_OFFSET 3
|
|
#define DMC_CHN1_WR_DONE_INT_RAW_MASK 0x00000008
|
|
#define DMC_CHN1_RD_DONE_INT_RAW_OFFSET 2
|
|
#define DMC_CHN1_RD_DONE_INT_RAW_MASK 0x00000004
|
|
#define DMC_CHN1_WR_TIMEOUT_INT_RAW_OFFSET 1
|
|
#define DMC_CHN1_WR_TIMEOUT_INT_RAW_MASK 0x00000002
|
|
#define DMC_CHN1_RD_TIMEOUT_INT_RAW_OFFSET 0
|
|
#define DMC_CHN1_RD_TIMEOUT_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN1_INTR_ST_ADDR 0x114
|
|
#define DMC_CHN1_EXCEED_SIZE_INT_ST_OFFSET 5
|
|
#define DMC_CHN1_EXCEED_SIZE_INT_ST_MASK 0x00000020
|
|
#define DMC_CHN1_PUSH_EXCEED_INT_ST_OFFSET 4
|
|
#define DMC_CHN1_PUSH_EXCEED_INT_ST_MASK 0x00000010
|
|
#define DMC_CHN1_WR_DONE_INT_ST_OFFSET 3
|
|
#define DMC_CHN1_WR_DONE_INT_ST_MASK 0x00000008
|
|
#define DMC_CHN1_RD_DONE_INT_ST_OFFSET 2
|
|
#define DMC_CHN1_RD_DONE_INT_ST_MASK 0x00000004
|
|
#define DMC_CHN1_WR_TIMEOUT_INT_ST_OFFSET 1
|
|
#define DMC_CHN1_WR_TIMEOUT_INT_ST_MASK 0x00000002
|
|
#define DMC_CHN1_RD_TIMEOUT_INT_ST_OFFSET 0
|
|
#define DMC_CHN1_RD_TIMEOUT_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN1_INTR_ENA_ADDR 0x118
|
|
#define DMC_CHN1_EXCEED_SIZE_INT_ENA_OFFSET 5
|
|
#define DMC_CHN1_EXCEED_SIZE_INT_ENA_MASK 0x00000020
|
|
#define DMC_CHN1_PUSH_EXCEED_INT_ENA_OFFSET 4
|
|
#define DMC_CHN1_PUSH_EXCEED_INT_ENA_MASK 0x00000010
|
|
#define DMC_CHN1_WR_DONE_INT_ENA_OFFSET 3
|
|
#define DMC_CHN1_WR_DONE_INT_ENA_MASK 0x00000008
|
|
#define DMC_CHN1_RD_DONE_INT_ENA_OFFSET 2
|
|
#define DMC_CHN1_RD_DONE_INT_ENA_MASK 0x00000004
|
|
#define DMC_CHN1_WR_TIMEOUT_INT_ENA_OFFSET 1
|
|
#define DMC_CHN1_WR_TIMEOUT_INT_ENA_MASK 0x00000002
|
|
#define DMC_CHN1_RD_TIMEOUT_INT_ENA_OFFSET 0
|
|
#define DMC_CHN1_RD_TIMEOUT_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN1_INTR_CLR_ADDR 0x11C
|
|
#define DMC_CHN1_EXCEED_SIZE_INT_CLR_OFFSET 5
|
|
#define DMC_CHN1_EXCEED_SIZE_INT_CLR_MASK 0x00000020
|
|
#define DMC_CHN1_PUSH_EXCEED_INT_CLR_OFFSET 4
|
|
#define DMC_CHN1_PUSH_EXCEED_INT_CLR_MASK 0x00000010
|
|
#define DMC_CHN1_WR_DONE_INT_CLR_OFFSET 3
|
|
#define DMC_CHN1_WR_DONE_INT_CLR_MASK 0x00000008
|
|
#define DMC_CHN1_RD_DONE_INT_CLR_OFFSET 2
|
|
#define DMC_CHN1_RD_DONE_INT_CLR_MASK 0x00000004
|
|
#define DMC_CHN1_WR_TIMEOUT_INT_CLR_OFFSET 1
|
|
#define DMC_CHN1_WR_TIMEOUT_INT_CLR_MASK 0x00000002
|
|
#define DMC_CHN1_RD_TIMEOUT_INT_CLR_OFFSET 0
|
|
#define DMC_CHN1_RD_TIMEOUT_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN2_INTR_RAW_ADDR 0x120
|
|
#define DMC_CHN2_EXCEED_SIZE_INT_RAW_OFFSET 5
|
|
#define DMC_CHN2_EXCEED_SIZE_INT_RAW_MASK 0x00000020
|
|
#define DMC_CHN2_PUSH_EXCEED_INT_RAW_OFFSET 4
|
|
#define DMC_CHN2_PUSH_EXCEED_INT_RAW_MASK 0x00000010
|
|
#define DMC_CHN2_WR_DONE_INT_RAW_OFFSET 3
|
|
#define DMC_CHN2_WR_DONE_INT_RAW_MASK 0x00000008
|
|
#define DMC_CHN2_RD_DONE_INT_RAW_OFFSET 2
|
|
#define DMC_CHN2_RD_DONE_INT_RAW_MASK 0x00000004
|
|
#define DMC_CHN2_WR_TIMEOUT_INT_RAW_OFFSET 1
|
|
#define DMC_CHN2_WR_TIMEOUT_INT_RAW_MASK 0x00000002
|
|
#define DMC_CHN2_RD_TIMEOUT_INT_RAW_OFFSET 0
|
|
#define DMC_CHN2_RD_TIMEOUT_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN2_INTR_ST_ADDR 0x124
|
|
#define DMC_CHN2_EXCEED_SIZE_INT_ST_OFFSET 5
|
|
#define DMC_CHN2_EXCEED_SIZE_INT_ST_MASK 0x00000020
|
|
#define DMC_CHN2_PUSH_EXCEED_INT_ST_OFFSET 4
|
|
#define DMC_CHN2_PUSH_EXCEED_INT_ST_MASK 0x00000010
|
|
#define DMC_CHN2_WR_DONE_INT_ST_OFFSET 3
|
|
#define DMC_CHN2_WR_DONE_INT_ST_MASK 0x00000008
|
|
#define DMC_CHN2_RD_DONE_INT_ST_OFFSET 2
|
|
#define DMC_CHN2_RD_DONE_INT_ST_MASK 0x00000004
|
|
#define DMC_CHN2_WR_TIMEOUT_INT_ST_OFFSET 1
|
|
#define DMC_CHN2_WR_TIMEOUT_INT_ST_MASK 0x00000002
|
|
#define DMC_CHN2_RD_TIMEOUT_INT_ST_OFFSET 0
|
|
#define DMC_CHN2_RD_TIMEOUT_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN2_INTR_ENA_ADDR 0x128
|
|
#define DMC_CHN2_EXCEED_SIZE_INT_ENA_OFFSET 5
|
|
#define DMC_CHN2_EXCEED_SIZE_INT_ENA_MASK 0x00000020
|
|
#define DMC_CHN2_PUSH_EXCEED_INT_ENA_OFFSET 4
|
|
#define DMC_CHN2_PUSH_EXCEED_INT_ENA_MASK 0x00000010
|
|
#define DMC_CHN2_WR_DONE_INT_ENA_OFFSET 3
|
|
#define DMC_CHN2_WR_DONE_INT_ENA_MASK 0x00000008
|
|
#define DMC_CHN2_RD_DONE_INT_ENA_OFFSET 2
|
|
#define DMC_CHN2_RD_DONE_INT_ENA_MASK 0x00000004
|
|
#define DMC_CHN2_WR_TIMEOUT_INT_ENA_OFFSET 1
|
|
#define DMC_CHN2_WR_TIMEOUT_INT_ENA_MASK 0x00000002
|
|
#define DMC_CHN2_RD_TIMEOUT_INT_ENA_OFFSET 0
|
|
#define DMC_CHN2_RD_TIMEOUT_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN2_INTR_CLR_ADDR 0x12C
|
|
#define DMC_CHN2_EXCEED_SIZE_INT_CLR_OFFSET 5
|
|
#define DMC_CHN2_EXCEED_SIZE_INT_CLR_MASK 0x00000020
|
|
#define DMC_CHN2_PUSH_EXCEED_INT_CLR_OFFSET 4
|
|
#define DMC_CHN2_PUSH_EXCEED_INT_CLR_MASK 0x00000010
|
|
#define DMC_CHN2_WR_DONE_INT_CLR_OFFSET 3
|
|
#define DMC_CHN2_WR_DONE_INT_CLR_MASK 0x00000008
|
|
#define DMC_CHN2_RD_DONE_INT_CLR_OFFSET 2
|
|
#define DMC_CHN2_RD_DONE_INT_CLR_MASK 0x00000004
|
|
#define DMC_CHN2_WR_TIMEOUT_INT_CLR_OFFSET 1
|
|
#define DMC_CHN2_WR_TIMEOUT_INT_CLR_MASK 0x00000002
|
|
#define DMC_CHN2_RD_TIMEOUT_INT_CLR_OFFSET 0
|
|
#define DMC_CHN2_RD_TIMEOUT_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN3_INTR_RAW_ADDR 0x130
|
|
#define DMC_CHN3_EXCEED_SIZE_INT_RAW_OFFSET 5
|
|
#define DMC_CHN3_EXCEED_SIZE_INT_RAW_MASK 0x00000020
|
|
#define DMC_CHN3_PUSH_EXCEED_INT_RAW_OFFSET 4
|
|
#define DMC_CHN3_PUSH_EXCEED_INT_RAW_MASK 0x00000010
|
|
#define DMC_CHN3_WR_DONE_INT_RAW_OFFSET 3
|
|
#define DMC_CHN3_WR_DONE_INT_RAW_MASK 0x00000008
|
|
#define DMC_CHN3_RD_DONE_INT_RAW_OFFSET 2
|
|
#define DMC_CHN3_RD_DONE_INT_RAW_MASK 0x00000004
|
|
#define DMC_CHN3_WR_TIMEOUT_INT_RAW_OFFSET 1
|
|
#define DMC_CHN3_WR_TIMEOUT_INT_RAW_MASK 0x00000002
|
|
#define DMC_CHN3_RD_TIMEOUT_INT_RAW_OFFSET 0
|
|
#define DMC_CHN3_RD_TIMEOUT_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN3_INTR_ST_ADDR 0x134
|
|
#define DMC_CHN3_EXCEED_SIZE_INT_ST_OFFSET 5
|
|
#define DMC_CHN3_EXCEED_SIZE_INT_ST_MASK 0x00000020
|
|
#define DMC_CHN3_PUSH_EXCEED_INT_ST_OFFSET 4
|
|
#define DMC_CHN3_PUSH_EXCEED_INT_ST_MASK 0x00000010
|
|
#define DMC_CHN3_WR_DONE_INT_ST_OFFSET 3
|
|
#define DMC_CHN3_WR_DONE_INT_ST_MASK 0x00000008
|
|
#define DMC_CHN3_RD_DONE_INT_ST_OFFSET 2
|
|
#define DMC_CHN3_RD_DONE_INT_ST_MASK 0x00000004
|
|
#define DMC_CHN3_WR_TIMEOUT_INT_ST_OFFSET 1
|
|
#define DMC_CHN3_WR_TIMEOUT_INT_ST_MASK 0x00000002
|
|
#define DMC_CHN3_RD_TIMEOUT_INT_ST_OFFSET 0
|
|
#define DMC_CHN3_RD_TIMEOUT_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN3_INTR_ENA_ADDR 0x138
|
|
#define DMC_CHN3_EXCEED_SIZE_INT_ENA_OFFSET 5
|
|
#define DMC_CHN3_EXCEED_SIZE_INT_ENA_MASK 0x00000020
|
|
#define DMC_CHN3_PUSH_EXCEED_INT_ENA_OFFSET 4
|
|
#define DMC_CHN3_PUSH_EXCEED_INT_ENA_MASK 0x00000010
|
|
#define DMC_CHN3_WR_DONE_INT_ENA_OFFSET 3
|
|
#define DMC_CHN3_WR_DONE_INT_ENA_MASK 0x00000008
|
|
#define DMC_CHN3_RD_DONE_INT_ENA_OFFSET 2
|
|
#define DMC_CHN3_RD_DONE_INT_ENA_MASK 0x00000004
|
|
#define DMC_CHN3_WR_TIMEOUT_INT_ENA_OFFSET 1
|
|
#define DMC_CHN3_WR_TIMEOUT_INT_ENA_MASK 0x00000002
|
|
#define DMC_CHN3_RD_TIMEOUT_INT_ENA_OFFSET 0
|
|
#define DMC_CHN3_RD_TIMEOUT_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN3_INTR_CLR_ADDR 0x13C
|
|
#define DMC_CHN3_EXCEED_SIZE_INT_CLR_OFFSET 5
|
|
#define DMC_CHN3_EXCEED_SIZE_INT_CLR_MASK 0x00000020
|
|
#define DMC_CHN3_PUSH_EXCEED_INT_CLR_OFFSET 4
|
|
#define DMC_CHN3_PUSH_EXCEED_INT_CLR_MASK 0x00000010
|
|
#define DMC_CHN3_WR_DONE_INT_CLR_OFFSET 3
|
|
#define DMC_CHN3_WR_DONE_INT_CLR_MASK 0x00000008
|
|
#define DMC_CHN3_RD_DONE_INT_CLR_OFFSET 2
|
|
#define DMC_CHN3_RD_DONE_INT_CLR_MASK 0x00000004
|
|
#define DMC_CHN3_WR_TIMEOUT_INT_CLR_OFFSET 1
|
|
#define DMC_CHN3_WR_TIMEOUT_INT_CLR_MASK 0x00000002
|
|
#define DMC_CHN3_RD_TIMEOUT_INT_CLR_OFFSET 0
|
|
#define DMC_CHN3_RD_TIMEOUT_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN4_INTR_RAW_ADDR 0x140
|
|
#define DMC_CHN4_EXCEED_SIZE_INT_RAW_OFFSET 5
|
|
#define DMC_CHN4_EXCEED_SIZE_INT_RAW_MASK 0x00000020
|
|
#define DMC_CHN4_PUSH_EXCEED_INT_RAW_OFFSET 4
|
|
#define DMC_CHN4_PUSH_EXCEED_INT_RAW_MASK 0x00000010
|
|
#define DMC_CHN4_WR_DONE_INT_RAW_OFFSET 3
|
|
#define DMC_CHN4_WR_DONE_INT_RAW_MASK 0x00000008
|
|
#define DMC_CHN4_RD_DONE_INT_RAW_OFFSET 2
|
|
#define DMC_CHN4_RD_DONE_INT_RAW_MASK 0x00000004
|
|
#define DMC_CHN4_WR_TIMEOUT_INT_RAW_OFFSET 1
|
|
#define DMC_CHN4_WR_TIMEOUT_INT_RAW_MASK 0x00000002
|
|
#define DMC_CHN4_RD_TIMEOUT_INT_RAW_OFFSET 0
|
|
#define DMC_CHN4_RD_TIMEOUT_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN4_INTR_ST_ADDR 0x144
|
|
#define DMC_CHN4_EXCEED_SIZE_INT_ST_OFFSET 5
|
|
#define DMC_CHN4_EXCEED_SIZE_INT_ST_MASK 0x00000020
|
|
#define DMC_CHN4_PUSH_EXCEED_INT_ST_OFFSET 4
|
|
#define DMC_CHN4_PUSH_EXCEED_INT_ST_MASK 0x00000010
|
|
#define DMC_CHN4_WR_DONE_INT_ST_OFFSET 3
|
|
#define DMC_CHN4_WR_DONE_INT_ST_MASK 0x00000008
|
|
#define DMC_CHN4_RD_DONE_INT_ST_OFFSET 2
|
|
#define DMC_CHN4_RD_DONE_INT_ST_MASK 0x00000004
|
|
#define DMC_CHN4_WR_TIMEOUT_INT_ST_OFFSET 1
|
|
#define DMC_CHN4_WR_TIMEOUT_INT_ST_MASK 0x00000002
|
|
#define DMC_CHN4_RD_TIMEOUT_INT_ST_OFFSET 0
|
|
#define DMC_CHN4_RD_TIMEOUT_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN4_INTR_ENA_ADDR 0x148
|
|
#define DMC_CHN4_EXCEED_SIZE_INT_ENA_OFFSET 5
|
|
#define DMC_CHN4_EXCEED_SIZE_INT_ENA_MASK 0x00000020
|
|
#define DMC_CHN4_PUSH_EXCEED_INT_ENA_OFFSET 4
|
|
#define DMC_CHN4_PUSH_EXCEED_INT_ENA_MASK 0x00000010
|
|
#define DMC_CHN4_WR_DONE_INT_ENA_OFFSET 3
|
|
#define DMC_CHN4_WR_DONE_INT_ENA_MASK 0x00000008
|
|
#define DMC_CHN4_RD_DONE_INT_ENA_OFFSET 2
|
|
#define DMC_CHN4_RD_DONE_INT_ENA_MASK 0x00000004
|
|
#define DMC_CHN4_WR_TIMEOUT_INT_ENA_OFFSET 1
|
|
#define DMC_CHN4_WR_TIMEOUT_INT_ENA_MASK 0x00000002
|
|
#define DMC_CHN4_RD_TIMEOUT_INT_ENA_OFFSET 0
|
|
#define DMC_CHN4_RD_TIMEOUT_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN4_INTR_CLR_ADDR 0x14C
|
|
#define DMC_CHN4_EXCEED_SIZE_INT_CLR_OFFSET 5
|
|
#define DMC_CHN4_EXCEED_SIZE_INT_CLR_MASK 0x00000020
|
|
#define DMC_CHN4_PUSH_EXCEED_INT_CLR_OFFSET 4
|
|
#define DMC_CHN4_PUSH_EXCEED_INT_CLR_MASK 0x00000010
|
|
#define DMC_CHN4_WR_DONE_INT_CLR_OFFSET 3
|
|
#define DMC_CHN4_WR_DONE_INT_CLR_MASK 0x00000008
|
|
#define DMC_CHN4_RD_DONE_INT_CLR_OFFSET 2
|
|
#define DMC_CHN4_RD_DONE_INT_CLR_MASK 0x00000004
|
|
#define DMC_CHN4_WR_TIMEOUT_INT_CLR_OFFSET 1
|
|
#define DMC_CHN4_WR_TIMEOUT_INT_CLR_MASK 0x00000002
|
|
#define DMC_CHN4_RD_TIMEOUT_INT_CLR_OFFSET 0
|
|
#define DMC_CHN4_RD_TIMEOUT_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN5_INTR_RAW_ADDR 0x150
|
|
#define DMC_CHN5_EXCEED_SIZE_INT_RAW_OFFSET 5
|
|
#define DMC_CHN5_EXCEED_SIZE_INT_RAW_MASK 0x00000020
|
|
#define DMC_CHN5_PUSH_EXCEED_INT_RAW_OFFSET 4
|
|
#define DMC_CHN5_PUSH_EXCEED_INT_RAW_MASK 0x00000010
|
|
#define DMC_CHN5_WR_DONE_INT_RAW_OFFSET 3
|
|
#define DMC_CHN5_WR_DONE_INT_RAW_MASK 0x00000008
|
|
#define DMC_CHN5_RD_DONE_INT_RAW_OFFSET 2
|
|
#define DMC_CHN5_RD_DONE_INT_RAW_MASK 0x00000004
|
|
#define DMC_CHN5_WR_TIMEOUT_INT_RAW_OFFSET 1
|
|
#define DMC_CHN5_WR_TIMEOUT_INT_RAW_MASK 0x00000002
|
|
#define DMC_CHN5_RD_TIMEOUT_INT_RAW_OFFSET 0
|
|
#define DMC_CHN5_RD_TIMEOUT_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN5_INTR_ST_ADDR 0x154
|
|
#define DMC_CHN5_EXCEED_SIZE_INT_ST_OFFSET 5
|
|
#define DMC_CHN5_EXCEED_SIZE_INT_ST_MASK 0x00000020
|
|
#define DMC_CHN5_PUSH_EXCEED_INT_ST_OFFSET 4
|
|
#define DMC_CHN5_PUSH_EXCEED_INT_ST_MASK 0x00000010
|
|
#define DMC_CHN5_WR_DONE_INT_ST_OFFSET 3
|
|
#define DMC_CHN5_WR_DONE_INT_ST_MASK 0x00000008
|
|
#define DMC_CHN5_RD_DONE_INT_ST_OFFSET 2
|
|
#define DMC_CHN5_RD_DONE_INT_ST_MASK 0x00000004
|
|
#define DMC_CHN5_WR_TIMEOUT_INT_ST_OFFSET 1
|
|
#define DMC_CHN5_WR_TIMEOUT_INT_ST_MASK 0x00000002
|
|
#define DMC_CHN5_RD_TIMEOUT_INT_ST_OFFSET 0
|
|
#define DMC_CHN5_RD_TIMEOUT_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN5_INTR_ENA_ADDR 0x158
|
|
#define DMC_CHN5_EXCEED_SIZE_INT_ENA_OFFSET 5
|
|
#define DMC_CHN5_EXCEED_SIZE_INT_ENA_MASK 0x00000020
|
|
#define DMC_CHN5_PUSH_EXCEED_INT_ENA_OFFSET 4
|
|
#define DMC_CHN5_PUSH_EXCEED_INT_ENA_MASK 0x00000010
|
|
#define DMC_CHN5_WR_DONE_INT_ENA_OFFSET 3
|
|
#define DMC_CHN5_WR_DONE_INT_ENA_MASK 0x00000008
|
|
#define DMC_CHN5_RD_DONE_INT_ENA_OFFSET 2
|
|
#define DMC_CHN5_RD_DONE_INT_ENA_MASK 0x00000004
|
|
#define DMC_CHN5_WR_TIMEOUT_INT_ENA_OFFSET 1
|
|
#define DMC_CHN5_WR_TIMEOUT_INT_ENA_MASK 0x00000002
|
|
#define DMC_CHN5_RD_TIMEOUT_INT_ENA_OFFSET 0
|
|
#define DMC_CHN5_RD_TIMEOUT_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN5_INTR_CLR_ADDR 0x15C
|
|
#define DMC_CHN5_EXCEED_SIZE_INT_CLR_OFFSET 5
|
|
#define DMC_CHN5_EXCEED_SIZE_INT_CLR_MASK 0x00000020
|
|
#define DMC_CHN5_PUSH_EXCEED_INT_CLR_OFFSET 4
|
|
#define DMC_CHN5_PUSH_EXCEED_INT_CLR_MASK 0x00000010
|
|
#define DMC_CHN5_WR_DONE_INT_CLR_OFFSET 3
|
|
#define DMC_CHN5_WR_DONE_INT_CLR_MASK 0x00000008
|
|
#define DMC_CHN5_RD_DONE_INT_CLR_OFFSET 2
|
|
#define DMC_CHN5_RD_DONE_INT_CLR_MASK 0x00000004
|
|
#define DMC_CHN5_WR_TIMEOUT_INT_CLR_OFFSET 1
|
|
#define DMC_CHN5_WR_TIMEOUT_INT_CLR_MASK 0x00000002
|
|
#define DMC_CHN5_RD_TIMEOUT_INT_CLR_OFFSET 0
|
|
#define DMC_CHN5_RD_TIMEOUT_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN6_INTR_RAW_ADDR 0x160
|
|
#define DMC_CHN6_EXCEED_SIZE_INT_RAW_OFFSET 5
|
|
#define DMC_CHN6_EXCEED_SIZE_INT_RAW_MASK 0x00000020
|
|
#define DMC_CHN6_PUSH_EXCEED_INT_RAW_OFFSET 4
|
|
#define DMC_CHN6_PUSH_EXCEED_INT_RAW_MASK 0x00000010
|
|
#define DMC_CHN6_WR_DONE_INT_RAW_OFFSET 3
|
|
#define DMC_CHN6_WR_DONE_INT_RAW_MASK 0x00000008
|
|
#define DMC_CHN6_RD_DONE_INT_RAW_OFFSET 2
|
|
#define DMC_CHN6_RD_DONE_INT_RAW_MASK 0x00000004
|
|
#define DMC_CHN6_WR_TIMEOUT_INT_RAW_OFFSET 1
|
|
#define DMC_CHN6_WR_TIMEOUT_INT_RAW_MASK 0x00000002
|
|
#define DMC_CHN6_RD_TIMEOUT_INT_RAW_OFFSET 0
|
|
#define DMC_CHN6_RD_TIMEOUT_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN6_INTR_ST_ADDR 0x164
|
|
#define DMC_CHN6_EXCEED_SIZE_INT_ST_OFFSET 5
|
|
#define DMC_CHN6_EXCEED_SIZE_INT_ST_MASK 0x00000020
|
|
#define DMC_CHN6_PUSH_EXCEED_INT_ST_OFFSET 4
|
|
#define DMC_CHN6_PUSH_EXCEED_INT_ST_MASK 0x00000010
|
|
#define DMC_CHN6_WR_DONE_INT_ST_OFFSET 3
|
|
#define DMC_CHN6_WR_DONE_INT_ST_MASK 0x00000008
|
|
#define DMC_CHN6_RD_DONE_INT_ST_OFFSET 2
|
|
#define DMC_CHN6_RD_DONE_INT_ST_MASK 0x00000004
|
|
#define DMC_CHN6_WR_TIMEOUT_INT_ST_OFFSET 1
|
|
#define DMC_CHN6_WR_TIMEOUT_INT_ST_MASK 0x00000002
|
|
#define DMC_CHN6_RD_TIMEOUT_INT_ST_OFFSET 0
|
|
#define DMC_CHN6_RD_TIMEOUT_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN6_INTR_ENA_ADDR 0x168
|
|
#define DMC_CHN6_EXCEED_SIZE_INT_ENA_OFFSET 5
|
|
#define DMC_CHN6_EXCEED_SIZE_INT_ENA_MASK 0x00000020
|
|
#define DMC_CHN6_PUSH_EXCEED_INT_ENA_OFFSET 4
|
|
#define DMC_CHN6_PUSH_EXCEED_INT_ENA_MASK 0x00000010
|
|
#define DMC_CHN6_WR_DONE_INT_ENA_OFFSET 3
|
|
#define DMC_CHN6_WR_DONE_INT_ENA_MASK 0x00000008
|
|
#define DMC_CHN6_RD_DONE_INT_ENA_OFFSET 2
|
|
#define DMC_CHN6_RD_DONE_INT_ENA_MASK 0x00000004
|
|
#define DMC_CHN6_WR_TIMEOUT_INT_ENA_OFFSET 1
|
|
#define DMC_CHN6_WR_TIMEOUT_INT_ENA_MASK 0x00000002
|
|
#define DMC_CHN6_RD_TIMEOUT_INT_ENA_OFFSET 0
|
|
#define DMC_CHN6_RD_TIMEOUT_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN6_INTR_CLR_ADDR 0x16C
|
|
#define DMC_CHN6_EXCEED_SIZE_INT_CLR_OFFSET 5
|
|
#define DMC_CHN6_EXCEED_SIZE_INT_CLR_MASK 0x00000020
|
|
#define DMC_CHN6_PUSH_EXCEED_INT_CLR_OFFSET 4
|
|
#define DMC_CHN6_PUSH_EXCEED_INT_CLR_MASK 0x00000010
|
|
#define DMC_CHN6_WR_DONE_INT_CLR_OFFSET 3
|
|
#define DMC_CHN6_WR_DONE_INT_CLR_MASK 0x00000008
|
|
#define DMC_CHN6_RD_DONE_INT_CLR_OFFSET 2
|
|
#define DMC_CHN6_RD_DONE_INT_CLR_MASK 0x00000004
|
|
#define DMC_CHN6_WR_TIMEOUT_INT_CLR_OFFSET 1
|
|
#define DMC_CHN6_WR_TIMEOUT_INT_CLR_MASK 0x00000002
|
|
#define DMC_CHN6_RD_TIMEOUT_INT_CLR_OFFSET 0
|
|
#define DMC_CHN6_RD_TIMEOUT_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN7_INTR_RAW_ADDR 0x170
|
|
#define DMC_CHN7_EXCEED_SIZE_INT_RAW_OFFSET 5
|
|
#define DMC_CHN7_EXCEED_SIZE_INT_RAW_MASK 0x00000020
|
|
#define DMC_CHN7_PUSH_EXCEED_INT_RAW_OFFSET 4
|
|
#define DMC_CHN7_PUSH_EXCEED_INT_RAW_MASK 0x00000010
|
|
#define DMC_CHN7_WR_DONE_INT_RAW_OFFSET 3
|
|
#define DMC_CHN7_WR_DONE_INT_RAW_MASK 0x00000008
|
|
#define DMC_CHN7_RD_DONE_INT_RAW_OFFSET 2
|
|
#define DMC_CHN7_RD_DONE_INT_RAW_MASK 0x00000004
|
|
#define DMC_CHN7_WR_TIMEOUT_INT_RAW_OFFSET 1
|
|
#define DMC_CHN7_WR_TIMEOUT_INT_RAW_MASK 0x00000002
|
|
#define DMC_CHN7_RD_TIMEOUT_INT_RAW_OFFSET 0
|
|
#define DMC_CHN7_RD_TIMEOUT_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMC_CHN7_INTR_ST_ADDR 0x174
|
|
#define DMC_CHN7_EXCEED_SIZE_INT_ST_OFFSET 5
|
|
#define DMC_CHN7_EXCEED_SIZE_INT_ST_MASK 0x00000020
|
|
#define DMC_CHN7_PUSH_EXCEED_INT_ST_OFFSET 4
|
|
#define DMC_CHN7_PUSH_EXCEED_INT_ST_MASK 0x00000010
|
|
#define DMC_CHN7_WR_DONE_INT_ST_OFFSET 3
|
|
#define DMC_CHN7_WR_DONE_INT_ST_MASK 0x00000008
|
|
#define DMC_CHN7_RD_DONE_INT_ST_OFFSET 2
|
|
#define DMC_CHN7_RD_DONE_INT_ST_MASK 0x00000004
|
|
#define DMC_CHN7_WR_TIMEOUT_INT_ST_OFFSET 1
|
|
#define DMC_CHN7_WR_TIMEOUT_INT_ST_MASK 0x00000002
|
|
#define DMC_CHN7_RD_TIMEOUT_INT_ST_OFFSET 0
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#define DMC_CHN7_RD_TIMEOUT_INT_ST_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMC_CHN7_INTR_ENA_ADDR 0x178
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#define DMC_CHN7_EXCEED_SIZE_INT_ENA_OFFSET 5
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#define DMC_CHN7_EXCEED_SIZE_INT_ENA_MASK 0x00000020
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#define DMC_CHN7_PUSH_EXCEED_INT_ENA_OFFSET 4
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#define DMC_CHN7_PUSH_EXCEED_INT_ENA_MASK 0x00000010
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#define DMC_CHN7_WR_DONE_INT_ENA_OFFSET 3
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#define DMC_CHN7_WR_DONE_INT_ENA_MASK 0x00000008
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#define DMC_CHN7_RD_DONE_INT_ENA_OFFSET 2
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#define DMC_CHN7_RD_DONE_INT_ENA_MASK 0x00000004
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#define DMC_CHN7_WR_TIMEOUT_INT_ENA_OFFSET 1
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#define DMC_CHN7_WR_TIMEOUT_INT_ENA_MASK 0x00000002
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#define DMC_CHN7_RD_TIMEOUT_INT_ENA_OFFSET 0
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#define DMC_CHN7_RD_TIMEOUT_INT_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMC_CHN7_INTR_CLR_ADDR 0x17C
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#define DMC_CHN7_EXCEED_SIZE_INT_CLR_OFFSET 5
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#define DMC_CHN7_EXCEED_SIZE_INT_CLR_MASK 0x00000020
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#define DMC_CHN7_PUSH_EXCEED_INT_CLR_OFFSET 4
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#define DMC_CHN7_PUSH_EXCEED_INT_CLR_MASK 0x00000010
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#define DMC_CHN7_WR_DONE_INT_CLR_OFFSET 3
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#define DMC_CHN7_WR_DONE_INT_CLR_MASK 0x00000008
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#define DMC_CHN7_RD_DONE_INT_CLR_OFFSET 2
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#define DMC_CHN7_RD_DONE_INT_CLR_MASK 0x00000004
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#define DMC_CHN7_WR_TIMEOUT_INT_CLR_OFFSET 1
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#define DMC_CHN7_WR_TIMEOUT_INT_CLR_MASK 0x00000002
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#define DMC_CHN7_RD_TIMEOUT_INT_CLR_OFFSET 0
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#define DMC_CHN7_RD_TIMEOUT_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMC_CHN8_INTR_RAW_ADDR 0x180
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#define DMC_CHN8_EXCEED_SIZE_INT_RAW_OFFSET 5
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#define DMC_CHN8_EXCEED_SIZE_INT_RAW_MASK 0x00000020
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#define DMC_CHN8_PUSH_EXCEED_INT_RAW_OFFSET 4
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#define DMC_CHN8_PUSH_EXCEED_INT_RAW_MASK 0x00000010
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#define DMC_CHN8_WR_DONE_INT_RAW_OFFSET 3
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#define DMC_CHN8_WR_DONE_INT_RAW_MASK 0x00000008
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#define DMC_CHN8_RD_DONE_INT_RAW_OFFSET 2
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#define DMC_CHN8_RD_DONE_INT_RAW_MASK 0x00000004
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#define DMC_CHN8_WR_TIMEOUT_INT_RAW_OFFSET 1
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#define DMC_CHN8_WR_TIMEOUT_INT_RAW_MASK 0x00000002
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#define DMC_CHN8_RD_TIMEOUT_INT_RAW_OFFSET 0
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#define DMC_CHN8_RD_TIMEOUT_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMC_CHN8_INTR_ST_ADDR 0x184
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#define DMC_CHN8_EXCEED_SIZE_INT_ST_OFFSET 5
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#define DMC_CHN8_EXCEED_SIZE_INT_ST_MASK 0x00000020
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#define DMC_CHN8_PUSH_EXCEED_INT_ST_OFFSET 4
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#define DMC_CHN8_PUSH_EXCEED_INT_ST_MASK 0x00000010
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#define DMC_CHN8_WR_DONE_INT_ST_OFFSET 3
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#define DMC_CHN8_WR_DONE_INT_ST_MASK 0x00000008
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#define DMC_CHN8_RD_DONE_INT_ST_OFFSET 2
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#define DMC_CHN8_RD_DONE_INT_ST_MASK 0x00000004
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#define DMC_CHN8_WR_TIMEOUT_INT_ST_OFFSET 1
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#define DMC_CHN8_WR_TIMEOUT_INT_ST_MASK 0x00000002
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#define DMC_CHN8_RD_TIMEOUT_INT_ST_OFFSET 0
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#define DMC_CHN8_RD_TIMEOUT_INT_ST_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMC_CHN8_INTR_ENA_ADDR 0x188
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#define DMC_CHN8_EXCEED_SIZE_INT_ENA_OFFSET 5
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#define DMC_CHN8_EXCEED_SIZE_INT_ENA_MASK 0x00000020
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#define DMC_CHN8_PUSH_EXCEED_INT_ENA_OFFSET 4
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#define DMC_CHN8_PUSH_EXCEED_INT_ENA_MASK 0x00000010
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#define DMC_CHN8_WR_DONE_INT_ENA_OFFSET 3
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#define DMC_CHN8_WR_DONE_INT_ENA_MASK 0x00000008
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#define DMC_CHN8_RD_DONE_INT_ENA_OFFSET 2
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#define DMC_CHN8_RD_DONE_INT_ENA_MASK 0x00000004
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#define DMC_CHN8_WR_TIMEOUT_INT_ENA_OFFSET 1
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#define DMC_CHN8_WR_TIMEOUT_INT_ENA_MASK 0x00000002
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#define DMC_CHN8_RD_TIMEOUT_INT_ENA_OFFSET 0
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#define DMC_CHN8_RD_TIMEOUT_INT_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMC_CHN8_INTR_CLR_ADDR 0x18C
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#define DMC_CHN8_EXCEED_SIZE_INT_CLR_OFFSET 5
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#define DMC_CHN8_EXCEED_SIZE_INT_CLR_MASK 0x00000020
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#define DMC_CHN8_PUSH_EXCEED_INT_CLR_OFFSET 4
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#define DMC_CHN8_PUSH_EXCEED_INT_CLR_MASK 0x00000010
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#define DMC_CHN8_WR_DONE_INT_CLR_OFFSET 3
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#define DMC_CHN8_WR_DONE_INT_CLR_MASK 0x00000008
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#define DMC_CHN8_RD_DONE_INT_CLR_OFFSET 2
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#define DMC_CHN8_RD_DONE_INT_CLR_MASK 0x00000004
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#define DMC_CHN8_WR_TIMEOUT_INT_CLR_OFFSET 1
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#define DMC_CHN8_WR_TIMEOUT_INT_CLR_MASK 0x00000002
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#define DMC_CHN8_RD_TIMEOUT_INT_CLR_OFFSET 0
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#define DMC_CHN8_RD_TIMEOUT_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMC_CHN9_INTR_RAW_ADDR 0x190
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#define DMC_CHN9_EXCEED_SIZE_INT_RAW_OFFSET 5
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#define DMC_CHN9_EXCEED_SIZE_INT_RAW_MASK 0x00000020
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#define DMC_CHN9_PUSH_EXCEED_INT_RAW_OFFSET 4
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#define DMC_CHN9_PUSH_EXCEED_INT_RAW_MASK 0x00000010
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#define DMC_CHN9_WR_DONE_INT_RAW_OFFSET 3
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#define DMC_CHN9_WR_DONE_INT_RAW_MASK 0x00000008
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#define DMC_CHN9_RD_DONE_INT_RAW_OFFSET 2
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#define DMC_CHN9_RD_DONE_INT_RAW_MASK 0x00000004
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#define DMC_CHN9_WR_TIMEOUT_INT_RAW_OFFSET 1
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#define DMC_CHN9_WR_TIMEOUT_INT_RAW_MASK 0x00000002
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#define DMC_CHN9_RD_TIMEOUT_INT_RAW_OFFSET 0
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#define DMC_CHN9_RD_TIMEOUT_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMC_CHN9_INTR_ST_ADDR 0x194
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#define DMC_CHN9_EXCEED_SIZE_INT_ST_OFFSET 5
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#define DMC_CHN9_EXCEED_SIZE_INT_ST_MASK 0x00000020
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#define DMC_CHN9_PUSH_EXCEED_INT_ST_OFFSET 4
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#define DMC_CHN9_PUSH_EXCEED_INT_ST_MASK 0x00000010
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#define DMC_CHN9_WR_DONE_INT_ST_OFFSET 3
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#define DMC_CHN9_WR_DONE_INT_ST_MASK 0x00000008
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#define DMC_CHN9_RD_DONE_INT_ST_OFFSET 2
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#define DMC_CHN9_RD_DONE_INT_ST_MASK 0x00000004
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#define DMC_CHN9_WR_TIMEOUT_INT_ST_OFFSET 1
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#define DMC_CHN9_WR_TIMEOUT_INT_ST_MASK 0x00000002
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#define DMC_CHN9_RD_TIMEOUT_INT_ST_OFFSET 0
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#define DMC_CHN9_RD_TIMEOUT_INT_ST_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMC_CHN9_INTR_ENA_ADDR 0x198
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#define DMC_CHN9_EXCEED_SIZE_INT_ENA_OFFSET 5
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#define DMC_CHN9_EXCEED_SIZE_INT_ENA_MASK 0x00000020
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#define DMC_CHN9_PUSH_EXCEED_INT_ENA_OFFSET 4
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#define DMC_CHN9_PUSH_EXCEED_INT_ENA_MASK 0x00000010
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#define DMC_CHN9_WR_DONE_INT_ENA_OFFSET 3
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#define DMC_CHN9_WR_DONE_INT_ENA_MASK 0x00000008
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#define DMC_CHN9_RD_DONE_INT_ENA_OFFSET 2
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#define DMC_CHN9_RD_DONE_INT_ENA_MASK 0x00000004
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#define DMC_CHN9_WR_TIMEOUT_INT_ENA_OFFSET 1
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#define DMC_CHN9_WR_TIMEOUT_INT_ENA_MASK 0x00000002
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#define DMC_CHN9_RD_TIMEOUT_INT_ENA_OFFSET 0
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#define DMC_CHN9_RD_TIMEOUT_INT_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMC_CHN9_INTR_CLR_ADDR 0x19C
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#define DMC_CHN9_EXCEED_SIZE_INT_CLR_OFFSET 5
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#define DMC_CHN9_EXCEED_SIZE_INT_CLR_MASK 0x00000020
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#define DMC_CHN9_PUSH_EXCEED_INT_CLR_OFFSET 4
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#define DMC_CHN9_PUSH_EXCEED_INT_CLR_MASK 0x00000010
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#define DMC_CHN9_WR_DONE_INT_CLR_OFFSET 3
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#define DMC_CHN9_WR_DONE_INT_CLR_MASK 0x00000008
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#define DMC_CHN9_RD_DONE_INT_CLR_OFFSET 2
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#define DMC_CHN9_RD_DONE_INT_CLR_MASK 0x00000004
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#define DMC_CHN9_WR_TIMEOUT_INT_CLR_OFFSET 1
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#define DMC_CHN9_WR_TIMEOUT_INT_CLR_MASK 0x00000002
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#define DMC_CHN9_RD_TIMEOUT_INT_CLR_OFFSET 0
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#define DMC_CHN9_RD_TIMEOUT_INT_CLR_MASK 0x00000001
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//HW module read/write macro
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#define DMC_RF_READ_REG(addr) SOC_READ_REG(DMC_RF_BASEADDR + addr)
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#define DMC_RF_WRITE_REG(addr,value) SOC_WRITE_REG(DMC_RF_BASEADDR + addr,value)
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