819 lines
28 KiB
C
819 lines
28 KiB
C
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//-----------------------------------
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#define CFG_TMI0_BAND0_ADDR 0x0000
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#define CFG_TMI0_BAND0_PBFL_OFFSET 8
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#define CFG_TMI0_BAND0_PBFL_MASK 0x000FFF00
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#define CFG_TMI0_BAND0_NUMSYM_OFFSET 0
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#define CFG_TMI0_BAND0_NUMSYM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_TMI0_BAND1_ADDR 0x0004
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#define CFG_TMI0_BAND1_PBFL_OFFSET 8
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#define CFG_TMI0_BAND1_PBFL_MASK 0x000FFF00
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#define CFG_TMI0_BAND1_NUMSYM_OFFSET 0
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#define CFG_TMI0_BAND1_NUMSYM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_TMI0_BAND2_ADDR 0x0008
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#define CFG_TMI0_BAND2_PBFL_OFFSET 8
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#define CFG_TMI0_BAND2_PBFL_MASK 0x000FFF00
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#define CFG_TMI0_BAND2_NUMSYM_OFFSET 0
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#define CFG_TMI0_BAND2_NUMSYM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_TMI0_BAND3_ADDR 0x000C
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#define CFG_TMI0_BAND3_PBFL_OFFSET 8
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#define CFG_TMI0_BAND3_PBFL_MASK 0x000FFF00
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#define CFG_TMI0_BAND3_NUMSYM_OFFSET 0
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#define CFG_TMI0_BAND3_NUMSYM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_TMI1_BAND0_ADDR 0x0010
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#define CFG_TMI1_BAND0_PBFL_OFFSET 8
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#define CFG_TMI1_BAND0_PBFL_MASK 0x000FFF00
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#define CFG_TMI1_BAND0_NUMSYM_OFFSET 0
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#define CFG_TMI1_BAND0_NUMSYM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_TMI1_BAND1_ADDR 0x0014
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#define CFG_TMI1_BAND1_PBFL_OFFSET 8
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#define CFG_TMI1_BAND1_PBFL_MASK 0x000FFF00
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#define CFG_TMI1_BAND1_NUMSYM_OFFSET 0
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#define CFG_TMI1_BAND1_NUMSYM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_TMI1_BAND2_ADDR 0x0018
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#define CFG_TMI1_BAND2_PBFL_OFFSET 8
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#define CFG_TMI1_BAND2_PBFL_MASK 0x000FFF00
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#define CFG_TMI1_BAND2_NUMSYM_OFFSET 0
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#define CFG_TMI1_BAND2_NUMSYM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_TMI1_BAND3_ADDR 0x001C
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#define CFG_TMI1_BAND3_PBFL_OFFSET 8
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#define CFG_TMI1_BAND3_PBFL_MASK 0x000FFF00
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#define CFG_TMI1_BAND3_NUMSYM_OFFSET 0
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#define CFG_TMI1_BAND3_NUMSYM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_TMI2_BAND0_ADDR 0x0020
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#define CFG_TMI2_BAND0_PBFL_OFFSET 8
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#define CFG_TMI2_BAND0_PBFL_MASK 0x000FFF00
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#define CFG_TMI2_BAND0_NUMSYM_OFFSET 0
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#define CFG_TMI2_BAND0_NUMSYM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_TMI2_BAND1_ADDR 0x0024
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#define CFG_TMI2_BAND1_PBFL_OFFSET 8
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#define CFG_TMI2_BAND1_PBFL_MASK 0x000FFF00
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#define CFG_TMI2_BAND1_NUMSYM_OFFSET 0
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#define CFG_TMI2_BAND1_NUMSYM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_TMI2_BAND2_ADDR 0x0028
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#define CFG_TMI2_BAND2_PBFL_OFFSET 8
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#define CFG_TMI2_BAND2_PBFL_MASK 0x000FFF00
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#define CFG_TMI2_BAND2_NUMSYM_OFFSET 0
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#define CFG_TMI2_BAND2_NUMSYM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_TMI2_BAND3_ADDR 0x002C
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#define CFG_TMI2_BAND3_PBFL_OFFSET 8
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#define CFG_TMI2_BAND3_PBFL_MASK 0x000FFF00
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#define CFG_TMI2_BAND3_NUMSYM_OFFSET 0
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#define CFG_TMI2_BAND3_NUMSYM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_TMI3_BAND0_ADDR 0x0030
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#define CFG_TMI3_BAND0_PBFL_OFFSET 8
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#define CFG_TMI3_BAND0_PBFL_MASK 0x000FFF00
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#define CFG_TMI3_BAND0_NUMSYM_OFFSET 0
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#define CFG_TMI3_BAND0_NUMSYM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_TMI3_BAND1_ADDR 0x0034
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#define CFG_TMI3_BAND1_PBFL_OFFSET 8
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#define CFG_TMI3_BAND1_PBFL_MASK 0x000FFF00
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#define CFG_TMI3_BAND1_NUMSYM_OFFSET 0
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#define CFG_TMI3_BAND1_NUMSYM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_TMI3_BAND2_ADDR 0x0038
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#define CFG_TMI3_BAND2_PBFL_OFFSET 8
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#define CFG_TMI3_BAND2_PBFL_MASK 0x000FFF00
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#define CFG_TMI3_BAND2_NUMSYM_OFFSET 0
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#define CFG_TMI3_BAND2_NUMSYM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_TMI3_BAND3_ADDR 0x003C
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#define CFG_TMI3_BAND3_PBFL_OFFSET 8
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#define CFG_TMI3_BAND3_PBFL_MASK 0x000FFF00
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#define CFG_TMI3_BAND3_NUMSYM_OFFSET 0
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#define CFG_TMI3_BAND3_NUMSYM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_RX_FILTER_0_ADDR 0x0040
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#define CFG_FC_CRCERR_FILTER_DIS_OFFSET 3
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#define CFG_FC_CRCERR_FILTER_DIS_MASK 0x00000008
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#define CFG_NID_FILTER_DIS_OFFSET 2
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#define CFG_NID_FILTER_DIS_MASK 0x00000004
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#define CFG_MPDU_DTEI_FILTER_DIS_OFFSET 1
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#define CFG_MPDU_DTEI_FILTER_DIS_MASK 0x00000002
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#define CFG_BEACON_PHASE_FILTER_DIS_OFFSET 0
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#define CFG_BEACON_PHASE_FILTER_DIS_MASK 0x00000001
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//-----------------------------------
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#define CFG_RX_FILTER_1_ADDR 0x0078
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#define CFG_SG_DT_FILTER_BLACKLIST_0_OFFSET 28
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#define CFG_SG_DT_FILTER_BLACKLIST_0_MASK 0xF0000000
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#define CFG_SG_DT_FILTER_BLACKLIST_1_OFFSET 24
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#define CFG_SG_DT_FILTER_BLACKLIST_1_MASK 0x0F000000
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#define CFG_SG_DT_FILTER_BLACKLIST_2_OFFSET 20
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#define CFG_SG_DT_FILTER_BLACKLIST_2_MASK 0x00F00000
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#define CFG_SG_DT_FILTER_BLACKLIST_3_OFFSET 16
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#define CFG_SG_DT_FILTER_BLACKLIST_3_MASK 0x000F0000
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#define CFG_GP_DT_FILTER_BLACKLIST_0_OFFSET 12
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#define CFG_GP_DT_FILTER_BLACKLIST_0_MASK 0x0000F000
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#define CFG_GP_DT_FILTER_BLACKLIST_1_OFFSET 8
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#define CFG_GP_DT_FILTER_BLACKLIST_1_MASK 0x00000F00
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#define CFG_GP_DT_FILTER_BLACKLIST_2_OFFSET 4
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#define CFG_GP_DT_FILTER_BLACKLIST_2_MASK 0x000000F0
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#define CFG_GP_DT_FILTER_BLACKLIST_3_OFFSET 0
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#define CFG_GP_DT_FILTER_BLACKLIST_3_MASK 0x0000000F
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//-----------------------------------
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#define CFG_VLAN0_NID_ADDR 0x0044
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#define CFG_VLAN0_NID_OFFSET 0
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#define CFG_VLAN0_NID_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN1_NID_ADDR 0x0048
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#define CFG_VLAN1_NID_OFFSET 0
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#define CFG_VLAN1_NID_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN2_NID_ADDR 0x004C
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#define CFG_VLAN2_NID_OFFSET 0
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#define CFG_VLAN2_NID_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN3_NID_ADDR 0x0050
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#define CFG_VLAN3_NID_OFFSET 0
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#define CFG_VLAN3_NID_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN4_NID_ADDR 0x0054
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#define CFG_VLAN4_NID_OFFSET 0
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#define CFG_VLAN4_NID_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN5_NID_ADDR 0x0058
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#define CFG_VLAN5_NID_OFFSET 0
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#define CFG_VLAN5_NID_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN6_NID_ADDR 0x005C
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#define CFG_VLAN6_NID_OFFSET 0
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#define CFG_VLAN6_NID_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN7_NID_ADDR 0x0060
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#define CFG_VLAN7_NID_OFFSET 0
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#define CFG_VLAN7_NID_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_RX_CTRL_ADDR 0x0064
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#define CFG_PB_HDR_TO_BUFFER_OFFSET 31
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#define CFG_PB_HDR_TO_BUFFER_MASK 0x80000000
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#define CFG_HASH_ENABLE_OFFSET 30
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#define CFG_HASH_ENABLE_MASK 0x40000000
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#define CFG_RX_FC_CRC_FROM_PHY_OFFSET 29
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#define CFG_RX_FC_CRC_FROM_PHY_MASK 0x20000000
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#define CFG_RX_PB_CRC_FROM_PHY_OFFSET 28
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#define CFG_RX_PB_CRC_FROM_PHY_MASK 0x10000000
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#define CFG_RX_GET_FC_FROM_PHY_OFFSET 27
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#define CFG_RX_GET_FC_FROM_PHY_MASK 0x08000000
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#define CFG_RX_BEACON_PLD_CRC_BY_SW_OFFSET 26
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#define CFG_RX_BEACON_PLD_CRC_BY_SW_MASK 0x04000000
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#define CFG_DBG_DISABLE_RX_OFFSET 25
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#define CFG_DBG_DISABLE_RX_MASK 0x02000000
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#define CFG_DBG_DISABLE_RX_VECTOR_OFFSET 24
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#define CFG_DBG_DISABLE_RX_VECTOR_MASK 0x01000000
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#define CFG_DBG_DISABLE_RX_FC_OFFSET 23
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#define CFG_DBG_DISABLE_RX_FC_MASK 0x00800000
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#define CFG_DBG_DISABLE_RX_PB_OFFSET 22
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#define CFG_DBG_DISABLE_RX_PB_MASK 0x00400000
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#define CFG_DBG_DISABLE_RX_ACK_OFFSET 21
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#define CFG_DBG_DISABLE_RX_ACK_MASK 0x00200000
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#define CFG_RX_PBNUM_FROM_PHY_OFFSET 20
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#define CFG_RX_PBNUM_FROM_PHY_MASK 0x00100000
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#define CFG_RX_PHY_FC_DONE_SEL_OFFSET 19
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#define CFG_RX_PHY_FC_DONE_SEL_MASK 0x00080000
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//-----------------------------------
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#define CFG_BUFFER_RING0_0_ADDR 0x0068
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#define CFG_RING0_PTR_OFFSET 0
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#define CFG_RING0_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BUFFER_RING0_1_ADDR 0x006c
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#define CFG_RING0_BUF_REENA_CLR_EN_OFFSET 26
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#define CFG_RING0_BUF_REENA_CLR_EN_MASK 0x04000000
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#define CFG_RING0_BUF_SIZE_FILTER_SEL_OFFSET 24
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#define CFG_RING0_BUF_SIZE_FILTER_SEL_MASK 0x03000000
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#define CFG_RING0_FILTER_OFFSET 20
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#define CFG_RING0_FILTER_MASK 0x00F00000
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#define CFG_RING0_BUF_SIZE_OFFSET 10
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#define CFG_RING0_BUF_SIZE_MASK 0x000FFC00
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#define CFG_RING0_BUF_NUM_OFFSET 0
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#define CFG_RING0_BUF_NUM_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BUFFER_RING0_2_ADDR 0x0070
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#define RING0_STATUS_OFFSET 31
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#define RING0_STATUS_MASK 0x80000000
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#define CFG_RING0_EN_OFFSET 30
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#define CFG_RING0_EN_MASK 0x40000000
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#define CFG_RING0_LOW_WATERMARK_OFFSET 20
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#define CFG_RING0_LOW_WATERMARK_MASK 0x3FF00000
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#define RO_RING0_WR_IDX_OFFSET 10
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#define RO_RING0_WR_IDX_MASK 0x000FFC00
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#define CFG_RING0_RD_IDX_OFFSET 0
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#define CFG_RING0_RD_IDX_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BUFFER_RING0_3_ADDR 0x0074
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#define CFG_RING0_BUF_EXCEED_CLR_OFFSET 31
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#define CFG_RING0_BUF_EXCEED_CLR_MASK 0x80000000
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#define RING0_WR_BUF_EXCEED_DEPTH_OFFSET 26
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#define RING0_WR_BUF_EXCEED_DEPTH_MASK 0x7C000000
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#define RING0_WR_BUF_EXCEED_CNT_OFFSET 22
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#define RING0_WR_BUF_EXCEED_CNT_MASK 0x03C00000
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#define CFG_RING0_DESC_EN_OFFSET 21
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#define CFG_RING0_DESC_EN_MASK 0x00200000
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#define CFG_RING0_PAYLOAD_EN_OFFSET 20
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#define CFG_RING0_PAYLOAD_EN_MASK 0x00100000
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#define CFG_RING0_DESC_OFFSET_OFFSET 10
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#define CFG_RING0_DESC_OFFSET_MASK 0x000FFC00
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#define CFG_RING0_PAYLOAD_OFFSET_OFFSET 0
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#define CFG_RING0_PAYLOAD_OFFSET_MASK 0x000003FF
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//-----------------------------------
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#define CFG_RESP_CTRL_ADDR 0x007c
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#define CFG_HW_RESP_EN_OFFSET 0
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#define CFG_HW_RESP_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_BUFFER_RING1_0_ADDR 0x0080
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#define CFG_RING1_PTR_OFFSET 0
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#define CFG_RING1_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BUFFER_RING1_1_ADDR 0x0084
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#define CFG_RING1_BUF_REENA_CLR_EN_OFFSET 26
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#define CFG_RING1_BUF_REENA_CLR_EN_MASK 0x04000000
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#define CFG_RING1_BUF_SIZE_FILTER_SEL_OFFSET 24
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#define CFG_RING1_BUF_SIZE_FILTER_SEL_MASK 0x03000000
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#define CFG_RING1_FILTER_OFFSET 20
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#define CFG_RING1_FILTER_MASK 0x00F00000
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#define CFG_RING1_BUF_SIZE_OFFSET 10
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#define CFG_RING1_BUF_SIZE_MASK 0x000FFC00
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#define CFG_RING1_BUF_NUM_OFFSET 0
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#define CFG_RING1_BUF_NUM_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BUFFER_RING1_2_ADDR 0x0088
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#define RING1_STATUS_OFFSET 31
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#define RING1_STATUS_MASK 0x80000000
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#define CFG_RING1_EN_OFFSET 30
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#define CFG_RING1_EN_MASK 0x40000000
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#define CFG_RING1_LOW_WATERMARK_OFFSET 20
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#define CFG_RING1_LOW_WATERMARK_MASK 0x3FF00000
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#define RO_RING1_WR_IDX_OFFSET 10
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#define RO_RING1_WR_IDX_MASK 0x000FFC00
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#define CFG_RING1_RD_IDX_OFFSET 0
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#define CFG_RING1_RD_IDX_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BUFFER_RING1_3_ADDR 0x008c
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#define CFG_RING1_BUF_EXCEED_CLR_OFFSET 31
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#define CFG_RING1_BUF_EXCEED_CLR_MASK 0x80000000
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#define RING1_WR_BUF_EXCEED_DEPTH_OFFSET 26
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#define RING1_WR_BUF_EXCEED_DEPTH_MASK 0x7C000000
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#define RING1_WR_BUF_EXCEED_CNT_OFFSET 22
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#define RING1_WR_BUF_EXCEED_CNT_MASK 0x03C00000
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#define CFG_RING1_DESC_EN_OFFSET 21
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#define CFG_RING1_DESC_EN_MASK 0x00200000
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#define CFG_RING1_PAYLOAD_EN_OFFSET 20
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#define CFG_RING1_PAYLOAD_EN_MASK 0x00100000
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#define CFG_RING1_DESC_OFFSET_OFFSET 10
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#define CFG_RING1_DESC_OFFSET_MASK 0x000FFC00
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#define CFG_RING1_PAYLOAD_OFFSET_OFFSET 0
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#define CFG_RING1_PAYLOAD_OFFSET_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BUFFER_RING2_0_ADDR 0x0090
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#define CFG_RING2_PTR_OFFSET 0
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#define CFG_RING2_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BUFFER_RING2_1_ADDR 0x0094
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#define CFG_RING2_BUF_REENA_CLR_EN_OFFSET 26
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#define CFG_RING2_BUF_REENA_CLR_EN_MASK 0x04000000
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#define CFG_RING2_BUF_SIZE_FILTER_SEL_OFFSET 24
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#define CFG_RING2_BUF_SIZE_FILTER_SEL_MASK 0x03000000
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#define CFG_RING2_FILTER_OFFSET 20
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#define CFG_RING2_FILTER_MASK 0x00F00000
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#define CFG_RING2_BUF_SIZE_OFFSET 10
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#define CFG_RING2_BUF_SIZE_MASK 0x000FFC00
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#define CFG_RING2_BUF_NUM_OFFSET 0
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#define CFG_RING2_BUF_NUM_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BUFFER_RING2_2_ADDR 0x0098
|
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#define RING2_STATUS_OFFSET 31
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#define RING2_STATUS_MASK 0x80000000
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#define CFG_RING2_EN_OFFSET 30
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#define CFG_RING2_EN_MASK 0x40000000
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#define CFG_RING2_LOW_WATERMARK_OFFSET 20
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#define CFG_RING2_LOW_WATERMARK_MASK 0x3FF00000
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#define RO_RING2_WR_IDX_OFFSET 10
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#define RO_RING2_WR_IDX_MASK 0x000FFC00
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#define CFG_RING2_RD_IDX_OFFSET 0
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#define CFG_RING2_RD_IDX_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BUFFER_RING2_3_ADDR 0x009c
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#define CFG_RING2_BUF_EXCEED_CLR_OFFSET 31
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#define CFG_RING2_BUF_EXCEED_CLR_MASK 0x80000000
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#define RING2_WR_BUF_EXCEED_DEPTH_OFFSET 26
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#define RING2_WR_BUF_EXCEED_DEPTH_MASK 0x7C000000
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#define RING2_WR_BUF_EXCEED_CNT_OFFSET 22
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#define RING2_WR_BUF_EXCEED_CNT_MASK 0x03C00000
|
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#define CFG_RING2_DESC_EN_OFFSET 21
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#define CFG_RING2_DESC_EN_MASK 0x00200000
|
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#define CFG_RING2_PAYLOAD_EN_OFFSET 20
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#define CFG_RING2_PAYLOAD_EN_MASK 0x00100000
|
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#define CFG_RING2_DESC_OFFSET_OFFSET 10
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#define CFG_RING2_DESC_OFFSET_MASK 0x000FFC00
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#define CFG_RING2_PAYLOAD_OFFSET_OFFSET 0
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#define CFG_RING2_PAYLOAD_OFFSET_MASK 0x000003FF
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|
|
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//-----------------------------------
|
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#define CFG_BUFFER_RING3_0_ADDR 0x00a0
|
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#define CFG_RING3_PTR_OFFSET 0
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#define CFG_RING3_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BUFFER_RING3_1_ADDR 0x00a4
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#define CFG_RING3_BUF_REENA_CLR_EN_OFFSET 26
|
|
#define CFG_RING3_BUF_REENA_CLR_EN_MASK 0x04000000
|
|
#define CFG_RING3_BUF_SIZE_FILTER_SEL_OFFSET 24
|
|
#define CFG_RING3_BUF_SIZE_FILTER_SEL_MASK 0x03000000
|
|
#define CFG_RING3_FILTER_OFFSET 20
|
|
#define CFG_RING3_FILTER_MASK 0x00F00000
|
|
#define CFG_RING3_BUF_SIZE_OFFSET 10
|
|
#define CFG_RING3_BUF_SIZE_MASK 0x000FFC00
|
|
#define CFG_RING3_BUF_NUM_OFFSET 0
|
|
#define CFG_RING3_BUF_NUM_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUFFER_RING3_2_ADDR 0x00a8
|
|
#define RING3_STATUS_OFFSET 31
|
|
#define RING3_STATUS_MASK 0x80000000
|
|
#define CFG_RING3_EN_OFFSET 30
|
|
#define CFG_RING3_EN_MASK 0x40000000
|
|
#define CFG_RING3_LOW_WATERMARK_OFFSET 20
|
|
#define CFG_RING3_LOW_WATERMARK_MASK 0x3FF00000
|
|
#define RO_RING3_WR_IDX_OFFSET 10
|
|
#define RO_RING3_WR_IDX_MASK 0x000FFC00
|
|
#define CFG_RING3_RD_IDX_OFFSET 0
|
|
#define CFG_RING3_RD_IDX_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUFFER_RING3_3_ADDR 0x00ac
|
|
#define CFG_RING3_BUF_EXCEED_CLR_OFFSET 31
|
|
#define CFG_RING3_BUF_EXCEED_CLR_MASK 0x80000000
|
|
#define RING3_WR_BUF_EXCEED_DEPTH_OFFSET 26
|
|
#define RING3_WR_BUF_EXCEED_DEPTH_MASK 0x7C000000
|
|
#define RING3_WR_BUF_EXCEED_CNT_OFFSET 22
|
|
#define RING3_WR_BUF_EXCEED_CNT_MASK 0x03C00000
|
|
#define CFG_RING3_DESC_EN_OFFSET 21
|
|
#define CFG_RING3_DESC_EN_MASK 0x00200000
|
|
#define CFG_RING3_PAYLOAD_EN_OFFSET 20
|
|
#define CFG_RING3_PAYLOAD_EN_MASK 0x00100000
|
|
#define CFG_RING3_DESC_OFFSET_OFFSET 10
|
|
#define CFG_RING3_DESC_OFFSET_MASK 0x000FFC00
|
|
#define CFG_RING3_PAYLOAD_OFFSET_OFFSET 0
|
|
#define CFG_RING3_PAYLOAD_OFFSET_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUFFER_RING4_0_ADDR 0x00b0
|
|
#define CFG_RING4_PTR_OFFSET 0
|
|
#define CFG_RING4_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUFFER_RING4_1_ADDR 0x00b4
|
|
#define CFG_RING4_BUF_REENA_CLR_EN_OFFSET 26
|
|
#define CFG_RING4_BUF_REENA_CLR_EN_MASK 0x04000000
|
|
#define CFG_RING4_BUF_SIZE_FILTER_SEL_OFFSET 24
|
|
#define CFG_RING4_BUF_SIZE_FILTER_SEL_MASK 0x03000000
|
|
#define CFG_RING4_FILTER_OFFSET 20
|
|
#define CFG_RING4_FILTER_MASK 0x00F00000
|
|
#define CFG_RING4_BUF_SIZE_OFFSET 10
|
|
#define CFG_RING4_BUF_SIZE_MASK 0x000FFC00
|
|
#define CFG_RING4_BUF_NUM_OFFSET 0
|
|
#define CFG_RING4_BUF_NUM_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUFFER_RING4_2_ADDR 0x00b8
|
|
#define RING4_STATUS_OFFSET 31
|
|
#define RING4_STATUS_MASK 0x80000000
|
|
#define CFG_RING4_EN_OFFSET 30
|
|
#define CFG_RING4_EN_MASK 0x40000000
|
|
#define CFG_RING4_LOW_WATERMARK_OFFSET 20
|
|
#define CFG_RING4_LOW_WATERMARK_MASK 0x3FF00000
|
|
#define RO_RING4_WR_IDX_OFFSET 10
|
|
#define RO_RING4_WR_IDX_MASK 0x000FFC00
|
|
#define CFG_RING4_RD_IDX_OFFSET 0
|
|
#define CFG_RING4_RD_IDX_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUFFER_RING4_3_ADDR 0x00bc
|
|
#define CFG_RING4_BUF_EXCEED_CLR_OFFSET 31
|
|
#define CFG_RING4_BUF_EXCEED_CLR_MASK 0x80000000
|
|
#define RING4_WR_BUF_EXCEED_DEPTH_OFFSET 26
|
|
#define RING4_WR_BUF_EXCEED_DEPTH_MASK 0x7C000000
|
|
#define RING4_WR_BUF_EXCEED_CNT_OFFSET 22
|
|
#define RING4_WR_BUF_EXCEED_CNT_MASK 0x03C00000
|
|
#define CFG_RING4_DESC_EN_OFFSET 21
|
|
#define CFG_RING4_DESC_EN_MASK 0x00200000
|
|
#define CFG_RING4_PAYLOAD_EN_OFFSET 20
|
|
#define CFG_RING4_PAYLOAD_EN_MASK 0x00100000
|
|
#define CFG_RING4_DESC_OFFSET_OFFSET 10
|
|
#define CFG_RING4_DESC_OFFSET_MASK 0x000FFC00
|
|
#define CFG_RING4_PAYLOAD_OFFSET_OFFSET 0
|
|
#define CFG_RING4_PAYLOAD_OFFSET_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_RING0_DBG_CNT_ADDR 0x00c0
|
|
#define RING0_RX_DBG_CNT_OFFSET 0
|
|
#define RING0_RX_DBG_CNT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_RING1_DBG_CNT_ADDR 0x00c4
|
|
#define RING1_RX_DBG_CNT_OFFSET 0
|
|
#define RING1_RX_DBG_CNT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_RING2_DBG_CNT_ADDR 0x00c8
|
|
#define RING2_RX_DBG_CNT_OFFSET 0
|
|
#define RING2_RX_DBG_CNT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_RING3_DBG_CNT_ADDR 0x00cc
|
|
#define RING3_RX_DBG_CNT_OFFSET 0
|
|
#define RING3_RX_DBG_CNT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_RING4_DBG_CNT_ADDR 0x00d0
|
|
#define RING4_RX_DBG_CNT_OFFSET 0
|
|
#define RING4_RX_DBG_CNT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DBG_CNT_CLR_ADDR 0x00d4
|
|
#define CFG_RING4_RX_DBG_CLR_OFFSET 4
|
|
#define CFG_RING4_RX_DBG_CLR_MASK 0x00000010
|
|
#define CFG_RING3_RX_DBG_CLR_OFFSET 3
|
|
#define CFG_RING3_RX_DBG_CLR_MASK 0x00000008
|
|
#define CFG_RING2_RX_DBG_CLR_OFFSET 2
|
|
#define CFG_RING2_RX_DBG_CLR_MASK 0x00000004
|
|
#define CFG_RING1_RX_DBG_CLR_OFFSET 1
|
|
#define CFG_RING1_RX_DBG_CLR_MASK 0x00000002
|
|
#define CFG_RING0_RX_DBG_CLR_OFFSET 0
|
|
#define CFG_RING0_RX_DBG_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_FC_DBG_CNT_ADDR 0x00d8
|
|
#define RX_FC_DBG_CNT_OFFSET 0
|
|
#define RX_FC_DBG_CNT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_DBG_CNT_CLR_ADDR 0x00dc
|
|
#define CFG_RX_ABORT_DBG_CNT_CLR_OFFSET 2
|
|
#define CFG_RX_ABORT_DBG_CNT_CLR_MASK 0x00000004
|
|
#define CFG_PKT_DETECTED_DBG_CNT_CLR_OFFSET 1
|
|
#define CFG_PKT_DETECTED_DBG_CNT_CLR_MASK 0x00000002
|
|
#define CFG_RX_FC_DBG_CNT_CLR_OFFSET 0
|
|
#define CFG_RX_FC_DBG_CNT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_PKT_DETECTED_CNT_ADDR 0x00e0
|
|
#define PKT_DETECTED_DBG_CNT_OFFSET 0
|
|
#define PKT_DETECTED_DBG_CNT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_TIMEOUT_0_ADDR 0x00e4
|
|
#define CFG_RX_VEC_TIMEOUT_OFFSET 0
|
|
#define CFG_RX_VEC_TIMEOUT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_TIMEOUT_1_ADDR 0x00e8
|
|
#define CFG_RX_PB_TIMEOUT_OFFSET 0
|
|
#define CFG_RX_PB_TIMEOUT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_TIMEOUT_2_ADDR 0x00ec
|
|
#define CFG_RX_RESP_TX_TIMEOUT_OFFSET 0
|
|
#define CFG_RX_RESP_TX_TIMEOUT_MASK 0x000FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_TIMEOUT_ACT_ADDR 0x00f0
|
|
#define CFG_RX_ABORT_SEL_OFFSET 3
|
|
#define CFG_RX_ABORT_SEL_MASK 0x00000008
|
|
#define CFG_TDMA_RX_ABORT_WAIT_CIFS_OFFSET 2
|
|
#define CFG_TDMA_RX_ABORT_WAIT_CIFS_MASK 0x00000004
|
|
#define CFG_MAC_RX_ABORT_ACT_OFFSET 1
|
|
#define CFG_MAC_RX_ABORT_ACT_MASK 0x00000002
|
|
#define CFG_RX_TIMEOUT_ACT_OFFSET 0
|
|
#define CFG_RX_TIMEOUT_ACT_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_ABORT_DBG_CNT_ADDR 0x00f4
|
|
#define RX_ABORT_DBG_CNT_OFFSET 0
|
|
#define RX_ABORT_DBG_CNT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_RESP_TX_METHOD_ADDR 0x00f8
|
|
#define CFG_RX_RESP_TX_FROM_TD_OFFSET 0
|
|
#define CFG_RX_RESP_TX_FROM_TD_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SG_PBNUM_SEL_ADDR 0x00fc
|
|
#define CFG_SG_SOF_PBNUM_OPT_OFFSET 1
|
|
#define CFG_SG_SOF_PBNUM_OPT_MASK 0x00000002
|
|
#define CFG_SG_BCN_PBNUM_FORCE_ONE_OFFSET 0
|
|
#define CFG_SG_BCN_PBNUM_FORCE_ONE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_ECO_ADDR 0x0100
|
|
#define CFG_LAST_PB_ECO_SEL_OFFSET 1
|
|
#define CFG_LAST_PB_ECO_SEL_MASK 0x00000002
|
|
#define CFG_FIRST_PB_ECO_SEL_OFFSET 0
|
|
#define CFG_FIRST_PB_ECO_SEL_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_RX_NTB_TIMESTAMP_ADDR 0x0104
|
|
#define RX_NTB_TIMESTAMP_OFFSET 0
|
|
#define RX_NTB_TIMESTAMP_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_RX_LOCAL_TIMESTAMP_ADDR 0x0108
|
|
#define RX_LOCAL_TIMESTAMP_OFFSET 0
|
|
#define RX_LOCAL_TIMESTAMP_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_RX_ZC_OFFSET_ADDR 0x010C
|
|
#define RX_ZC_OFFSET_OFFSET 0
|
|
#define RX_ZC_OFFSET_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_ABORT_DBG_CNT1_ADDR 0x0110
|
|
#define RX_FRAG_ABORT_DBG_CNT_OFFSET 16
|
|
#define RX_FRAG_ABORT_DBG_CNT_MASK 0xFFFF0000
|
|
#define TDMA_ABORT_RX_DBG_CNT_OFFSET 0
|
|
#define TDMA_ABORT_RX_DBG_CNT_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_ABORT_DBG_CNT2_ADDR 0x0114
|
|
#define RX_TIMEOUT_ABORT_DBG_CNT_OFFSET 0
|
|
#define RX_TIMEOUT_ABORT_DBG_CNT_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_PHY_INFO_CRC_SEL_ADDR 0x0118
|
|
#define CFG_PHY_CRC_INFO_SEL_OFFSET 0
|
|
#define CFG_PHY_CRC_INFO_SEL_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_RX_FC_0_ADDR 0x011C
|
|
#define RO_RX_FC_0_OFFSET 0
|
|
#define RO_RX_FC_0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_RX_FC_1_ADDR 0x0120
|
|
#define RO_RX_FC_1_OFFSET 0
|
|
#define RO_RX_FC_1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_RX_FC_2_ADDR 0x0124
|
|
#define RO_RX_FC_2_OFFSET 0
|
|
#define RO_RX_FC_2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_RX_FC_3_ADDR 0x0128
|
|
#define RO_RX_FC_3_OFFSET 0
|
|
#define RO_RX_FC_3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_FC_DONE_SEL_ADDR 0x012c
|
|
#define CFG_FC_ACK_WAIT_PARSER_DONE_OFFSET 0
|
|
#define CFG_FC_ACK_WAIT_PARSER_DONE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUF_FIX_ADDR 0x0130
|
|
#define CFG_RX_BUF_RING_BUG_FIX_OFFSET 0
|
|
#define CFG_RX_BUF_RING_BUG_FIX_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_DBG_ADDR 0x0134
|
|
#define CFG_RX_FIFO_OVERFLOW_CLR_OFFSET 1
|
|
#define CFG_RX_FIFO_OVERFLOW_CLR_MASK 0x00000002
|
|
#define RO_RX_FIFO_OVERFLOW_OFFSET 0
|
|
#define RO_RX_FIFO_OVERFLOW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING_DESC_DBG_CLR_ADDR 0x0138
|
|
#define RING4_DESC_DBG_CLR_OFFSET 4
|
|
#define RING4_DESC_DBG_CLR_MASK 0x00000010
|
|
#define RING3_DESC_DBG_CLR_OFFSET 3
|
|
#define RING3_DESC_DBG_CLR_MASK 0x00000008
|
|
#define RING2_DESC_DBG_CLR_OFFSET 2
|
|
#define RING2_DESC_DBG_CLR_MASK 0x00000004
|
|
#define RING1_DESC_DBG_CLR_OFFSET 1
|
|
#define RING1_DESC_DBG_CLR_MASK 0x00000002
|
|
#define RING0_DESC_DBG_CLR_OFFSET 0
|
|
#define RING0_DESC_DBG_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING0_ATTEN_DBG_ADDR 0x0140
|
|
#define RING0_ATTEN_DBG_OFFSET 0
|
|
#define RING0_ATTEN_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING1_ATTEN_DBG_ADDR 0x0144
|
|
#define RING1_ATTEN_DBG_OFFSET 0
|
|
#define RING1_ATTEN_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING2_ATTEN_DBG_ADDR 0x0148
|
|
#define RING2_ATTEN_DBG_OFFSET 0
|
|
#define RING2_ATTEN_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING3_ATTEN_DBG_ADDR 0x014c
|
|
#define RING3_ATTEN_DBG_OFFSET 0
|
|
#define RING3_ATTEN_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING4_ATTEN_DBG_ADDR 0x0150
|
|
#define RING4_ATTEN_DBG_OFFSET 0
|
|
#define RING4_ATTEN_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING0_OTHER_DBG_ADDR 0x0154
|
|
#define RING0_OTHER_DBG_OFFSET 0
|
|
#define RING0_OTHER_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING1_OTHER_DBG_ADDR 0x0158
|
|
#define RING1_OTHER_DBG_OFFSET 0
|
|
#define RING1_OTHER_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING2_OTHER_DBG_ADDR 0x015c
|
|
#define RING2_OTHER_DBG_OFFSET 0
|
|
#define RING2_OTHER_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING3_OTHER_DBG_ADDR 0x0160
|
|
#define RING3_OTHER_DBG_OFFSET 0
|
|
#define RING3_OTHER_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING4_OTHER_DBG_ADDR 0x0164
|
|
#define RING4_OTHER_DBG_OFFSET 0
|
|
#define RING4_OTHER_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING0_NTB_LOW_DBG_ADDR 0x0170
|
|
#define RING0_NTB_LOW_DBG_OFFSET 0
|
|
#define RING0_NTB_LOW_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING1_NTB_LOW_DBG_ADDR 0x0174
|
|
#define RING1_NTB_LOW_DBG_OFFSET 0
|
|
#define RING1_NTB_LOW_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING2_NTB_LOW_DBG_ADDR 0x0178
|
|
#define RING2_NTB_LOW_DBG_OFFSET 0
|
|
#define RING2_NTB_LOW_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING3_NTB_LOW_DBG_ADDR 0x017c
|
|
#define RING3_NTB_LOW_DBG_OFFSET 0
|
|
#define RING3_NTB_LOW_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING4_NTB_LOW_DBG_ADDR 0x0180
|
|
#define RING4_NTB_LOW_DBG_OFFSET 0
|
|
#define RING4_NTB_LOW_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING0_NTB_HIG_DBG_ADDR 0x0184
|
|
#define RING0_NTB_HIG_DBG_OFFSET 0
|
|
#define RING0_NTB_HIG_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING1_NTB_HIG_DBG_ADDR 0x0188
|
|
#define RING1_NTB_HIG_DBG_OFFSET 0
|
|
#define RING1_NTB_HIG_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING2_NTB_HIG_DBG_ADDR 0x018c
|
|
#define RING2_NTB_HIG_DBG_OFFSET 0
|
|
#define RING2_NTB_HIG_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING3_NTB_HIG_DBG_ADDR 0x0190
|
|
#define RING3_NTB_HIG_DBG_OFFSET 0
|
|
#define RING3_NTB_HIG_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RING4_NTB_HIG_DBG_ADDR 0x0194
|
|
#define RING4_NTB_HIG_DBG_OFFSET 0
|
|
#define RING4_NTB_HIG_DBG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_FD_OVF_CRTL_ADDR 0x01a0
|
|
#define CFG_RX_ERR_FD_OVF_ABORT_PHY_EN_OFFSET 4
|
|
#define CFG_RX_ERR_FD_OVF_ABORT_PHY_EN_MASK 0x00000010
|
|
#define CFG_RX_ERR_FD_OVF_ABORT_MAC_EN_OFFSET 3
|
|
#define CFG_RX_ERR_FD_OVF_ABORT_MAC_EN_MASK 0x00000008
|
|
#define CFG_RX_FD_OVF_BACK_ZERO_EN_OFFSET 2
|
|
#define CFG_RX_FD_OVF_BACK_ZERO_EN_MASK 0x00000004
|
|
#define CFG_PHY_OVF_RX_ABORT_REASON_1_EN_OFFSET 1
|
|
#define CFG_PHY_OVF_RX_ABORT_REASON_1_EN_MASK 0x00000002
|
|
#define CFG_PHY_OVF_RX_ABORT_REASON_0_EN_OFFSET 0
|
|
#define CFG_PHY_OVF_RX_ABORT_REASON_0_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_MPDU_WR_IDX_0_ADDR 0x01b0
|
|
#define RO_RING2_MPDU_BUF_WR_IDX_OFFSET 20
|
|
#define RO_RING2_MPDU_BUF_WR_IDX_MASK 0x3FF00000
|
|
#define RO_RING1_MPDU_BUF_WR_IDX_OFFSET 10
|
|
#define RO_RING1_MPDU_BUF_WR_IDX_MASK 0x000FFC00
|
|
#define RO_RING0_MPDU_BUF_WR_IDX_OFFSET 0
|
|
#define RO_RING0_MPDU_BUF_WR_IDX_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_BUF_MPDU_WR_IDX_1_ADDR 0x01b4
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#define RO_RING4_MPDU_BUF_WR_IDX_OFFSET 10
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#define RO_RING4_MPDU_BUF_WR_IDX_MASK 0x000FFC00
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#define RO_RING3_MPDU_BUF_WR_IDX_OFFSET 0
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#define RO_RING3_MPDU_BUF_WR_IDX_MASK 0x000003FF
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//-----------------------------------
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#define CFG_RX_DBG_OPTION_CTRL_ADDR 0x01b8
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#define CFG_RX_ABORT_LOCK_CLR_OFFSET 0
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#define CFG_RX_ABORT_LOCK_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_RX_DBG_OPTION_STS_0_ADDR 0x01bc
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#define RO_RX_ABORT_DBG_STS_0_OFFSET 0
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#define RO_RX_ABORT_DBG_STS_0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_RX_DBG_OPTION_STS_1_ADDR 0x01c0
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#define RO_RX_ABORT_DBG_STS_1_OFFSET 0
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#define RO_RX_ABORT_DBG_STS_1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_RX_TIMEOUT_3_ADDR 0x01c4
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#define CFG_RX_FC_TIMEOUT_OFFSET 0
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#define CFG_RX_FC_TIMEOUT_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_RESP_SACK_INT_CTRL_ADDR 0x01c8
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#define CFG_RESP_WAIT_TD_TIMEOUT_DELTA_OFFSET 0
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#define CFG_RESP_WAIT_TD_TIMEOUT_DELTA_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_RX_PB_OPT_ADDR 0x01d0
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#define CFG_RX_PB_NUM_GP_LOCK_EN_OFFSET 5
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#define CFG_RX_PB_NUM_GP_LOCK_EN_MASK 0x00000020
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#define CFG_RX_PB_NUM_SG_LOCK_EN_OFFSET 4
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#define CFG_RX_PB_NUM_SG_LOCK_EN_MASK 0x00000010
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#define CFG_RX_PARSE_DONE_CHOS_OFFSET 3
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#define CFG_RX_PARSE_DONE_CHOS_MASK 0x00000008
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#define CFG_RX_BURST_FSM_PROTECT_EN_OFFSET 2
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#define CFG_RX_BURST_FSM_PROTECT_EN_MASK 0x00000004
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#define CFG_BST_SND_FC_DATA_UPDATE_OPT_OFFSET 1
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#define CFG_BST_SND_FC_DATA_UPDATE_OPT_MASK 0x00000002
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#define CFG_PB_HDR_CRC_OPT_OFFSET 0
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#define CFG_PB_HDR_CRC_OPT_MASK 0x00000001
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//HW module read/write macro
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#define RGF_RX_READ_REG(addr) SOC_READ_REG(RGF_RX_BASEADDR + addr)
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#define RGF_RX_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_RX_BASEADDR + addr,value)
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