111 lines
3.4 KiB
C
111 lines
3.4 KiB
C
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//-----------------------------------
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#define CFG_INTC_RVER_ADDR 0x0000
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#define INTC_RF_VER_OFFSET 0
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#define INTC_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_INT_SRC_ADDR 0x0004
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#define INT_SRC_OFFSET 0
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#define INT_SRC_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_ENA_ADDR 0x0008
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#define INT_ENA_OFFSET 0
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#define INT_ENA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_PRI_SEL_ADDR 0x000c
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#define INT_PRI_SEL_OFFSET 0
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#define INT_PRI_SEL_MASK 0x00000007
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//-----------------------------------
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#define CFG_INT_PRI_CFG0_ADDR 0x0010
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#define INT7_PRI_CFG_OFFSET 28
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#define INT7_PRI_CFG_MASK 0x70000000
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#define INT6_PRI_CFG_OFFSET 24
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#define INT6_PRI_CFG_MASK 0x07000000
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#define INT5_PRI_CFG_OFFSET 20
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#define INT5_PRI_CFG_MASK 0x00700000
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#define INT4_PRI_CFG_OFFSET 16
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#define INT4_PRI_CFG_MASK 0x00070000
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#define INT3_PRI_CFG_OFFSET 12
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#define INT3_PRI_CFG_MASK 0x00007000
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#define INT2_PRI_CFG_OFFSET 8
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#define INT2_PRI_CFG_MASK 0x00000700
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#define INT1_PRI_CFG_OFFSET 4
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#define INT1_PRI_CFG_MASK 0x00000070
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#define INT0_PRI_CFG_OFFSET 0
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#define INT0_PRI_CFG_MASK 0x00000007
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//-----------------------------------
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#define CFG_INT_PRI_CFG1_ADDR 0x0014
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#define INT15_PRI_CFG_OFFSET 28
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#define INT15_PRI_CFG_MASK 0x70000000
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#define INT14_PRI_CFG_OFFSET 24
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#define INT14_PRI_CFG_MASK 0x07000000
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#define INT13_PRI_CFG_OFFSET 20
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#define INT13_PRI_CFG_MASK 0x00700000
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#define INT12_PRI_CFG_OFFSET 16
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#define INT12_PRI_CFG_MASK 0x00070000
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#define INT11_PRI_CFG_OFFSET 12
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#define INT11_PRI_CFG_MASK 0x00007000
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#define INT10_PRI_CFG_OFFSET 8
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#define INT10_PRI_CFG_MASK 0x00000700
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#define INT9_PRI_CFG_OFFSET 4
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#define INT9_PRI_CFG_MASK 0x00000070
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#define INT8_PRI_CFG_OFFSET 0
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#define INT8_PRI_CFG_MASK 0x00000007
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//-----------------------------------
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#define CFG_INT_PRI_CFG2_ADDR 0x0018
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#define INT23_PRI_CFG_OFFSET 28
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#define INT23_PRI_CFG_MASK 0x70000000
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#define INT22_PRI_CFG_OFFSET 24
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#define INT22_PRI_CFG_MASK 0x07000000
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#define INT21_PRI_CFG_OFFSET 20
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#define INT21_PRI_CFG_MASK 0x00700000
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#define INT20_PRI_CFG_OFFSET 16
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#define INT20_PRI_CFG_MASK 0x00070000
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#define INT19_PRI_CFG_OFFSET 12
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#define INT19_PRI_CFG_MASK 0x00007000
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#define INT18_PRI_CFG_OFFSET 8
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#define INT18_PRI_CFG_MASK 0x00000700
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#define INT17_PRI_CFG_OFFSET 4
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#define INT17_PRI_CFG_MASK 0x00000070
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#define INT16_PRI_CFG_OFFSET 0
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#define INT16_PRI_CFG_MASK 0x00000007
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//-----------------------------------
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#define CFG_INT_PRI_CFG3_ADDR 0x001c
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#define INT31_PRI_CFG_OFFSET 28
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#define INT31_PRI_CFG_MASK 0x70000000
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#define INT30_PRI_CFG_OFFSET 24
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#define INT30_PRI_CFG_MASK 0x07000000
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#define INT29_PRI_CFG_OFFSET 20
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#define INT29_PRI_CFG_MASK 0x00700000
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#define INT28_PRI_CFG_OFFSET 16
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#define INT28_PRI_CFG_MASK 0x00070000
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#define INT27_PRI_CFG_OFFSET 12
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#define INT27_PRI_CFG_MASK 0x00007000
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#define INT26_PRI_CFG_OFFSET 8
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#define INT26_PRI_CFG_MASK 0x00000700
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#define INT25_PRI_CFG_OFFSET 4
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#define INT25_PRI_CFG_MASK 0x00000070
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#define INT24_PRI_CFG_OFFSET 0
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#define INT24_PRI_CFG_MASK 0x00000007
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//-----------------------------------
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#define CFG_INT_STS_ADDR 0x0020
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#define INT_STS_OFFSET 0
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#define INT_STS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_PRI_STS_ADDR 0x0024
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#define INT_PRI_STS_OFFSET 0
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#define INT_PRI_STS_MASK 0x00000007
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//HW module read/write macro
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#define INTC_READ_REG(addr) SOC_READ_REG(INTC_BASEADDR + addr)
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#define INTC_WRITE_REG(addr,value) SOC_WRITE_REG(INTC_BASEADDR + addr,value)
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