kunlun/plc/halmac/hw/misc/mac_hw_misc.c

/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/

/* os shim includes */
#include "os_types.h"

/* mac module internal includes */
#include "mac_vdev.h"
#include "mac_pdev.h"
#include "mac_status.h"
#include "hw_reg_api.h"
#include "mac_sys_reg.h"
#include "mac_cmn_hw.h"

/* public api includes */
#include "plc_fr.h"
#include "plc_protocol.h"
#include "chip_reg_base.h"
#include "multi_nid_sync.h"

#if HW_PLATFORM == HW_PLATFORM_SIMU

#include "simulator_txrx.h"

void mac_config_nid(mac_vdev_t *vdev, uint32_t nid)
{
    simulator_config_nid(&g_mac_pdev[vdev->ref_pdev_id]->simu,
        vdev->vdev_id, nid);
}

uint32_t mac_get_hw_nid()
{
    return 0;
}

void mac_config_role(mac_vdev_t *vdev, uint8_t role)
{
    (void)vdev;
    (void)role;
}

uint32_t mac_get_hw_role()
{
    return 0;
}

void mac_config_tei(mac_vdev_t *vdev, uint16_t tei)
{
    simulator_config_tei(&g_mac_pdev[vdev->ref_pdev_id]->simu,
        vdev->vdev_id, (uint32_t)tei);
}

uint32_t mac_get_hw_tei()
{
    return 0;
}

uint32_t mac_enable_hw_ntb_adjust(uint32_t enable)
{
    /* kunlun 1 has no this feature */
    (void)enable;
    return 0;
}

void mac_ena_hw_ntb_wrap_fix(uint8_t enable)
{
    (void)enable;
}

/* mac ppm calibration */
uint32_t mac_ppm_cal_set(PHY_CAL_UNIT_ID cal_unit, \
    int16_t ppm_err, uint32_t rate_mode)
{
    /* kunlun 1 has no this feature */
    (void)cal_unit;
    (void)ppm_err;
    (void)rate_mode;
    return 0;
}

void mac_dump_buf_from_cvg(void)
{
    return;
}

void mac_hw_sync_ppm_clr(uint8_t pdev_id)
{
    (void)pdev_id;
    return;
}

#else /* HW_PLATFORM */
int32_t IRAM_ATTR mac_config_ntb_delta_from_isr(uint8_t is_positive, uint32_t delta_ntb)
{
    int32_t ret = 0;
#if ENA_WAR_911
    /* war for hw bug, low bit overflow high bit not + 1 */
    uint32_t cur_ntb = mac_sched_get_ntb(NULL);
    if (is_positive) {
        /* positive */
        uint64_t temp_ntb = (uint64_t)cur_ntb + delta_ntb;
        if (iot_uint64_higher32(temp_ntb) >= 1) {
            uint32_t temp_delta = MAX_UINT32_NTB - cur_ntb;
            if (temp_delta > RESERVE_NTB) {
                uint32_t temp_delta_a = temp_delta - (RESERVE_NTB >> 1);
                ret = delta_ntb - temp_delta_a;
                delta_ntb = temp_delta_a;
                /* drop the other part of delta */
            } else {
                /* drop delta */
                ret = delta_ntb;
                delta_ntb = 0;
            }
        }
    } else {
        /* negative */
        if (cur_ntb < delta_ntb) {
            ret -= (delta_ntb - cur_ntb);
            delta_ntb = cur_ntb;
        }
    }
#endif

    uint32_t tmp;
    tmp = RGF_MAC_READ_REG(CFG_NTB_SYNC_1_ADDR);
    REG_FIELD_SET(CFG_NTB_DELTA_VAL, tmp, delta_ntb);
    RGF_MAC_WRITE_REG(CFG_NTB_SYNC_1_ADDR, tmp);

#if ENA_WAR_728
    /* Note: not fix this */
    #define WAR_728_CFG_NTB_DELTA_REG_TIME      3
    uint32_t ntb_fix_before, ntb_fix_after;

    tmp = RGF_MAC_READ_REG(CFG_NTB_SYNC_0_ADDR);
    ntb_fix_before = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
    REG_FIELD_SET(CFG_NTB_DELTA_VAL_SIGN, tmp, is_positive);
    REG_FIELD_SET(CFG_MODIFY_NTB_EN, tmp, 1);
    RGF_MAC_WRITE_REG(CFG_NTB_SYNC_0_ADDR, tmp);
    /* Note: not fix this. 3 mschine cycles must be delayed */
    __asm volatile("nop\n");
    __asm volatile("nop\n");
    __asm volatile("nop\n");
    ntb_fix_after = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);

    ntb_fix_before += (is_positive ? delta_ntb : (-delta_ntb))
        + WAR_728_CFG_NTB_DELTA_REG_TIME;
    ret += ((ntb_fix_before > ntb_fix_after) ? 1 : 0);
#else
    tmp = RGF_MAC_READ_REG(CFG_NTB_SYNC_0_ADDR);
    REG_FIELD_SET(CFG_NTB_DELTA_VAL_SIGN, tmp, is_positive);
    REG_FIELD_SET(CFG_MODIFY_NTB_EN, tmp, 1);
    RGF_MAC_WRITE_REG(CFG_NTB_SYNC_0_ADDR, tmp);
#endif
    return ret;
}

/* mac_config_nid() - config network ID to HW
 * @vdev:   pointer to mac vdev
 * @nid:    the network ID to be set
 */
void mac_config_nid(mac_vdev_t *vdev, uint32_t nid)
{
    uint32_t value;
    (void)vdev;

    value = RGF_MAC_READ_REG(CFG_MYNID_ADDR);
    value &= ~CFG_MYNID_MASK;
    value |= (nid << CFG_MYNID_OFFSET) & CFG_MYNID_MASK;
    RGF_MAC_WRITE_REG(CFG_MYNID_ADDR, value);
}

uint32_t mac_get_hw_nid()
{
    return RGF_MAC_READ_REG(CFG_MYNID_ADDR) & CFG_MYNID_MASK;
}

void mac_config_role(mac_vdev_t *vdev, uint8_t role)
{
    uint32_t value;
    (void)vdev;

    value = RGF_MAC_READ_REG(CFG_MYSTAT_ADDR);
    if (role == PLC_DEV_ROLE_CCO) {
        value |= CFG_CCO_MODE_MASK;
    } else {
        value &= ~CFG_CCO_MODE_MASK;
    }
    RGF_MAC_WRITE_REG(CFG_MYSTAT_ADDR, value);
}

uint32_t mac_get_hw_role()
{
    return RGF_MAC_READ_REG(CFG_MYSTAT_ADDR) & CFG_CCO_MODE_MASK;
}

void mac_config_tei(mac_vdev_t *vdev, uint16_t tei)
{
    uint32_t value;
    (void)vdev;

    value = RGF_MAC_READ_REG(CFG_MYTEI_ADDR);
    value &= ~CFG_MYTEI_MASK;
    value |= (((uint32_t)tei) << CFG_MYTEI_OFFSET) & CFG_MYTEI_MASK;
    RGF_MAC_WRITE_REG(CFG_MYTEI_ADDR, value);
}

uint32_t mac_get_hw_tei()
{
    return RGF_MAC_READ_REG(CFG_MYTEI_ADDR) & CFG_MYTEI_MASK;
}

void mac_set_sg_sack_snr(uint32_t ena_sw_cfg, int8_t snr)
{
    uint32_t tmp;
    tmp = RGF_MAC_READ_REG(CFG_TX_CTRL1_ADDR);
    REG_FIELD_SET(CFG_SG_SNR_BY_SW, tmp, ena_sw_cfg);
    REG_FIELD_SET(CFG_SG_SNR, tmp, snr);
    RGF_MAC_WRITE_REG(CFG_TX_CTRL1_ADDR, tmp);
    return;
}

uint32_t mac_enable_hw_ntb_adjust(uint32_t enable)
{
    /* kunlun 1 has no this feature */
    (void)enable;
    return 0;
}

void mac_ena_hw_ntb_wrap_fix(uint8_t enable)
{
    /* kunlun1 not supported */
    (void)enable;
}

/* mac ppm calibration */
uint32_t mac_ppm_cal_set(PHY_CAL_UNIT_ID cal_unit, \
    int16_t ppm_err, uint32_t rate_mode)
{
    (void)cal_unit;
    (void)ppm_err;
    (void)rate_mode;
    return 0;
}

void mac_dump_buf_from_cvg(void)
{
    phy_get_status_printf_force();
    mac_get_status_printf();
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    mac_dump_buf(MAC_DUMP_TYPE_3, (uint32_t *)INTC_BASEADDR, 7, \
        (uint32_t *)RGF_MAC_BASEADDR, 86, \
        (uint32_t *)RGF_RX_BASEADDR, 69, true);
#endif
    return;
}

void IRAM_ATTR mac_hw_sync_ppm_clr(uint8_t pdev_id)
{
    if (mac_multi_sync_get_ena(pdev_id)) {
        /* reset rx ppm */
        phy_ppm_set(g_phy_ctxt.dep.phy_ppm_init, BB_PPM_RX_ONLY);
    }
    return;
}

#endif /* HW_PLATFORM */