431 lines
13 KiB
C
431 lines
13 KiB
C
/****************************************************************************
|
|
|
|
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
|
|
|
|
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
|
|
be copied by any method or incorporated into another program without
|
|
the express written consent of Aerospace C.Power. This Information or any portion
|
|
thereof remains the property of Aerospace C.Power. The Information contained herein
|
|
is believed to be accurate and Aerospace C.Power assumes no responsibility or
|
|
liability for its use in any way and conveys no license or title under
|
|
any patent or copyright and makes no representation or warranty that this
|
|
Information is free from patent or copyright infringement.
|
|
|
|
****************************************************************************/
|
|
|
|
/* os shim includes */
|
|
#include "iot_config.h"
|
|
#include "os_types.h"
|
|
|
|
/* plc public api includes */
|
|
#include "plc_fr.h"
|
|
#include "plc_const.h"
|
|
|
|
/* driver includes */
|
|
#include "iot_irq.h"
|
|
#include "bb_cpu_mac_isr.h"
|
|
#include "bb_cpu_mac_init.h"
|
|
#include "bb_cpu_fsm.h"
|
|
#include "bb_cpu_timer.h"
|
|
#include "mac_rf_isr.h"
|
|
#include "iot_io.h"
|
|
|
|
#include "hw_reg_api.h"
|
|
#include "rfplc_reg_base.h"
|
|
#include "rf_mac_reg.h"
|
|
#include "mac_sys_reg.h"
|
|
#include "plc_mac_cfg.h"
|
|
#include "mac_rf_common_hw.h"
|
|
#include "mac_rf_timer.h"
|
|
|
|
/* define mac isr ctxt */
|
|
rf_mac_isr_ctx_t g_rf_mac_isr_1 = { 0 };
|
|
rf_mac_isr_ctx_t *p_rf_mac_isr_1 = &g_rf_mac_isr_1;
|
|
|
|
static uint8_t stf_occur = 0;
|
|
|
|
/* get hw intrrupt status, hw interrupt */
|
|
static uint32_t bb_cpu_mac_get_hw_interrupt_sts()
|
|
{
|
|
return RF_MAC_READ_REG(CFG_RF_MAC_COMMON_INT_REG_7_ADDR);
|
|
}
|
|
|
|
/* clear hw intrrupt status, hw interrupt */
|
|
static void bb_cpu_mac_clear_hw_interrupt(uint32_t irq_sts)
|
|
{
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_5_ADDR, irq_sts);
|
|
}
|
|
|
|
/* get sw intrrupt status, hw interrupt */
|
|
static uint32_t bb_cpu_mac_get_sw_interrupt_sts()
|
|
{
|
|
return RF_MAC_READ_REG(CFG_RF_MAC_COMMON_INT_REG_27_ADDR);
|
|
}
|
|
|
|
/* clear sw intrrupt status, hw interrupt */
|
|
static void bb_cpu_mac_clear_sw_interrupt(uint32_t irq_sts)
|
|
{
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_25_ADDR, irq_sts);
|
|
}
|
|
|
|
static void bb_cpu_mac_hw_isr_reset(void)
|
|
{
|
|
/* disable all mac interrupt */
|
|
p_rf_mac_isr_1->isr_hw_mask = 0;
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_9_ADDR,
|
|
p_rf_mac_isr_1->isr_hw_mask);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_1_ADDR,
|
|
p_rf_mac_isr_1->isr_hw_mask);
|
|
|
|
/* clean up all pending interrupt */
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_5_ADDR,
|
|
RF_MAC_COMMON_IRQ_SW_CLR_CPU2_MASK);
|
|
}
|
|
|
|
static void bb_cpu_mac_sw_isr_reset(void)
|
|
{
|
|
/* disable all mac interrupt */
|
|
p_rf_mac_isr_1->isr_sw_mask = 0;
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_29_ADDR,
|
|
p_rf_mac_isr_1->isr_sw_mask);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_21_ADDR,
|
|
p_rf_mac_isr_1->isr_sw_mask);
|
|
|
|
/* clean up all pending interrupt */
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_25_ADDR,
|
|
RF_MAC_COMMON_SHARE_IRQ_SW_CLR_CPU2_MASK);
|
|
}
|
|
|
|
static void bb_cpu_mac_share_isr_reset(void)
|
|
{
|
|
/* disable all mac interrupt */
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_19_ADDR, 0);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_11_ADDR, 0);
|
|
|
|
/* clean up all pending interrupt */
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_15_ADDR,
|
|
RF_MAC_COMMON_SHARE_IRQ_SW_CLR_CPU2_MASK);
|
|
}
|
|
|
|
void bb_cpu_mac_hw_isr_enable(uint8_t id)
|
|
{
|
|
uint32_t int_mask;
|
|
int_mask = 1 << id;
|
|
if (!(p_rf_mac_isr_1->isr_hw_mask & int_mask)) {
|
|
p_rf_mac_isr_1->isr_hw_mask |= int_mask;
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_9_ADDR,
|
|
p_rf_mac_isr_1->isr_hw_mask);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_1_ADDR,
|
|
p_rf_mac_isr_1->isr_hw_mask);
|
|
}
|
|
}
|
|
|
|
void bb_cpu_mac_sw_isr_enable(uint8_t id)
|
|
{
|
|
uint32_t int_mask;
|
|
int_mask = 1 << id;
|
|
if (!(p_rf_mac_isr_1->isr_sw_mask & int_mask)) {
|
|
p_rf_mac_isr_1->isr_sw_mask |= int_mask;
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_29_ADDR,
|
|
p_rf_mac_isr_1->isr_sw_mask);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_21_ADDR,
|
|
p_rf_mac_isr_1->isr_sw_mask);
|
|
}
|
|
}
|
|
|
|
void bb_cpu_mac_hw_isr_disable(uint8_t id)
|
|
{
|
|
uint32_t int_mask;
|
|
int_mask = 1 << id;
|
|
if (p_rf_mac_isr_1->isr_hw_mask & int_mask) {
|
|
p_rf_mac_isr_1->isr_hw_mask &= ~int_mask;
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_9_ADDR,
|
|
p_rf_mac_isr_1->isr_hw_mask);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_1_ADDR,
|
|
p_rf_mac_isr_1->isr_hw_mask);
|
|
}
|
|
}
|
|
|
|
void bb_cpu_mac_sw_isr_disable(uint8_t id)
|
|
{
|
|
uint32_t int_mask;
|
|
int_mask = 1 << id;
|
|
if (p_rf_mac_isr_1->isr_sw_mask & int_mask) {
|
|
p_rf_mac_isr_1->isr_sw_mask &= ~int_mask;
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_19_ADDR,
|
|
p_rf_mac_isr_1->isr_sw_mask);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_11_ADDR,
|
|
p_rf_mac_isr_1->isr_sw_mask);
|
|
}
|
|
}
|
|
|
|
void bb_cpu_mac_set_sw_irq_to_maincpu(uint8_t id)
|
|
{
|
|
if (id < RF_MAC_SW_INT_MAX) {
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_22_ADDR, (1 << id));
|
|
} else {
|
|
IOT_ASSERT(id < RF_MAC_SW2_INT_MAX);
|
|
uint32_t timer_id = id - RF_MAC_SW_INT_MAX;
|
|
mac_rf_timer_stop(timer_id);
|
|
mac_rf_timer_set(timer_id, 1);
|
|
mac_rf_timer_start(timer_id);
|
|
}
|
|
}
|
|
|
|
void bb_cpu_mac_set_share_irq_to_maincpu(uint8_t id)
|
|
{
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_12_ADDR, (1 << id));
|
|
}
|
|
|
|
void bb_cpu_mac_isr_start(void)
|
|
{
|
|
/* enable soc irq */
|
|
iot_interrupt_unmask(p_rf_mac_isr_1->isr_hw_h);
|
|
iot_interrupt_unmask(p_rf_mac_isr_1->isr_sw_h);
|
|
iot_interrupt_unmask(p_rf_mac_isr_1->isr_timer_h);
|
|
}
|
|
|
|
void bb_cpu_mac_isr_stop(void)
|
|
{
|
|
/* disable soc irq */
|
|
iot_interrupt_mask(p_rf_mac_isr_1->isr_hw_h);
|
|
iot_interrupt_mask(p_rf_mac_isr_1->isr_sw_h);
|
|
iot_interrupt_mask(p_rf_mac_isr_1->isr_timer_h);
|
|
}
|
|
|
|
void bb_cpu_mac_isr_enable()
|
|
{
|
|
/* enable hw interrupt */
|
|
for (uint32_t i = 0; i < RF_MAC_ISR_HW_MAX_ID; i++) {
|
|
bb_cpu_mac_hw_isr_enable(i);
|
|
}
|
|
/* enable bb init and set channel interrupt */
|
|
bb_cpu_mac_sw_isr_enable(RF_MAC_SW_ISR_BB_INIT);
|
|
bb_cpu_mac_sw_isr_enable(RF_MAC_SW_ISR_SET_CHANNEL);
|
|
/* enable trigger hwq interrupt */
|
|
bb_cpu_mac_sw_isr_enable(RF_MAC_SW_ISR_CSMA_TX_CHECK);
|
|
bb_cpu_mac_sw_isr_enable(RF_MAC_SW_ISR_SYNC_SPI_VALUE);
|
|
bb_cpu_mac_sw_isr_enable(RF_MAC_SW_ISR_TX_TONE);
|
|
bb_cpu_mac_sw_isr_enable(RF_MAC_SW_ISR_SET_PS_IDLE);
|
|
bb_cpu_mac_sw_isr_enable(RF_MAC_SW_ISR_TX_CAL_UPDATE);
|
|
}
|
|
|
|
static uint32_t bb_cpu_mac_isr_handler(uint32_t vector, uint32_t data)
|
|
{
|
|
(void)vector;
|
|
(void)data;
|
|
uint32_t hw_int_status, sw_int_status, timer_int_sts;
|
|
|
|
/* get interrupt status */
|
|
hw_int_status = bb_cpu_mac_get_hw_interrupt_sts();
|
|
/* clear interrupt status */
|
|
bb_cpu_mac_clear_hw_interrupt(hw_int_status);
|
|
|
|
/* get interrupt status */
|
|
sw_int_status = bb_cpu_mac_get_sw_interrupt_sts();
|
|
/* clear interrupt status */
|
|
bb_cpu_mac_clear_sw_interrupt(sw_int_status);
|
|
|
|
/* get timer interrupt status */
|
|
timer_int_sts = bb_cpu_timer_get_timeout_id();
|
|
bb_cpu_timer_clr_timeout_id(timer_int_sts);
|
|
|
|
/* cmdlist done */
|
|
if (hw_int_status & (0x1 << RF_MAC_ISR_CMDLIST_DONE_ID)) {
|
|
/* set event to cmdlist done and stop tx/rx */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_CMDLIST_DONE_ID);
|
|
}
|
|
|
|
/* stop schedule */
|
|
if (hw_int_status & (0x1 << RF_MAC_ISR_EARLY_STOP_START_ID)) {
|
|
/* set event to stop schduel(reset tx/rx) */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_RST_ID);
|
|
}
|
|
|
|
/* vcs timeout
|
|
* NOTE: the priority of BB_CPU_ISR_VCS_TIMEOUT_ID higher than
|
|
* RF_MAC_ISR_BB_RX_STF_ID.
|
|
*/
|
|
if (timer_int_sts & (0x1 << BB_CPU_ISR_VCS_TIMEOUT_ID)) {
|
|
/* stop vcs working */
|
|
bb_cpu_stop_vcs_working_from_isr();
|
|
}
|
|
|
|
/* rx stf */
|
|
if (hw_int_status & (0x1 << RF_MAC_ISR_BB_RX_STF_ID)) {
|
|
/* pull vcs up */
|
|
bb_cpu_mac_set_vcs_sts_from_isr(1);
|
|
/* set stf occour */
|
|
stf_occur = 1;
|
|
/* set eifs */
|
|
bb_cpu_set_vcs_timer_from_isr(RF_MAC_EIFS_US, 1);
|
|
/* increase rx stf cnt */
|
|
mac_rf_rx_stf_cnt_inc();
|
|
}
|
|
|
|
/* tx abort */
|
|
if (hw_int_status & (0x1 << RF_MAC_ISR_TX_ABORT_ID)) {
|
|
/* set event to tx abort */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_TX_ABORT_ID);
|
|
}
|
|
|
|
/* rx abort */
|
|
if (hw_int_status & (0x1 << RF_MAC_ISR_RX_ABORT_ID)) {
|
|
/* set event to rx abort */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_RX_ABORT_ID);
|
|
}
|
|
|
|
/* backoff timeout */
|
|
if (hw_int_status & (0x1 << RF_MAC_ISR_BACKOFF_TIMEOUT_ID)) {
|
|
/* set event to backoff timeout */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_BACKOFF_TIMEOUT_ID);
|
|
}
|
|
|
|
/* rx start */
|
|
if (hw_int_status & (0x1 << RF_MAC_ISR_RX_START_ID)) {
|
|
stf_occur = 0;
|
|
/* set event to rx start */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_MAC_RX_START_ID);
|
|
}
|
|
|
|
/* rx timeout */
|
|
if (timer_int_sts & (0x1 << BB_CPU_ISR_RX_TIMEOUT_ID)) {
|
|
/* set event to rx timeout */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_RX_TIMEOUT_ID);
|
|
}
|
|
|
|
/* tx start */
|
|
if (hw_int_status & (0x1 << RF_MAC_ISR_TX_START_ID)) {
|
|
/* set event to start tx */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_MAC_TX_START_ID);
|
|
}
|
|
|
|
/* tx timeout */
|
|
if (timer_int_sts & (0x1 << BB_CPU_ISR_TX_TIMEOUT_ID)) {
|
|
/* set event to tx timeout */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_TX_TIMEOUT_ID);
|
|
}
|
|
|
|
/* wait sack timeout */
|
|
if (timer_int_sts & (0x1 << BB_CPU_ISR_WAIT_SACK_TIMEOUT_ID)) {
|
|
/* in conflict scenarios, backoff eifs */
|
|
/* pull vcs up */
|
|
bb_cpu_mac_set_vcs_sts_from_isr(1);
|
|
/* set eifs */
|
|
bb_cpu_set_vcs_timer_from_isr(RF_MAC_EIFS_US, 0);
|
|
/* set event to wait sack timeout */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_WAIT_SACK_TIMEOUT_ID);
|
|
}
|
|
|
|
/* wait reset timeout */
|
|
if (timer_int_sts & (0x1 << BB_CPU_ISR_RST_TIMEOUT_ID)) {
|
|
/* set event to wait reset timeout */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_RST_TIMEOUT_ID);
|
|
}
|
|
|
|
/* bb tx done */
|
|
if (hw_int_status & (0x1 << RF_MAC_ISR_BB_TX_DONE_ID)) {
|
|
/* set event to tx complete */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_TX_COMP_ID);
|
|
}
|
|
|
|
/* bb rx sig done */
|
|
if (hw_int_status & (0x1 << RF_MAC_ISR_BB_RX_SIG_ID)) {
|
|
if (!stf_occur) {
|
|
/* pull vcs up */
|
|
bb_cpu_mac_set_vcs_sts_from_isr(1);
|
|
/* set eifs */
|
|
bb_cpu_set_vcs_timer_from_isr(RF_MAC_EIFS_US, 1);
|
|
mac_rf_lost_stf_cnt_inc();
|
|
}
|
|
/* set event to rx sig */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_RX_SIG_ID);
|
|
}
|
|
|
|
/* bb rx phr done */
|
|
if (hw_int_status & (0x1 << RF_MAC_ISR_BB_RX_PHR_ID)) {
|
|
/* set event to rx phy header */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_RX_PHR_ID);
|
|
}
|
|
|
|
/* bb rx pld start */
|
|
if (hw_int_status & (0x1 << RF_MAC_ISR_BB_RX_PLD_START_ID)) {
|
|
/* set event to rx pld start */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_RX_PLD_START_ID);
|
|
}
|
|
|
|
/* bb init */
|
|
if (sw_int_status & (0x1 << RF_MAC_SW_ISR_BB_INIT)) {
|
|
/* set event to bb init */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_BB_INIT_ID);
|
|
}
|
|
|
|
/* bb set channel */
|
|
if (sw_int_status & (0x1 << RF_MAC_SW_ISR_SET_CHANNEL)) {
|
|
/* set event to set channel */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_SET_CHANNEL_ID);
|
|
}
|
|
|
|
/* bb early stop done */
|
|
if (hw_int_status & (0x1 << RF_MAC_ISR_EARLY_STOP_DONE_ID)) {
|
|
/* set isr is vaild */
|
|
bb_cpu_set_isr_vaild_from_isr(1);
|
|
}
|
|
|
|
/* csma q tx check */
|
|
if (sw_int_status & (0x1 << RF_MAC_SW_ISR_CSMA_TX_CHECK)) {
|
|
/* csma q tx check */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_CSMA_TX_CHECK_ID);
|
|
}
|
|
|
|
/* hplc cpu sync rf spi */
|
|
if (sw_int_status & (0x1 << RF_MAC_SW_ISR_SYNC_SPI_VALUE)) {
|
|
/* csma q tx check */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_SYNC_SPI_ID);
|
|
}
|
|
|
|
/* hplc cpu tx tone */
|
|
if (sw_int_status & (0x1 << RF_MAC_SW_ISR_TX_TONE)) {
|
|
/* tx tone */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_TX_TONE_ID);
|
|
}
|
|
|
|
/* hplc cpu set power save idle */
|
|
if (sw_int_status & (0x1 << RF_MAC_SW_ISR_SET_PS_IDLE)) {
|
|
/* set power save idle */
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_PS_IDLE_ID);
|
|
}
|
|
|
|
/* hplc cpu request tx cal update */
|
|
if (sw_int_status & (0x1 << RF_MAC_SW_ISR_TX_CAL_UPDATE)) {
|
|
bb_cpu_set_event_from_isr(BB_CPU_EVENT_TX_CAL_UPDATE_ID);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void bb_cpu_mac_isr_init(void)
|
|
{
|
|
bb_cpu_mac_hw_isr_reset();
|
|
bb_cpu_mac_sw_isr_reset();
|
|
bb_cpu_mac_share_isr_reset();
|
|
|
|
/* just need init hw interrupt(common isr) */
|
|
/* hw irq need isr handle */
|
|
p_rf_mac_isr_1->isr_hw_h = iot_interrupt_create(HAL_VECTOR_RFMAC_INT1,
|
|
HAL_INTR_PRI_7, (iot_addrword_t)NULL, bb_cpu_mac_isr_handler);
|
|
p_rf_mac_isr_1->isr_sw_h = iot_interrupt_create(HAL_VECTOR_RFMAC_INT1,
|
|
HAL_INTR_PRI_7, (iot_addrword_t)NULL, bb_cpu_mac_isr_handler);
|
|
|
|
iot_interrupt_attach(p_rf_mac_isr_1->isr_hw_h);
|
|
iot_interrupt_attach(p_rf_mac_isr_1->isr_sw_h);
|
|
|
|
/* timer irq need isr handle */
|
|
p_rf_mac_isr_1->isr_timer_h =
|
|
iot_interrupt_create(HAL_VECTOR_RFMAC_TIMEOUT_INT1, HAL_INTR_PRI_6,
|
|
(iot_addrword_t)NULL, bb_cpu_mac_isr_handler);
|
|
|
|
iot_interrupt_attach(p_rf_mac_isr_1->isr_timer_h);
|
|
}
|
|
|