474 lines
16 KiB
C
Executable File
474 lines
16 KiB
C
Executable File
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//-----------------------------------
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#define CFG_DDR_REG_RVER_ADDR 0x0
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#define DDR_RF_VER_OFFSET 0
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#define DDR_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DDR_RST_CFG_ADDR 0x4
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#define SAMPLE_REG_SOFT_RST_OFFSET 7
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#define SAMPLE_REG_SOFT_RST_MASK 0x00000080
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#define RXTX_RAM_SOFT_RST_OFFSET 6
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#define RXTX_RAM_SOFT_RST_MASK 0x00000040
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#define DL_SOFT_RST_OFFSET 5
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#define DL_SOFT_RST_MASK 0x00000020
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#define CHIP_PWR_UP_OFFSET 4
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#define CHIP_PWR_UP_MASK 0x00000010
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#define ARBIT_INIT_OFFSET 3
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#define ARBIT_INIT_MASK 0x00000008
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#define SOFT_FSM_RST_OFFSET 2
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#define SOFT_FSM_RST_MASK 0x00000004
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#define DL0_SOFT_RST_OFFSET 1
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#define DL0_SOFT_RST_MASK 0x00000002
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#define DL12_SOFT_RST_OFFSET 0
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#define DL12_SOFT_RST_MASK 0x00000001
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//-----------------------------------
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#define CFG_DDR_PROPERTY_CFG_ADDR 0x8
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#define CS3_SW_SEL_OFFSET 18
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#define CS3_SW_SEL_MASK 0x00040000
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#define CS2_SW_SEL_OFFSET 17
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#define CS2_SW_SEL_MASK 0x00020000
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#define CS1_SW_SEL_OFFSET 16
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#define CS1_SW_SEL_MASK 0x00010000
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#define CS0_SW_SEL_OFFSET 15
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#define CS0_SW_SEL_MASK 0x00008000
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#define DDR_CP1_LDO_SEL1P8_B_OFFSET 14
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#define DDR_CP1_LDO_SEL1P8_B_MASK 0x00004000
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#define DDR_CP0_LDO_SEL1P8_B_OFFSET 13
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#define DDR_CP0_LDO_SEL1P8_B_MASK 0x00002000
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#define PAD_CLK_FRC_ON_OFFSET 12
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#define PAD_CLK_FRC_ON_MASK 0x00001000
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#define CS3_FRC_ON_OFFSET 11
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#define CS3_FRC_ON_MASK 0x00000800
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#define CS2_FRC_ON_OFFSET 10
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#define CS2_FRC_ON_MASK 0x00000400
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#define CS1_FRC_ON_OFFSET 9
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#define CS1_FRC_ON_MASK 0x00000200
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#define CS0_FRC_ON_OFFSET 8
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#define CS0_FRC_ON_MASK 0x00000100
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#define CS_SIZE_OFFSET 4
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#define CS_SIZE_MASK 0x000000F0
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#define DEV_CS_INTG_OFFSET 2
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#define DEV_CS_INTG_MASK 0x00000004
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#define DEV_X8_X16_MODE_OFFSET 1
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#define DEV_X8_X16_MODE_MASK 0x00000002
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#define DQS_DM_SEPARATE_OFFSET 0
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#define DQS_DM_SEPARATE_MASK 0x00000001
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//-----------------------------------
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#define CFG_DDR_GEN_CMD_ST_ADDR 0xC
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#define GEN_CMD_DONE_OFFSET 12
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#define GEN_CMD_DONE_MASK 0x00001000
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#define CMD_ST_TOTAL_DLY_OFFSET 4
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#define CMD_ST_TOTAL_DLY_MASK 0x000007F0
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#define GEN_CMD_EARLY_NUM_OFFSET 0
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#define GEN_CMD_EARLY_NUM_MASK 0x0000000F
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//-----------------------------------
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#define CFG_DDR_CMD_DLY_CFG_ADDR 0x10
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#define DEV_RD_LATENCY_OFFSET 20
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#define DEV_RD_LATENCY_MASK 0x00F00000
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#define DEV_WR_LATENCY_OFFSET 16
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#define DEV_WR_LATENCY_MASK 0x000F0000
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#define CMD_INST_DUMMY_DLY_OFFSET 12
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#define CMD_INST_DUMMY_DLY_MASK 0x0000F000
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#define CMD_A2_DUMMY_DLY_OFFSET 8
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#define CMD_A2_DUMMY_DLY_MASK 0x00000F00
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#define CMD_A1_DUMMY_DLY_OFFSET 4
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#define CMD_A1_DUMMY_DLY_MASK 0x000000F0
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#define CMD_A0_DUMMY_DLY_OFFSET 0
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#define CMD_A0_DUMMY_DLY_MASK 0x0000000F
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//-----------------------------------
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#define CFG_DDR_PAGE_BOUNDARY_ADDR 0x14
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#define DDR_PAGE_BOUNDARY_OFFSET 0
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#define DDR_PAGE_BOUNDARY_MASK 0x0000000F
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//-----------------------------------
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#define CFG_DDR_SPEC_REG_CFG_ADDR 0x18
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#define DEV_MD1_ADDR_OFFSET 24
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#define DEV_MD1_ADDR_MASK 0xFF000000
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#define CALIB_MD1_VAL_OFFSET 16
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#define CALIB_MD1_VAL_MASK 0x00FF0000
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#define DEV_MD0_ADDR_OFFSET 8
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#define DEV_MD0_ADDR_MASK 0x0000FF00
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#define CALIB_MD0_VAL_OFFSET 0
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#define CALIB_MD0_VAL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_DDR_SOFT_CMD_CFG0_ADDR 0x1C
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#define DEV_OPERATION_SW_OFFSET 8
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#define DEV_OPERATION_SW_MASK 0x00000100
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#define DEV_CMD_SW_OFFSET 0
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#define DEV_CMD_SW_MASK 0x000000FF
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//-----------------------------------
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#define CFG_DDR_SOFT_CMD_CFG1_ADDR 0x20
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#define DEV_ADDR_SW_OFFSET 0
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#define DEV_ADDR_SW_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DDR_DL_TRAINING_CFG0_ADDR 0x24
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#define TRAINING_FORCE_DONE_OFFSET 14
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#define TRAINING_FORCE_DONE_MASK 0x00004000
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#define TRAINING_AUTO_EN_OFFSET 13
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#define TRAINING_AUTO_EN_MASK 0x00002000
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#define DL12_TRAINING_FORCE_START_OFFSET 12
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#define DL12_TRAINING_FORCE_START_MASK 0x00001000
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#define DL12_CNT_VALUE_SW_OFFSET 4
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#define DL12_CNT_VALUE_SW_MASK 0x00000FF0
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#define DL12_CFG_DLY_OFFSET 0
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#define DL12_CFG_DLY_MASK 0x0000000F
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//-----------------------------------
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#define CFG_DDR_DL_DEMO_TRAINING_CFG0_ADDR 0x28
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#define DL0_TRAINING_FORCE_START_OFFSET 19
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#define DL0_TRAINING_FORCE_START_MASK 0x00080000
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#define DL0_MONITIOR_EB_OFFSET 18
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#define DL0_MONITIOR_EB_MASK 0x00040000
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#define DL0_MONITIOR_RESTART_OFFSET 17
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#define DL0_MONITIOR_RESTART_MASK 0x00020000
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#define DL0_TRAINING_AUTO_EN_OFFSET 16
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#define DL0_TRAINING_AUTO_EN_MASK 0x00010000
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#define DL0_FETCH_RESULT_DLY_OFFSET 8
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#define DL0_FETCH_RESULT_DLY_MASK 0x0000FF00
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#define DL0_MONITIOR_DLY_OFFSET 0
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#define DL0_MONITIOR_DLY_MASK 0x000000FF
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//-----------------------------------
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#define CFG_DDR_TX_DL_TRAINING_CFG_ADDR 0x2C
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#define TX_DL_EB_OFFSET 8
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#define TX_DL_EB_MASK 0x00000100
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#define TX_DL_CFG_DATA_OFFSET 0
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#define TX_DL_CFG_DATA_MASK 0x000000FF
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//-----------------------------------
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#define CFG_DDR_DELAYLINE0_CFG_ADDR 0x34
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#define DL0_SAMPLE_VALUE_OFFSET 24
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#define DL0_SAMPLE_VALUE_MASK 0x03000000
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#define DL0_CNT_VALUE_OFFSET 16
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#define DL0_CNT_VALUE_MASK 0x00FF0000
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#define DL0_CNT_ADD_SUB_SEL_OFFSET 15
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#define DL0_CNT_ADD_SUB_SEL_MASK 0x00008000
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#define DL0_SW_CNT_SOFT_RST_OFFSET 14
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#define DL0_SW_CNT_SOFT_RST_MASK 0x00004000
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#define DL0_SW_CLK_OUT_FRC_ON_OFFSET 13
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#define DL0_SW_CLK_OUT_FRC_ON_MASK 0x00002000
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#define DL0_SW_CLK_IN_FRC_ON_OFFSET 12
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#define DL0_SW_CLK_IN_FRC_ON_MASK 0x00001000
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#define DL0_SW_CNT_CFG_DATA_OFFSET 4
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#define DL0_SW_CNT_CFG_DATA_MASK 0x00000FF0
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#define DL0_SW_CNT_CFG_PULSE_OFFSET 3
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#define DL0_SW_CNT_CFG_PULSE_MASK 0x00000008
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#define DL0_SW_EB_OFFSET 2
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#define DL0_SW_EB_MASK 0x00000004
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#define DL0_SW_CNT_PULSE_OFFSET 1
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#define DL0_SW_CNT_PULSE_MASK 0x00000002
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#define DL0_SW_OPERATION_OFFSET 0
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#define DL0_SW_OPERATION_MASK 0x00000001
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//-----------------------------------
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#define CFG_DDR_DELAYLINE1_CFG_ADDR 0x38
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#define DL1_CNT_VALUE_OFFSET 16
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#define DL1_CNT_VALUE_MASK 0x00FF0000
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#define DL1_CNT_ADD_SUB_SEL_OFFSET 15
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#define DL1_CNT_ADD_SUB_SEL_MASK 0x00008000
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#define DL1_SW_CNT_SOFT_RST_OFFSET 14
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#define DL1_SW_CNT_SOFT_RST_MASK 0x00004000
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#define DL1_SW_CLK_OUT_FRC_ON_OFFSET 13
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#define DL1_SW_CLK_OUT_FRC_ON_MASK 0x00002000
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#define DL1_SW_CLK_IN_FRC_ON_OFFSET 12
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#define DL1_SW_CLK_IN_FRC_ON_MASK 0x00001000
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#define DL1_SW_CNT_CFG_DATA_OFFSET 4
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#define DL1_SW_CNT_CFG_DATA_MASK 0x00000FF0
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#define DL1_SW_CNT_CFG_PULSE_OFFSET 3
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#define DL1_SW_CNT_CFG_PULSE_MASK 0x00000008
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#define DL1_SW_EB_OFFSET 2
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#define DL1_SW_EB_MASK 0x00000004
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#define DL1_SW_CNT_PULSE_OFFSET 1
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#define DL1_SW_CNT_PULSE_MASK 0x00000002
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#define DL1_SW_OPERATION_OFFSET 0
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#define DL1_SW_OPERATION_MASK 0x00000001
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//-----------------------------------
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#define CFG_DDR_DELAYLINE2_CFG_ADDR 0x3C
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#define DL2_CNT_VALUE_OFFSET 16
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#define DL2_CNT_VALUE_MASK 0x00FF0000
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#define DL2_CNT_ADD_SUB_SEL_OFFSET 15
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#define DL2_CNT_ADD_SUB_SEL_MASK 0x00008000
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#define DL2_SW_CNT_SOFT_RST_OFFSET 14
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#define DL2_SW_CNT_SOFT_RST_MASK 0x00004000
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#define DL2_SW_CLK_OUT_FRC_ON_OFFSET 13
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#define DL2_SW_CLK_OUT_FRC_ON_MASK 0x00002000
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#define DL2_SW_CLK_IN_FRC_ON_OFFSET 12
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#define DL2_SW_CLK_IN_FRC_ON_MASK 0x00001000
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#define DL2_SW_CNT_CFG_DATA_OFFSET 4
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#define DL2_SW_CNT_CFG_DATA_MASK 0x00000FF0
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#define DL2_SW_CNT_CFG_PULSE_OFFSET 3
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#define DL2_SW_CNT_CFG_PULSE_MASK 0x00000008
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#define DL2_SW_EB_OFFSET 2
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#define DL2_SW_EB_MASK 0x00000004
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#define DL2_SW_CNT_PULSE_OFFSET 1
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#define DL2_SW_CNT_PULSE_MASK 0x00000002
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#define DL2_SW_OPERATION_OFFSET 0
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#define DL2_SW_OPERATION_MASK 0x00000001
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//-----------------------------------
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#define CFG_DDR_RXTX_RAM_CFG_ADDR 0x40
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#define RXTX_RAM1_CLK_FRC_ON_OFFSET 1
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#define RXTX_RAM1_CLK_FRC_ON_MASK 0x00000002
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#define RXTX_RAM0_CLK_FRC_ON_OFFSET 0
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#define RXTX_RAM0_CLK_FRC_ON_MASK 0x00000001
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//-----------------------------------
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#define CFG_DDR_DBG_BUS0_ADDR 0xC0
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#define DDR_DBG_BUS0_OFFSET 0
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#define DDR_DBG_BUS0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DDR_DBG_BUS1_ADDR 0xC4
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#define DDR_DBG_BUS1_OFFSET 0
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#define DDR_DBG_BUS1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DDR_CHN_HUB_ST_ADDR 0xD0
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#define CHN_ID_OFFSET 0
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#define CHN_ID_MASK 0x0000000F
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//-----------------------------------
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#define CFG_DDR_DELAYLINE_DEMO_ST_ADDR 0xD4
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#define DL0_DBG_BUS_OFFSET 0
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#define DL0_DBG_BUS_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DDR_DELAYLINE_ST_ADDR 0xD8
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#define DL_DBG_BUS_OFFSET 0
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#define DL_DBG_BUS_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DDR_MEM_FIFO_ST_ADDR 0xE4
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#define MEM_FIFO1_DATA_NUM_OFFSET 19
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#define MEM_FIFO1_DATA_NUM_MASK 0x03F80000
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#define MEM_FIFO1_PRE_FULL_OFFSET 18
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#define MEM_FIFO1_PRE_FULL_MASK 0x00040000
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#define MEM_FIFO1_FULL_OFFSET 17
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#define MEM_FIFO1_FULL_MASK 0x00020000
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#define MEM_FIFO1_EMP_OFFSET 16
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#define MEM_FIFO1_EMP_MASK 0x00010000
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#define MEM_FIFO0_DATA_NUM_OFFSET 3
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#define MEM_FIFO0_DATA_NUM_MASK 0x000003F8
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#define MEM_FIFO0_PRE_FULL_OFFSET 2
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#define MEM_FIFO0_PRE_FULL_MASK 0x00000004
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#define MEM_FIFO0_FULL_OFFSET 1
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#define MEM_FIFO0_FULL_MASK 0x00000002
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#define MEM_FIFO0_EMP_OFFSET 0
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#define MEM_FIFO0_EMP_MASK 0x00000001
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//-----------------------------------
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#define CFG_DDR_CMD_FIFO_ST_ADDR 0xE8
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#define CMD_FIFO1_DATA_NUM_OFFSET 18
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#define CMD_FIFO1_DATA_NUM_MASK 0x003C0000
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#define CMD_FIFO1_FULL_OFFSET 17
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#define CMD_FIFO1_FULL_MASK 0x00020000
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#define CMD_FIFO1_EMP_OFFSET 16
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#define CMD_FIFO1_EMP_MASK 0x00010000
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#define CMD_FIFO0_DATA_NUM_OFFSET 2
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#define CMD_FIFO0_DATA_NUM_MASK 0x0000003C
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#define CMD_FIFO0_FULL_OFFSET 1
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#define CMD_FIFO0_FULL_MASK 0x00000002
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#define CMD_FIFO0_EMP_OFFSET 0
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#define CMD_FIFO0_EMP_MASK 0x00000001
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//-----------------------------------
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#define CFG_DDR_INT_RAW_ADDR 0xF0
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#define DDR_TRAINING_DEMO_DONE_INT_RAW_OFFSET 19
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#define DDR_TRAINING_DEMO_DONE_INT_RAW_MASK 0x00080000
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#define DDR_TRAINING_MONITIOR_FAIL_INT_RAW_OFFSET 18
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#define DDR_TRAINING_MONITIOR_FAIL_INT_RAW_MASK 0x00040000
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#define DDR_TRAINING_DONE_INT_RAW_OFFSET 17
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#define DDR_TRAINING_DONE_INT_RAW_MASK 0x00020000
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#define DDR_SW_CHN_INT_RAW_OFFSET 16
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#define DDR_SW_CHN_INT_RAW_MASK 0x00010000
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#define DDR_CHN8_INT_RAW_OFFSET 8
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#define DDR_CHN8_INT_RAW_MASK 0x00000100
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#define DDR_CHN7_INT_RAW_OFFSET 7
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#define DDR_CHN7_INT_RAW_MASK 0x00000080
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#define DDR_CHN6_INT_RAW_OFFSET 6
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#define DDR_CHN6_INT_RAW_MASK 0x00000040
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#define DDR_CHN5_INT_RAW_OFFSET 5
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#define DDR_CHN5_INT_RAW_MASK 0x00000020
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#define DDR_CHN4_INT_RAW_OFFSET 4
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#define DDR_CHN4_INT_RAW_MASK 0x00000010
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#define DDR_CHN3_INT_RAW_OFFSET 3
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#define DDR_CHN3_INT_RAW_MASK 0x00000008
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#define DDR_CHN2_INT_RAW_OFFSET 2
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#define DDR_CHN2_INT_RAW_MASK 0x00000004
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#define DDR_CHN1_INT_RAW_OFFSET 1
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#define DDR_CHN1_INT_RAW_MASK 0x00000002
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#define DDR_CHN0_INT_RAW_OFFSET 0
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#define DDR_CHN0_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_DDR_INT_ST_ADDR 0xF4
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#define DDR_TRAINING_DEMO_DONE_INT_ST_OFFSET 19
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#define DDR_TRAINING_DEMO_DONE_INT_ST_MASK 0x00080000
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#define DDR_TRAINING_MONITIOR_FAIL_INT_ST_OFFSET 18
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#define DDR_TRAINING_MONITIOR_FAIL_INT_ST_MASK 0x00040000
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#define DDR_TRAINING_DONE_INT_ST_OFFSET 17
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#define DDR_TRAINING_DONE_INT_ST_MASK 0x00020000
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#define DDR_SW_CHN_INT_ST_OFFSET 16
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#define DDR_SW_CHN_INT_ST_MASK 0x00010000
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#define DDR_CHN8_INT_ST_OFFSET 8
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#define DDR_CHN8_INT_ST_MASK 0x00000100
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#define DDR_CHN7_INT_ST_OFFSET 7
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#define DDR_CHN7_INT_ST_MASK 0x00000080
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#define DDR_CHN6_INT_ST_OFFSET 6
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#define DDR_CHN6_INT_ST_MASK 0x00000040
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#define DDR_CHN5_INT_ST_OFFSET 5
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#define DDR_CHN5_INT_ST_MASK 0x00000020
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#define DDR_CHN4_INT_ST_OFFSET 4
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#define DDR_CHN4_INT_ST_MASK 0x00000010
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#define DDR_CHN3_INT_ST_OFFSET 3
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#define DDR_CHN3_INT_ST_MASK 0x00000008
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#define DDR_CHN2_INT_ST_OFFSET 2
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#define DDR_CHN2_INT_ST_MASK 0x00000004
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#define DDR_CHN1_INT_ST_OFFSET 1
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#define DDR_CHN1_INT_ST_MASK 0x00000002
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#define DDR_CHN0_INT_ST_OFFSET 0
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#define DDR_CHN0_INT_ST_MASK 0x00000001
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//-----------------------------------
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#define CFG_DDR_INT_ENA_ADDR 0xF8
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#define DDR_TRAINING_DEMO_DONE_INT_ENA_OFFSET 19
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#define DDR_TRAINING_DEMO_DONE_INT_ENA_MASK 0x00080000
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#define DDR_TRAINING_MONITIOR_FAIL_INT_ENA_OFFSET 18
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#define DDR_TRAINING_MONITIOR_FAIL_INT_ENA_MASK 0x00040000
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#define DDR_TRAINING_DONE_INT_ENA_OFFSET 17
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#define DDR_TRAINING_DONE_INT_ENA_MASK 0x00020000
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#define DDR_SW_CHN_INT_ENA_OFFSET 16
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#define DDR_SW_CHN_INT_ENA_MASK 0x00010000
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#define DDR_CHN8_INT_ENA_OFFSET 8
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#define DDR_CHN8_INT_ENA_MASK 0x00000100
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#define DDR_CHN7_INT_ENA_OFFSET 7
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#define DDR_CHN7_INT_ENA_MASK 0x00000080
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#define DDR_CHN6_INT_ENA_OFFSET 6
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#define DDR_CHN6_INT_ENA_MASK 0x00000040
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#define DDR_CHN5_INT_ENA_OFFSET 5
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#define DDR_CHN5_INT_ENA_MASK 0x00000020
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#define DDR_CHN4_INT_ENA_OFFSET 4
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#define DDR_CHN4_INT_ENA_MASK 0x00000010
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#define DDR_CHN3_INT_ENA_OFFSET 3
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#define DDR_CHN3_INT_ENA_MASK 0x00000008
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#define DDR_CHN2_INT_ENA_OFFSET 2
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#define DDR_CHN2_INT_ENA_MASK 0x00000004
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#define DDR_CHN1_INT_ENA_OFFSET 1
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#define DDR_CHN1_INT_ENA_MASK 0x00000002
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#define DDR_CHN0_INT_ENA_OFFSET 0
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#define DDR_CHN0_INT_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_DDR_INT_CLR_ADDR 0xFC
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#define DDR_TRAINING_DEMO_DONE_INT_CLR_OFFSET 19
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#define DDR_TRAINING_DEMO_DONE_INT_CLR_MASK 0x00080000
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#define DDR_TRAINING_MONITIOR_FAIL_INT_CLR_OFFSET 18
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#define DDR_TRAINING_MONITIOR_FAIL_INT_CLR_MASK 0x00040000
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#define DDR_TRAINING_DONE_INT_CLR_OFFSET 17
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#define DDR_TRAINING_DONE_INT_CLR_MASK 0x00020000
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#define DDR_SW_CHN_INT_CLR_OFFSET 16
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#define DDR_SW_CHN_INT_CLR_MASK 0x00010000
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#define DDR_CHN8_INT_CLR_OFFSET 8
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#define DDR_CHN8_INT_CLR_MASK 0x00000100
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#define DDR_CHN7_INT_CLR_OFFSET 7
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#define DDR_CHN7_INT_CLR_MASK 0x00000080
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#define DDR_CHN6_INT_CLR_OFFSET 6
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#define DDR_CHN6_INT_CLR_MASK 0x00000040
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#define DDR_CHN5_INT_CLR_OFFSET 5
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#define DDR_CHN5_INT_CLR_MASK 0x00000020
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#define DDR_CHN4_INT_CLR_OFFSET 4
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#define DDR_CHN4_INT_CLR_MASK 0x00000010
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#define DDR_CHN3_INT_CLR_OFFSET 3
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#define DDR_CHN3_INT_CLR_MASK 0x00000008
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#define DDR_CHN2_INT_CLR_OFFSET 2
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#define DDR_CHN2_INT_CLR_MASK 0x00000004
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#define DDR_CHN1_INT_CLR_OFFSET 1
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#define DDR_CHN1_INT_CLR_MASK 0x00000002
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#define DDR_CHN0_INT_CLR_OFFSET 0
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#define DDR_CHN0_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_DDR_OPERATION_INT_MEM0_ADDR 0x100
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#define SW_MEM_WDATA0_OFFSET 0
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#define SW_MEM_WDATA0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DDR_OPERATION_INT_MEM1_ADDR 0x104
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#define CMD_OR_DATA_FIFO_OFFSET 28
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#define CMD_OR_DATA_FIFO_MASK 0x10000000
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#define SW_MEM_WDATA1_OFFSET 0
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#define SW_MEM_WDATA1_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_DDR_OPERATION_INT_MEM2_ADDR 0x108
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#define SW_MEM0_RDATA_OFFSET 0
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#define SW_MEM0_RDATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DDR_OPERATION_INT_MEM3_ADDR 0x11C
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#define SW_RD_OR_WR_OFFSET 9
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#define SW_RD_OR_WR_MASK 0x00000200
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#define SW_MEM_HANDLE_EB_OFFSET 8
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#define SW_MEM_HANDLE_EB_MASK 0x00000100
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#define SW_MEM_WR_OFFSET 3
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#define SW_MEM_WR_MASK 0x00000008
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#define SW_SWH_CLK_PHY_90_270_OFFSET 2
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#define SW_SWH_CLK_PHY_90_270_MASK 0x00000004
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#define PHY_EB_SOFT_OFFSET 1
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#define PHY_EB_SOFT_MASK 0x00000002
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#define SW_MEM_RD_OFFSET 0
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#define SW_MEM_RD_MASK 0x00000001
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//-----------------------------------
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#define CFG_DDR_OPERATION_INT_MEM4_ADDR 0x120
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#define SW_MEM1_RDATA_OFFSET 0
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#define SW_MEM1_RDATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DDR_CHN0_CFG_ADDR 0x200
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#define CHN0_PREFETCH_WORD_NUM_OFFSET 0
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#define CHN0_PREFETCH_WORD_NUM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_DDR_CHN1_CFG_ADDR 0x204
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#define CHN1_PREFETCH_WORD_NUM_OFFSET 0
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#define CHN1_PREFETCH_WORD_NUM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_DDR_CHN2_CFG_ADDR 0x208
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#define CHN2_PREFETCH_WORD_NUM_OFFSET 0
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#define CHN2_PREFETCH_WORD_NUM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_DDR_CHN3_CFG_ADDR 0x20C
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#define CHN3_PREFETCH_WORD_NUM_OFFSET 0
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#define CHN3_PREFETCH_WORD_NUM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_DDR_CHN4_CFG_ADDR 0x210
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#define CHN4_PREFETCH_WORD_NUM_OFFSET 0
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#define CHN4_PREFETCH_WORD_NUM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_DDR_CHN5_CFG_ADDR 0x214
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#define CHN5_PREFETCH_WORD_NUM_OFFSET 0
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#define CHN5_PREFETCH_WORD_NUM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_DDR_CHN6_CFG_ADDR 0x218
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#define CHN6_PREFETCH_WORD_NUM_OFFSET 0
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#define CHN6_PREFETCH_WORD_NUM_MASK 0x000000FF
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//HW module read/write macro
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#define DDR_RF_READ_REG(addr) SOC_READ_REG(DDR_RF_BASEADDR + addr)
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#define DDR_RF_WRITE_REG(addr,value) SOC_WRITE_REG(DDR_RF_BASEADDR + addr,value)
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