319 lines
9.5 KiB
C
319 lines
9.5 KiB
C
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "iot_config.h"
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#include "iot_errno_api.h"
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#include "iot_io.h"
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#include "iot_utils_api.h"
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#include "hw_phy_api.h"
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#include "hw_tonemask.h"
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#include "phy_txrx_pwr.h"
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#include "phy_bb.h"
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#include "phy_cfg.h"
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#include "phy_dfe_reg.h"
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#include "hw_reg_api.h"
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#include "phy_rxtd_reg.h"
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#include "mac_rx_descriptor_reg.h"
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#include "rx_desc_reg_api.h"
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/* get fd rms info depend on tonemask id */
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uint32_t phy_tone_msk_rms_get_by_valid_tone(uint16_t valid_tone_num,
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uint8_t *fd_rms)
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{
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uint8_t band_idx = 0;
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uint32_t ret = ERR_FAIL;
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#if IOT_DTEST_ONLY_SUPPORT == 0
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if (g_phy_ctxt.indep.tx_pwr_psd_fix_db > 0) {
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if (g_phy_cpu_share_ctxt.tx_pwr_ctl_ena) {
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*fd_rms = (uint8_t)(
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g_phy_ctxt.indep.tx_pwr_psd_fix_db -
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PHY_PWR_DIG_ATT_MAX);
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} else {
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*fd_rms = (uint8_t)(
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g_phy_ctxt.indep.tx_pwr_psd_fix_db);
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}
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return ERR_OK;
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}
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#endif
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for(band_idx = 0;
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band_idx < IOT_ARRAY_CNT(iot_plc_tonemask_rms_all); band_idx++) {
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if (iot_plc_tonemask_rms_all[band_idx].valid_tone_number ==
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valid_tone_num) {
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#if IOT_DTEST_ONLY_SUPPORT == 0
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if (g_phy_cpu_share_ctxt.tx_pwr_ctl_ena)
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#else
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if (0)
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#endif
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{
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*fd_rms = (uint8_t)(
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iot_plc_tonemask_rms_all[band_idx].fd_rms_max);
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} else {
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*fd_rms = (uint8_t)(
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iot_plc_tonemask_rms_all[band_idx].fd_rms_max -
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g_phy_ctxt.indep.tx_pwr_reduce_db);
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}
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ret = ERR_OK;
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break;
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}
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}
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#if IOT_DTEST_ONLY_SUPPORT == 0
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if (!g_phy_cpu_share_ctxt.tx_pwr_ctl_ena) {
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*fd_rms += PHY_PWR_DIG_ATT_MAX;
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}
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#endif
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return ret;
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}
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/* kunlun2 pwr control */
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const phy_fd_td_ana_full_t phy_fd_td_ana_full_tbl[] = {
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{IOT_SUPPORT_TONE_80_490, {56, 9, 7, 9, 12}, {PHY_FULL_PWR_DBUV, 125}},
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{IOT_SUPPORT_TONE_100_230, {61, 9, 7, 9, 12}, {PHY_FULL_PWR_DBUV, 122}},
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{IOT_SUPPORT_TONE_32_120, {63, 6, 7, 6, 12}, {PHY_FULL_PWR_DBUV, 121}},
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{IOT_SUPPORT_TONE_72_120, {66, 0, 7, 0, 12}, {PHY_FULL_PWR_DBUV, 117}},
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{IOT_SUPPORT_TONE_231_490, {58, 9, 7, 9, 12}, {PHY_FULL_PWR_DBUV, 125}},
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{IOT_SUPPORT_TONE_240_370, {61, 9, 7, 9, 12}, {PHY_FULL_PWR_DBUV, 122}},
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{IOT_SUPPORT_TONE_200_1000, {54, 0, 7, 0, 12}, {PHY_FULL_PWR_DBUV, 130}},
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{IOT_SUPPORT_TONE_1160_1415, {59, 0, 7, 0, 12}, {PHY_FULL_PWR_DBUV, 125}},
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{IOT_SUPPORT_TONE_200_500, {58, 3, 7, 3, 12}, {PHY_FULL_PWR_DBUV, 127}}
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};
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uint32_t phy_fd_td_ana_full_get(uint32_t band_id,
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const phy_fd_td_ana_full_t *tbl,
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uint16_t tbl_len,
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uint8_t *fd_pwr_int,
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uint8_t *fd_pwr_frac,
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uint8_t *td_pwr,
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uint8_t *ana_pwr)
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{
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for (int i = 0; i < tbl_len; i++) {
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if (tbl[i].band_id == band_id) {
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*fd_pwr_int = tbl[i].fd_td_ana_full.fd_pwr_int;
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if (phy_get_pwr_ctl_en()) {
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*fd_pwr_frac = tbl[i].fd_td_ana_full.fd_pwr_frac;
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} else {
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*fd_pwr_frac = tbl[i].fd_td_ana_full.fd_pwr_frac_lp;
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}
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*td_pwr = tbl[i].fd_td_ana_full.td_pwr;
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*ana_pwr = tbl[i].fd_td_ana_full.ana_pwr;
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return ERR_OK;
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}
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}
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return ERR_INVAL;
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}
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uint32_t phy_tx_pwr_to_fd_td_ana_value(
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uint32_t hw_rate_id,
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uint32_t band_id,
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uint8_t uint_dbuv,
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uint8_t *fd_pwr_int,
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uint8_t *fd_pwr_frac,
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uint8_t *td_pwr,
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uint8_t *ana_pwr)
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{
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uint32_t ret = ERR_OK;
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uint8_t rms_delta = 0;
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/* get set delta */
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rms_delta = PHY_FULL_PWR_DBUV - uint_dbuv;
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ret = phy_fd_td_ana_full_get(band_id,
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phy_fd_td_ana_full_tbl,
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IOT_ARRAY_CNT(phy_fd_td_ana_full_tbl),
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fd_pwr_int,
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fd_pwr_frac,
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td_pwr,
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ana_pwr);
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if (ret != ERR_OK) {
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iot_printf("phy fd_td_ana full power para get fail\n");
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return ret;
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}
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#if HW_PLATFORM == HW_PLATFORM_FPGA
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/* without analog PA */
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*fd_pwr_int = *fd_pwr_int - rms_delta;
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*ana_pwr = 0;
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#elif HW_PLATFORM == HW_PLATFORM_SILICON
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/* TD: -12/12 ,ana: -10.5/13.5 */
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if (rms_delta < PHY_PWR_CTRL_THRESHHOLD) {
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/* ana 6db step*/
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*ana_pwr -= rms_delta / PHY_PWR_ANA_STEP_LEN;
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*td_pwr -= rms_delta % PHY_PWR_ANA_STEP_LEN;
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} else if (rms_delta <= 2 * PHY_PWR_CTRL_THRESHHOLD) {
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*ana_pwr = 0;
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*td_pwr -= rms_delta - PHY_PWR_CTRL_THRESHHOLD;
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} else {
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*ana_pwr = 0;
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*td_pwr = PHY_PWR_TD_MIN;
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*fd_pwr_int -= rms_delta - PHY_PWR_CTRL_THRESHHOLD;
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}
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#endif
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(void)hw_rate_id;
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return ret;
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}
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uint32_t phy_get_default_tx_pwr(uint32_t band_id,uint8_t *uint_dbuv,
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uint8_t *dlt_max)
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{
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uint32_t ret = ERR_INVAL;
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uint8_t full_dbuv, lp_dbuv;
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for (int i = 0; i < IOT_ARRAY_CNT(phy_fd_td_ana_full_tbl); i++) {
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if (phy_fd_td_ana_full_tbl[i].band_id == band_id) {
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full_dbuv = phy_fd_td_ana_full_tbl[i].psd_full.full_dbuv;
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if (!phy_get_pwr_ctl_en()) {
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lp_dbuv = phy_fd_td_ana_full_tbl[i].psd_full.lp_dbuv;
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*dlt_max = full_dbuv - lp_dbuv;
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*uint_dbuv = lp_dbuv;
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return ERR_OK;
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} else {
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*dlt_max = 0;
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*uint_dbuv = full_dbuv;
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return ERR_OK;
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}
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}
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}
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return ret;
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}
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/* war for setting sack tx power.
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* Now adjust the power of each packet to control the power of all packets
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* by configuring registers.
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* so ana/td/fd frac/fd int all config to register.
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*/
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uint32_t phy_set_common_pwr_reg(uint32_t pwr_db)
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{
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uint8_t fd_pwr_int, fd_pwr_frac, td_pwr, ana_pwr;
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uint32_t hw_band_id = phy_def_hw_band_id_get();
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uint32_t single_proto_band = phy_proto_single_band_id_get();
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phy_tx_pwr_to_fd_td_ana_value(0,
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single_proto_band,
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pwr_db,
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&fd_pwr_int,
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&fd_pwr_frac,
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&td_pwr,
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&ana_pwr);
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/* set td and ana power to register */
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phy_force_ana_td_power(true);
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phy_set_tx_pwr_td(td_pwr);
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phy_set_tx_pwr_ana(ana_pwr);
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phy_set_tx_pwr_fd_frac(fd_pwr_frac);
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phy_set_tx_pwr_fd_int(fd_pwr_int);
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/* war for fd int/frac invalid */
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phy_tx_rms_set(0, hw_band_id, fd_pwr_int, fd_pwr_frac);
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phy_tx_rms_set(1, hw_band_id, fd_pwr_int, fd_pwr_frac);
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iot_printf("[ptr_dbg] set pwr_reg power:%d, td_pwr:%d, ana_pwr:%d, "
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"fd_frac:%d, fd_int:%d\n",
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pwr_db, td_pwr, ana_pwr, fd_pwr_frac, fd_pwr_int);
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return 0;
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}
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void phy_set_sack_tx_power(uint32_t pwr_db)
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{
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(void)pwr_db;
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}
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uint32_t phy_swagc_set(bool_t en)
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{
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return ERR_OK;
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}
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void phy_tx_resp_pwr_ctl_en(
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uint8_t fd_int_en, uint8_t fd_frac_en, uint8_t td_en, uint8_t ana_en)
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{
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(void)fd_int_en;
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(void)fd_frac_en;
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(void)td_en;
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(void)ana_en;
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}
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void phy_set_tx_resp_pwr(
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uint8_t fd_int, uint8_t fd_frac, uint8_t td, uint8_t ana)
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{
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(void)fd_int;
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(void)fd_frac;
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(void)td;
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(void)ana;
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}
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uint32_t phy_info_check_entry(void *mpdu_st,
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void *fc, uint32_t role, uint8_t mt_mode_sel)
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{
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(void)mpdu_st;
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(void)role;
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/* check beacon pkt */
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frame_control_t *sg_fc = (frame_control_t *)fc;
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if(sg_fc->delimiter_type == 0) {
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if(g_phy_ctxt.indep.work_mode == PHY_MODE_TEST &&
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(mt_mode_sel == CERT_TEST_CMD_ENTER_PHY_T)) {
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phy_channel_est_request();
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}
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}
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return ERR_OK;
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}
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void phy_check_spur_cert_handle(uint16_t notch_alpha)
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{
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(void)notch_alpha;
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}
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uint32_t phy_work_mode_set(phy_work_mode_id mode)
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{
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if (mode < PHY_MODE_END) {
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g_phy_ctxt.indep.work_mode = mode;
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if (g_phy_ctxt.indep.work_mode == PHY_MODE_TEST &&
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phy_get_g_mt_mode_sel() == CERT_TEST_CMD_ENTER_PHY_LP) {
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/* notch filter clear */
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phy_anf_option_set(PHY_ANF_MODE_BYPASS,0,0,0);
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/* bypass fnf */
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phy_fnf_option_set(PHY_FNF_MODE_BYPASS, 0, 0);
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/* clear to avoid mask over for time-varying spur */
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phy_tone_mask_amp_phase_tab_load(&all_mask_amp_phase_table,
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phy_mask_id_get(), PHY_PROTO_TYPE_GET());
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iot_printf("[BB] enter cert mode!\n");
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}
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}
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return ERR_OK;
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}
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void phy_overstress_power_down(uint32_t dowm_db)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tx_power = phy_get_tx_pwr_limit(phy_proto_single_band_id_get());
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if (tx_power > dowm_db) {
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tx_power -= dowm_db;
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}
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g_phy_ctxt.indep.ovs_ctxt.ovr_pwr = max(tx_power, MIN_TX_POWER);
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phy_set_tx_pwr_limit(tx_power);
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#else
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(void)dowm_db;
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#endif
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}
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void phy_overstress_power_up()
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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/* ignore overstress power and set sw_set_power */
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phy_set_tx_pwr_limit(g_phy_ctxt.dep.sw_set_pwr);
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#endif
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}
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