kunlun/driver/src/hw2/smc.c

/**
  ******************************************************************************
  * @file    smc.c
  * @author  Aerospace C.Power
  * @version V0.0.1
  * @date    6-March-2017
*/

/* Includes ------------------------------------------------------------------*/
#include "hw_reg_api.h"
#include "ly68s32xx.h"
#include "smc_rf.h"
#include "smc.h"
#include "iot_config.h"

/* smc transmit ena */
smc_sts_type_t hal_smc_qspi_start()
{
    uint32_t tmp;
    smc_sts_type_t status = SMC_QSPI_ERROR;

    tmp = SMC_RF_READ_REG(CFG_SMC_CMD0_ADDR);
    REG_FIELD_SET(SW_SMC_ENA, tmp, 1);
    SMC_RF_WRITE_REG(CFG_SMC_CMD0_ADDR, tmp);

    /* Return function status */
    return status;
}

smc_sts_type_t hal_smc_disable()
{
    uint32_t tmp;
    smc_sts_type_t status = SMC_QSPI_OK;

    tmp = SMC_RF_READ_REG(CFG_SMC_CMD0_ADDR);
    REG_FIELD_SET(SW_SMC_ENA, tmp, 0);
    SMC_RF_WRITE_REG(CFG_SMC_CMD0_ADDR, tmp);

    tmp = SMC_RF_READ_REG(CFG_SMC_CLK0_ADDR);
    REG_FIELD_SET(CLK_SPI_SMC_ENA, tmp, 0);
    SMC_RF_WRITE_REG(CFG_SMC_CLK0_ADDR, tmp);
    /* Return function status */
    return status;
}

/* smc quad cfg */
smc_sts_type_t hal_smc_qspi_quad_cfg(uint8_t clk)
{
    uint32_t tmp;
    smc_sts_type_t status = SMC_QSPI_OK;
    tmp = SMC_RF_READ_REG(CFG_SMC_CFG0_ADDR);
    REG_FIELD_SET(SMC_SPI_QPI_MODE, tmp, 1);
    SMC_RF_WRITE_REG(CFG_SMC_CFG0_ADDR, tmp);

    tmp = SMC_RF_READ_REG(CFG_SMC_CFG0_ADDR);
    REG_FIELD_SET(SMC_CACHE_WR_MODE, tmp, 1);
    SMC_RF_WRITE_REG(CFG_SMC_CFG0_ADDR, tmp);

    tmp = SMC_RF_READ_REG(CFG_SMC_CFG0_ADDR);
    REG_FIELD_SET(SMC_CACHE_RD_MODE, tmp, 2);
    SMC_RF_WRITE_REG(CFG_SMC_CFG0_ADDR, tmp);
#if HW_PLATFORM == HW_PLATFORM_SILICON
    tmp = SMC_RF_READ_REG(CFG_SMC_CLK0_ADDR);
    REG_FIELD_SET(CLK_SPI_SMC_ENA, tmp, 1);
    REG_FIELD_SET(CLK_SPI_SMC_DIV, tmp, 0);
    SMC_RF_WRITE_REG(CFG_SMC_CLK0_ADDR, tmp);
#endif
    return status;
}

bool_t is_smc_cmd_busy()
{
    return REG_FIELD_GET(SW_SMC_ENA, SMC_RF_READ_REG(CFG_SMC_CMD0_ADDR));
}

/* smc rst en */
smc_sts_type_t hal_smc_qspi_rst_en()
{
    smc_sts_type_t status = SMC_QSPI_OK;

    /* Return function status */
    return status;
}

/* smc rst en */
smc_sts_type_t hal_smc_qspi_rst()
{
    smc_sts_type_t status = SMC_QSPI_OK;

    /* Return function status */
    return status;
}

/* si:command + address */
smc_sts_type_t hal_smc_qspi_command(smc_op_t *cmd, uint32_t timeout)
{
    smc_sts_type_t status = SMC_QSPI_OK;
    uint32_t tmp;

    /* cmd and addr */
    tmp = SMC_RF_READ_REG(CFG_SMC_CMD1_ADDR);
    REG_FIELD_SET(SW_SMC_CMD, tmp, cmd->cmd);
    SMC_RF_WRITE_REG(CFG_SMC_CMD1_ADDR, tmp);

    tmp = SMC_RF_READ_REG(CFG_SMC_CMD1_ADDR);
    REG_FIELD_SET(SW_SMC_ADDR, tmp, cmd->addr);
    SMC_RF_WRITE_REG(CFG_SMC_CMD1_ADDR, tmp);

    /* operation */
    tmp = SMC_RF_READ_REG(CFG_SMC_CMD0_ADDR);
    REG_FIELD_SET(SW_SMC_MODE, tmp, cmd->smc_mode);
    SMC_RF_WRITE_REG(CFG_SMC_CMD0_ADDR, tmp);

    /* size */
    tmp = SMC_RF_READ_REG(CFG_SMC_CMD0_ADDR);
    REG_FIELD_SET(SW_SMC_DLEN, tmp, cmd->smc_dlen);
    SMC_RF_WRITE_REG(CFG_SMC_CMD0_ADDR, tmp);

    /* qpi mode */
    tmp = SMC_RF_READ_REG(CFG_SMC_CFG0_ADDR);
    REG_FIELD_SET(SMC_SPI_QPI_MODE, tmp, cmd->qpi_mode);
    SMC_RF_WRITE_REG(CFG_SMC_CFG0_ADDR, tmp);

    /* Return function status */
    return status;
}

/* spi output:data */
smc_sts_type_t hal_smc_qspi_transmit(uint8_t *data, uint32_t len, uint8_t is_buf, uint32_t timeout)
{
    smc_sts_type_t status = SMC_QSPI_OK;
    uint8_t *smc_data_buf;

    if(is_buf)
    {
        smc_data_buf = (uint8_t *)(SMC_RF_BASEADDR - 0x200);
        /* write data to buf ram */
        while(len--)
        {
            *smc_data_buf = *data;
            data++;
            smc_data_buf++;
        }
    }

    hal_smc_qspi_start();

    return status;
}

/* spi input:data */
smc_sts_type_t hal_smc_qspi_receive(uint8_t *data, uint32_t len, uint8_t is_buf, uint32_t timeout)
{
    smc_sts_type_t status = SMC_QSPI_OK;
    uint32_t tmp = 0;
    uint8_t *smc_data_buf;
    uint8_t *rdata = data;

    while(is_smc_cmd_busy());

    if(is_buf)
    {
        smc_data_buf = (uint8_t *)(SMC_RF_BASEADDR - 0x200);
        while(len--)
        {
            *rdata = *smc_data_buf;
            rdata++;
            smc_data_buf++;
        }
    }
    else{
        tmp = SMC_RF_READ_REG(CFG_SMC_RDATA_ADDR);
        *data     = tmp & 0xff;
        *(data+1) = tmp & (0xff < 8);
        *(data+2) = tmp & (0xff < 16);
        *(data+3) = tmp & (0xff < 24);
    }

    return status;
}

void hal_smc_qspi_set_timeout(uint32_t timeout)
{

}

/* Private functions ---------------------------------------------------------*/
smc_sts_type_t smc_qspi_wait_flag_state_until_timeout(uint32_t flag, uint32_t state, uint32_t timeout)
{
    return SMC_QSPI_OK;
}

/*****************************END OF FILE***********************/