73 lines
2.2 KiB
C
Executable File
73 lines
2.2 KiB
C
Executable File
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "hw_reg_api.h"
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#include "phy_dfe_reg.h"
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#include "phy_ana.h"
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#include "phy_bb.h"
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#include "ahb.h"
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/*
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* when phy reset, must close PA in order
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* to prevent generate step signal
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*/
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void phy_reset_pre_protect()
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{
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uint32_t tmp;
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phy_ana_enlic_en(false);
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/* close PA, make HW can't control analog */
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tmp = PHY_DFE_READ_REG(CFG_BB_ANA_TX_START_CFG_ADDR);
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REG_FIELD_SET(SW_TX_START_CFG_DATA, tmp, 0x0);
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PHY_DFE_WRITE_REG(CFG_BB_ANA_TX_START_CFG_ADDR, tmp);
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}
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/*
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* in order to prevent Resets the unsigned DAC input to 0
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* 1 force tx,open dac's clk
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* 2 set dac'reg to 512
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* 3 Restore the previous configuration
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*/
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void phy_reset_post_protect()
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{
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uint32_t tmp;
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/* force phy in tx state */
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phy_txrx_ovr_set(true, 2);
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phy_ana_enlic_en(false);
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/* en analog tx */
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phy_ana_tx_set(true, true);
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phy_ana_rx_set(false, false);
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/* overwrite DAC = unsigned 512 = signed 0 */
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phy_dac_data_ovr_set(true, 512);
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phy_dac_data_ovr_set(false, 512);
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/* disable force idle */
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phy_txrx_ovr_set(false, 0);
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/*
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* make hardware can't control Analog
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* top_en_tx: 1
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* top_enlic:10
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* top_en_dac: 1
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*/
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tmp = PHY_DFE_READ_REG(CFG_BB_ANA_TX_START_CFG_ADDR);
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REG_FIELD_SET(SW_TX_START_CFG_DATA, tmp, 0x20202);
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PHY_DFE_WRITE_REG(CFG_BB_ANA_TX_START_CFG_ADDR, tmp);
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}
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