379 lines
11 KiB
C
379 lines
11 KiB
C
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "hw_reg_api.h"
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#include "chip_reg_base.h"
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#include "apb_cache_reg.h"
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#include "sram.h"
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#include "smc.h"
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#include "ahb.h"
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#include "gp_timer.h"
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#include "uart.h"
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#include "dbg_io.h"
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#include "iot_io_api.h"
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#include "os_mem_api.h"
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#include "iot_errno_api.h"
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#include "dtest_printf.h"
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#define DTEST_SMC_CASE_GET_SIZE (1 << 0)
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#define DTEST_SMC_CASE_API_RW (1 << 1)
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#define DTEST_SMC_CASE_CACHE_RW (1 << 2)
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#define DTEST_SMC_CASE_FULL_RW (1 << 3)
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/* test PSRAM size using write loopback mechanism */
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uint32_t dtest_smc_get_psram_size_test(uint8_t *size)
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{
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uint8_t i;
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uint32_t addr_test, data_test, data;
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dcase_start("get psram size test\n");
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// cache_invalidate(0, ICACHE0_SMC_RAM_BASEADDR, 32);
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cache_clear(0);
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*(volatile uint32_t *)(ICACHE0_SMC_RAM_BASEADDR) = 0x0;
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cache_flush(0, 0x00, 32);
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for (i = 0; i < 32; i++) {
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addr_test = 0x100000 * i;
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uint8_t temp = i ^ 0x55;
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data_test = (temp << 24) | (temp << 16) | (temp << 8) | temp;
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dprintf("test addr:0x%08x, data:0x%08x\n", addr_test, data_test);
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*(volatile uint32_t *)(ICACHE0_SMC_RAM_BASEADDR + addr_test) = data_test;
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cache_flush(0, addr_test, 32);
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// cache_invalidate(0, ICACHE0_SMC_RAM_BASEADDR, 32);
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cache_clear(0);
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data = *(volatile uint32_t *)(ICACHE0_SMC_RAM_BASEADDR);
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if (addr_test == 0x00) {
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if (data != data_test) {
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dprintf("addr(0x00) write and read error, psram not working\n");
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*size = 0;
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break;
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}
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} else {
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if (data == data_test) {
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dprintf("write data loopback\n");
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break;
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}
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}
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}
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if (i == 32) {
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dprintf("no matching psram size found\n");
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goto fail;
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}
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dprintf("get psram size:%d\n", i);
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dcase_success();
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return ERR_OK;
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fail:
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dcase_failed();
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return ERR_FAIL;
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}
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uint32_t dtest_smc_api_test()
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{
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int i = 0;
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uint8_t rdata[0x40] = {0};
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uint8_t wdata[0x40] = {0};
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uint8_t data_test = 0x55;
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uint32_t addr_test = 0x10000;
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dcase_start("smc api read/write test\n");
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dprintf("init test data with 0x%x\n", data_test);
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os_mem_set(wdata, data_test, sizeof(wdata));
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while(sram_qspi_is_busy() != HAL_SRAM_OK) {
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dprintf("FLASH IS Busy Now!\n");
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}
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/* spi mode */
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dprintf("use spi mode to read/write psram\n");
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sram_qspi_exit();
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while (sram_qspi_is_busy() != HAL_SRAM_OK);
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dprintf("qpi exit succeed\n");
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dprintf("spi write data\n");
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sram_qspi_write(wdata, addr_test, sizeof(wdata));
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while(sram_qspi_is_busy() != HAL_SRAM_OK);
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dprintf("spi read data\n");
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sram_qspi_read(rdata, addr_test, sizeof(rdata));
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while(sram_qspi_is_busy() != HAL_SRAM_OK);
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for (i = 0; i < sizeof(wdata); i++) {
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if (wdata[i] != rdata[i]) {
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dprintf("spi mode read data err, index:%d, wdata:%x, rdata:%x\n", i, wdata[i], rdata[i]);
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goto fail;
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}
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}
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/* qpi mode */
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data_test = 0xaa;
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dprintf("use qpi mode to read/write psram, init test data with 0x%x\n", data_test);
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os_mem_set(wdata, data_test, sizeof(wdata));
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sram_qspi_enter();
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while(sram_qspi_is_busy() != HAL_SRAM_OK);
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dprintf("qspi enter succeed\n");
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dprintf("qpi write data\n");
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sram_qspi_quad_write(wdata, addr_test, sizeof(wdata));
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while(sram_qspi_is_busy());
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dprintf("qpi read data\n");
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os_mem_set(rdata, 0x00, sizeof(rdata));
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sram_qspi_quad_read(rdata, addr_test, sizeof(rdata));
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while(sram_qspi_is_busy() != HAL_SRAM_OK);
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for (i = 0; i < sizeof(wdata); i++) {
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if (wdata[i] != rdata[i]) {
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dprintf("qpi mode read data err, index:%d, wdata:%x, rdata:%x\n", i, wdata[i], rdata[i]);
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goto fail;
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}
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}
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dcase_success();
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return ERR_OK;
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fail:
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dcase_failed();
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return ERR_FAIL;
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}
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uint32_t dtest_smc_cache_rw_test()
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{
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uint32_t i = 0, data = 0, error = 0, test_len = 0x1000, addr_test = 0x000000;
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dcase_start("smc cache read/write test\n");
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for (i = 0; i < test_len; i++) {
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*((volatile uint8_t*)(DCACHE0_SMC_RAM_BASEADDR + addr_test + i)) = i % 0xff;
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}
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cache_flush(AHB_CACHE_D0, addr_test, test_len);
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dprintf("write/read sram by icache0\n");
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cache_invalidate(AHB_CACHE_I0, addr_test, test_len);
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for (i = 0; i < test_len; i++) {
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data = *(volatile uint8_t *)(ICACHE0_SMC_RAM_BASEADDR + addr_test + i);
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if (data != (i % 0xff)) {
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dprintf("ERROR icache0 sram read: i:%d, data:%02x\n", i, data);
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error++;
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}
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}
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dprintf("write/read sram by icache1\n");
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cache_invalidate(AHB_CACHE_I1, addr_test, test_len);
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for (i = 0; i < test_len; i++) {
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data = *(volatile uint8_t *)(ICACHE1_SMC_RAM_BASEADDR + addr_test + i);
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if (data != (i % 0xff)) {
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dprintf("ERROR icache1 sram read: i:%d, data:%02x\n", i, data);
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error++;
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}
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}
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dprintf("write/read sram by icache2\n");
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cache_invalidate(AHB_CACHE_I2, addr_test, test_len);
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for (i = 0; i < test_len; i++) {
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data = *(volatile uint8_t *)(ICACHE2_SMC_RAM_BASEADDR + addr_test + i);
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if (data != (i % 0xff)) {
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dprintf("ERROR icache2 sram read: i:%d, data:%02x\n", i, data);
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error++;
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}
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}
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dprintf("write/read sram by dcache0\n");
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cache_invalidate(AHB_CACHE_D0, addr_test, test_len);
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for (i = 0; i < test_len; i++) {
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data = *(volatile uint8_t *)(DCACHE0_SMC_RAM_BASEADDR + addr_test + i);
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if (data != (i % 0xff)) {
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dprintf("ERROR dcache0 sram read: i:%d, data:%02x\n", i, data);
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error++;
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}
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}
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dprintf("write/read sram by dcache1\n");
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cache_invalidate(AHB_CACHE_D1, addr_test, test_len);
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for (i = 0; i < test_len; i++) {
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data = *(volatile uint8_t *)(DCACHE1_SMC_RAM_BASEADDR + addr_test + i);
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if (data != (i % 0xff)) {
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dprintf("ERROR dcache1 sram read: i:%d, data:%02x\n", i, data);
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error++;
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}
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}
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if (0 == error) {
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dcase_success();
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return ERR_OK;
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}else {
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dcase_failed();
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return ERR_FAIL;
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}
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}
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uint32_t dtest_smc_psram_full_rw_test(uint8_t psram_size)
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{
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uint32_t i = 0, error = 0, temp;
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uint8_t data_test = 0x55, data;
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uint32_t len_test = psram_size * 0x100000;
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uint32_t time_old = 0, time_new = 0, time_use;
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dcase_start("psram full read/write test\n");
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/* icache_wr_auto_load = 0, it can significantly speed up the reading and
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* writing of large amounts of data.
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* In this test, the cache has no other work, and almost no miss will
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* be generated, so no significant reduction in time is observed(4m - 14678us).
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*/
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temp = CACHE0_READ_REG(CFG_CACHE_CTR0_ADDR);
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REG_FIELD_SET(ICACHE_WR_AUTO_LOAD, temp, 0);
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CACHE0_WRITE_REG(CFG_CACHE_CTR0_ADDR, temp);
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time_old = gp_timer_get_current_val(0);
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dprintf("write psram, data:0x%x, len:0x%x\n", data_test, len_test);
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cache_clear(AHB_CACHE_I0);
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for (i = 0; i < len_test; i++) {
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*((volatile uint8_t*)(ICACHE0_SMC_RAM_BASEADDR + i)) = i % 0xff;
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}
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dprintf("read psram\n");
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cache_invalidate(AHB_CACHE_I0, 0x00, 0x8000);
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for (i = 0; i < len_test; i++) {
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data = *(volatile uint8_t *)(ICACHE0_SMC_RAM_BASEADDR + i);
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if (data != data_test) {
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dprintf("ERROR icache0 sram read: i:%d, data:%02x\n", i, data);
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error++;
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}
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}
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data_test = 0xaa;
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dprintf("write psram, data:0x%x, len:0x%x\n", data_test, len_test);
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cache_clear(AHB_CACHE_I0);
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for (i = 0; i < len_test; i++) {
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*((volatile uint8_t*)(ICACHE0_SMC_RAM_BASEADDR + i)) = i % 0xff;
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}
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dprintf("read psram\n");
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cache_invalidate(AHB_CACHE_I0, 0x00, 0x8000);
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for (i = 0; i < len_test; i++) {
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data = *(volatile uint8_t *)(ICACHE0_SMC_RAM_BASEADDR + i);
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if (data != data_test) {
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dprintf("ERROR icache0 sram read: i:%d, data:%02x\n", i, data);
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error++;
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}
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}
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time_new = gp_timer_get_current_val(0);
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time_use = (time_old < time_new) ? (time_new - time_old) :
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(0xffffffff - time_old + time_new);
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dprintf("full read/write complete, it takes %d us\n", time_use);
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temp = CACHE0_READ_REG(CFG_CACHE_CTR0_ADDR);
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REG_FIELD_SET(ICACHE_WR_AUTO_LOAD, temp, 1);
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CACHE0_WRITE_REG(CFG_CACHE_CTR0_ADDR, temp);
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if (0 == error) {
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dcase_success();
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return ERR_OK;
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}else {
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dcase_failed();
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return ERR_FAIL;
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}
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}
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void dtest_smc_main()
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{
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uint32_t case_group = 0, error_cnt = 0;
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uint8_t psram_size = 0;
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dbg_uart_init();
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dconfig();
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dstart();
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dversion();
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if (dtest_get_case_group(&case_group) < 0) {
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case_group = 0xffffffff;
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}
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dprintf("get case group:0x%08X\n", case_group);
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gp_timer_init();
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gp_timer_set(0, 0xffffffff, 0);
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gp_timer_start(0);
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/* reset emc */
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dprintf("reset emc\n");
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ahb_emc_disable();
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ahb_emc_enable();
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ahb_emc_reset();
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/* init psram */
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dprintf("initialize psram\n");
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sram_qspi_init();
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sram_qspi_enter();
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hal_smc_qspi_quad_cfg(0);
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/* init cache */
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dprintf("initialize all of the cache\n");
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for (uint8_t i = AHB_CACHE_I0; i < AHB_CACHE_MAX; i++) {
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cache_disable(i);
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cache_enable(i);
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cache_fill_valid_space(i);
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}
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if (case_group & DTEST_SMC_CASE_GET_SIZE) {
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if (dtest_smc_get_psram_size_test(&psram_size)) {
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error_cnt++;
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}
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}
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/* only buffer mode, register mode will be failed */
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if (case_group & DTEST_SMC_CASE_API_RW) {
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if (dtest_smc_api_test()) {
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error_cnt++;
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}
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}
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if (case_group & DTEST_SMC_CASE_CACHE_RW) {
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if (dtest_smc_cache_rw_test()) {
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error_cnt++;
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}
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}
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if (case_group & DTEST_SMC_CASE_FULL_RW) {
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if (dtest_smc_psram_full_rw_test(psram_size)) {
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error_cnt++;
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}
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}
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if (error_cnt) {
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dprintf("smc dtest failed\n");
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} else {
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dprintf("smc dtest succeed\n");
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}
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dend();
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}
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int main(void) {
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dtest_smc_main();
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return 0;
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}
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