61 lines
1.7 KiB
C
61 lines
1.7 KiB
C
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//-----------------------------------
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#define CFG_GTMR_RVER_ADDR 0x0000
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#define GTMR_RF_VER_OFFSET 0
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#define GTMR_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_US_CFG_ADDR 0x0004
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#define US_GEN_CFG_OFFSET 0
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#define US_GEN_CFG_MASK 0x000000FF
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//-----------------------------------
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#define CFG_US_TMR_CFG_ADDR 0x0008
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#define US_TMR_MODE_OFFSET 12
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#define US_TMR_MODE_MASK 0x00001000
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#define US_TMR_CFG_OFFSET 0
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#define US_TMR_CFG_MASK 0x000003FF
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//-----------------------------------
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#define CFG_MS_TMR_CFG_ADDR 0x000c
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#define MS_TMR_MODE_OFFSET 12
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#define MS_TMR_MODE_MASK 0x00001000
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#define MS_TMR_CFG_OFFSET 0
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#define MS_TMR_CFG_MASK 0x000003FF
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//-----------------------------------
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#define CFG_SEC_TMR_CFG_ADDR 0x0010
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#define SEC_TMR_MODE_OFFSET 12
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#define SEC_TMR_MODE_MASK 0x00001000
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#define SEC_TMR_CFG_OFFSET 0
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#define SEC_TMR_CFG_MASK 0x000003FF
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//-----------------------------------
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#define CFG_TMR_INT_ENA_ADDR 0x00018
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#define TMR_INT_ENA_OFFSET 0
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#define TMR_INT_ENA_MASK 0x0000003F
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//-----------------------------------
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#define CFG_TMR_INT_STS_ADDR 0x0001c
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#define TMR_INT_STS_OFFSET 0
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#define TMR_INT_STS_MASK 0x0000003F
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//-----------------------------------
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#define CFG_TMR_CNT_ENA_ADDR 0x00024
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#define TMR_CNT_ENA_OFFSET 0
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#define TMR_CNT_ENA_MASK 0x0000003F
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//-----------------------------------
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#define CFG_TMR_CNT_CLR_ADDR 0x00028
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#define TMR_CNT_CLR_OFFSET 0
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#define TMR_CNT_CLR_MASK 0x0000003F
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//-----------------------------------
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#define CFG_TMR_CNT_STS_ADDR 0x0002c
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#define TMR_CNT_STS_OFFSET 0
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#define TMR_CNT_STS_MASK 0x0000003F
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//HW module read/write macro
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#define GTMR_READ_REG(addr) SOC_READ_REG(GTMR_BASEADDR + addr)
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#define GTMR_WRITE_REG(addr,value) SOC_WRITE_REG(GTMR_BASEADDR + addr,value)
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