388 lines
13 KiB
C
388 lines
13 KiB
C
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//-----------------------------------
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#define CFG_AHB_RVER_ADDR 0x0000
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#define AHB_RF_VER_OFFSET 0
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#define AHB_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_AHB_REG0_ADDR 0x0004
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#define SNAP_SHOT_SOFT_RST_OFFSET 26
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#define SNAP_SHOT_SOFT_RST_MASK 0x04000000
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#define SW_DMA1_SOFT_RST_OFFSET 25
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#define SW_DMA1_SOFT_RST_MASK 0x02000000
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#define SW_DMA0_SOFT_RST_OFFSET 24
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#define SW_DMA0_SOFT_RST_MASK 0x01000000
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#define PHY_ANA_SOFT_RST_OFFSET 23
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#define PHY_ANA_SOFT_RST_MASK 0x00800000
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#define PHY_REG_SOFT_RST_OFFSET 22
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#define PHY_REG_SOFT_RST_MASK 0x00400000
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#define PHY_SOFT_RST_OFFSET 21
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#define PHY_SOFT_RST_MASK 0x00200000
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#define MAC_REG_SOFT_RST_OFFSET 20
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#define MAC_REG_SOFT_RST_MASK 0x00100000
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#define RV5_CORE0_SOFT_RST_P_OFFSET 16
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#define RV5_CORE0_SOFT_RST_P_MASK 0x00010000
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#define GMAC_SOFT_RST_OFFSET 5
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#define GMAC_SOFT_RST_MASK 0x00000020
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#define DCACHE_SOFT_RST_OFFSET 4
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#define DCACHE_SOFT_RST_MASK 0x00000010
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#define ICACHE_SOFT_RST_OFFSET 3
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#define ICACHE_SOFT_RST_MASK 0x00000008
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#define ADA_SOFT_RST_OFFSET 1
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#define ADA_SOFT_RST_MASK 0x00000002
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#define MAC_SOFT_RST_OFFSET 0
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#define MAC_SOFT_RST_MASK 0x00000001
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//-----------------------------------
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#define CFG_AHB_REG1_ADDR 0x0008
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#define SNAP_SHOT_EB_OFFSET 26
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#define SNAP_SHOT_EB_MASK 0x04000000
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#define SW_DMA1_EB_OFFSET 25
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#define SW_DMA1_EB_MASK 0x02000000
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#define SW_DMA0_EB_OFFSET 24
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#define SW_DMA0_EB_MASK 0x01000000
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#define PHY_EB_OFFSET 20
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#define PHY_EB_MASK 0x00100000
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#define PERI_SYS_EB_OFFSET 19
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#define PERI_SYS_EB_MASK 0x00080000
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#define AHB_SYS_ENA_OFFSET 18
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#define AHB_SYS_ENA_MASK 0x00040000
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#define RV5_CORE0_ENA_OFFSET 16
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#define RV5_CORE0_ENA_MASK 0x00010000
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#define GMAC_EB_OFFSET 5
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#define GMAC_EB_MASK 0x00000020
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#define DCACHE_EB_OFFSET 4
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#define DCACHE_EB_MASK 0x00000010
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#define ICACHE_EB_OFFSET 3
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#define ICACHE_EB_MASK 0x00000008
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#define ADA_EB_OFFSET 1
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#define ADA_EB_MASK 0x00000002
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#define MAC_EB_OFFSET 0
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#define MAC_EB_MASK 0x00000001
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//-----------------------------------
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#define CFG_AHB_CTR0_ADDR 0x000c
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#define DCACHE_HIT_ERR_OFFSET 18
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#define DCACHE_HIT_ERR_MASK 0x00040000
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#define ICACHE_HIT_ERR_OFFSET 17
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#define ICACHE_HIT_ERR_MASK 0x00020000
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#define DCACHE_MODE_OFFSET 16
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#define DCACHE_MODE_MASK 0x00010000
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#define DCACHE_FSM_ST_OFFSET 12
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#define DCACHE_FSM_ST_MASK 0x0000F000
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#define ICACHE_FSM_ST_OFFSET 8
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#define ICACHE_FSM_ST_MASK 0x00000F00
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#define DCACHE_CLEAR_DONE_OFFSET 7
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#define DCACHE_CLEAR_DONE_MASK 0x00000080
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#define ICACHE_CLEAR_DONE_OFFSET 6
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#define ICACHE_CLEAR_DONE_MASK 0x00000040
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#define DCACHE_FLUSH_DONE_OFFSET 5
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#define DCACHE_FLUSH_DONE_MASK 0x00000020
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#define ICACHE_FLUSH_DONE_OFFSET 4
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#define ICACHE_FLUSH_DONE_MASK 0x00000010
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#define DCACHE_CLEAR_ENA_OFFSET 3
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#define DCACHE_CLEAR_ENA_MASK 0x00000008
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#define ICACHE_CLEAR_ENA_OFFSET 2
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#define ICACHE_CLEAR_ENA_MASK 0x00000004
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#define DCACHE_FLUSH_ENA_OFFSET 1
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#define DCACHE_FLUSH_ENA_MASK 0x00000002
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#define ICACHE_FLUSH_ENA_OFFSET 0
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#define ICACHE_FLUSH_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_DBG_CTR_ADDR 0x0010
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#define BB_ADC_SCALE_SEL_OFFSET 8
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#define BB_ADC_SCALE_SEL_MASK 0x00000F00
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#define BB_DAC_SCALE_SEL_OFFSET 2
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#define BB_DAC_SCALE_SEL_MASK 0x0000003C
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//-----------------------------------
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#define CFG_CLK_CFG0_ADDR 0x0014
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#define CLK_SPI_INF_DIV_OFFSET 0
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#define CLK_SPI_INF_DIV_MASK 0x00000003
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//-----------------------------------
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#define CFG_GMAC_REG1_ADDR 0x0018
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#define GMAC_SBD_FLOWCTRL_OFFSET 13
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#define GMAC_SBD_FLOWCTRL_MASK 0x00002000
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#define GMAC_PTP_AUX_TS_TRIG_OFFSET 12
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#define GMAC_PTP_AUX_TS_TRIG_MASK 0x00001000
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#define GMAC_CORE_PHY_ADDR_OFFSET 8
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#define GMAC_CORE_PHY_ADDR_MASK 0x00000F00
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#define GMAC_PHY_INTF_SEL_OFFSET 0
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#define GMAC_PHY_INTF_SEL_MASK 0x00000007
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//-----------------------------------
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#define CFG_GMAC_REG2_ADDR 0x001c
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#define GMAC_PTP_TIMESTMAP_L_OFFSET 0
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#define GMAC_PTP_TIMESTMAP_L_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GMAC_REG3_ADDR 0x0020
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#define GMAC_PTP_TIMESTMAP_H_OFFSET 0
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#define GMAC_PTP_TIMESTMAP_H_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_CACHE_MON_CFG0_ADDR 0x0024
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#define ICACHE_WR_MON_ENA_OFFSET 3
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#define ICACHE_WR_MON_ENA_MASK 0x00000008
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#define DCACHE_WR_MON_ENA_OFFSET 2
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#define DCACHE_WR_MON_ENA_MASK 0x00000004
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#define DCACHE_WR_MON_FLAG_OFFSET 1
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#define DCACHE_WR_MON_FLAG_MASK 0x00000002
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#define ICACHE_WR_MON_FLAG_OFFSET 0
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#define ICACHE_WR_MON_FLAG_MASK 0x00000001
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//-----------------------------------
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#define CFG_ICACHE_MADDR_ADDR 0x0028
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#define ICACHE_WCAP_ADDR_OFFSET 0
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#define ICACHE_WCAP_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DCACHE_MADDR_ADDR 0x002c
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#define DCACHE_WCAP_ADDR_OFFSET 0
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#define DCACHE_WCAP_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_AHB_LP_CTRL_ADDR 0x0030
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#define CHIP_DEEP_SLEEP_ENA_OFFSET 10
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#define CHIP_DEEP_SLEEP_ENA_MASK 0x00000400
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#define AHB_SYS_SLEEP_ENA_OFFSET 9
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#define AHB_SYS_SLEEP_ENA_MASK 0x00000200
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#define RV_CORE0_SLEEP_ENA_OFFSET 8
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#define RV_CORE0_SLEEP_ENA_MASK 0x00000100
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#define CHIP_DEEP_STOP_OFFSET 2
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#define CHIP_DEEP_STOP_MASK 0x00000004
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#define AHB_SYS_STOP_OFFSET 1
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#define AHB_SYS_STOP_MASK 0x00000002
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#define RV_CORE0_STOP_OFFSET 0
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#define RV_CORE0_STOP_MASK 0x00000001
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//-----------------------------------
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#define CFG_AHB_MEM_CTRL_ADDR 0x0034
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#define IIS_RAM_FORCE_ON_OFFSET 24
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#define IIS_RAM_FORCE_ON_MASK 0x01000000
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#define HRAM3_ADC_MODE_OFFSET 23
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#define HRAM3_ADC_MODE_MASK 0x00800000
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#define HRAM2_ADC_MODE_OFFSET 22
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#define HRAM2_ADC_MODE_MASK 0x00400000
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#define HRAM1_ADC_MODE_OFFSET 21
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#define HRAM1_ADC_MODE_MASK 0x00200000
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#define HRAM0_ADC_MODE_OFFSET 20
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#define HRAM0_ADC_MODE_MASK 0x00100000
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#define UART_RAM_FORCE_ON_OFFSET 19
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#define UART_RAM_FORCE_ON_MASK 0x00080000
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#define GMAC_RX_BUF_FORCE_ON_OFFSET 18
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#define GMAC_RX_BUF_FORCE_ON_MASK 0x00040000
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#define GMAC_TX_BUF_FORCE_ON_OFFSET 17
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#define GMAC_TX_BUF_FORCE_ON_MASK 0x00020000
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#define EMC_BUF_FORCE_ON_OFFSET 16
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#define EMC_BUF_FORCE_ON_MASK 0x00010000
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#define DCACHE_DMEM3_FORCE_ON_OFFSET 15
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#define DCACHE_DMEM3_FORCE_ON_MASK 0x00008000
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#define DCACHE_DMEM2_FORCE_ON_OFFSET 14
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#define DCACHE_DMEM2_FORCE_ON_MASK 0x00004000
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#define DCACHE_DMEM1_FORCE_ON_OFFSET 13
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#define DCACHE_DMEM1_FORCE_ON_MASK 0x00002000
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#define DCACHE_DMEM0_FORCE_ON_OFFSET 12
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#define DCACHE_DMEM0_FORCE_ON_MASK 0x00001000
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#define DCACHE_TMEM1_FORCE_ON_OFFSET 11
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#define DCACHE_TMEM1_FORCE_ON_MASK 0x00000800
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#define DCACHE_TMEM0_FORCE_ON_OFFSET 10
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#define DCACHE_TMEM0_FORCE_ON_MASK 0x00000400
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#define ICACHE_DMEM1_FORCE_ON_OFFSET 9
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#define ICACHE_DMEM1_FORCE_ON_MASK 0x00000200
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#define ICACHE_DMEM0_FORCE_ON_OFFSET 8
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#define ICACHE_DMEM0_FORCE_ON_MASK 0x00000100
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#define ICACHE_TMEM_FORCE_ON_OFFSET 7
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#define ICACHE_TMEM_FORCE_ON_MASK 0x00000080
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#define HROM1_FORCE_ON_OFFSET 6
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#define HROM1_FORCE_ON_MASK 0x00000040
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#define HROM0_FORCE_ON_OFFSET 5
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#define HROM0_FORCE_ON_MASK 0x00000020
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#define SEC_RAM_FORCE_ON_OFFSET 4
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#define SEC_RAM_FORCE_ON_MASK 0x00000010
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#define HRAM3_FORCE_ON_OFFSET 3
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#define HRAM3_FORCE_ON_MASK 0x00000008
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#define HRAM2_FORCE_ON_OFFSET 2
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#define HRAM2_FORCE_ON_MASK 0x00000004
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#define HRAM1_FORCE_ON_OFFSET 1
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#define HRAM1_FORCE_ON_MASK 0x00000002
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#define HRAM0_FORCE_ON_OFFSET 0
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#define HRAM0_FORCE_ON_MASK 0x00000001
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//-----------------------------------
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#define CFG_IC_MON_SADDR_ADDR 0x0038
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#define ICACHE_MON_SADDR_OFFSET 0
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#define ICACHE_MON_SADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_IC_MON_EADDR_ADDR 0x003c
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#define ICACHE_MON_EADDR_OFFSET 0
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#define ICACHE_MON_EADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DC_MON_SADDR_ADDR 0x0040
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#define DCACHE_MON_SADDR_OFFSET 0
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#define DCACHE_MON_SADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DC_MON_EADDR_ADDR 0x0044
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#define DCACHE_MON_EADDR_OFFSET 0
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#define DCACHE_MON_EADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DBG_CTR1_ADDR 0x0048
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#define CHIP_DBG_SIG_SEL_OFFSET 16
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#define CHIP_DBG_SIG_SEL_MASK 0x00FF0000
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#define CHIP_DBG_BUS_SEL_OFFSET 8
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#define CHIP_DBG_BUS_SEL_MASK 0x0000FF00
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#define DBG_BUS_TEST_OFFSET 0
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#define DBG_BUS_TEST_MASK 0x00000001
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//-----------------------------------
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#define CFG_CPU0_START_PC_ADDR 0x004c
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#define CORE0_START_PC_OFFSET 0
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#define CORE0_START_PC_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_RST_FLAG_ADDR 0x0050
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#define CHIP_SOFT_RST_FLAG_CLR_OFFSET 27
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#define CHIP_SOFT_RST_FLAG_CLR_MASK 0x08000000
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#define CORE1_SOFT_RST_FLAG_CLR_OFFSET 26
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#define CORE1_SOFT_RST_FLAG_CLR_MASK 0x04000000
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#define CORE0_SOFT_RST_FLAG_CLR_OFFSET 25
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#define CORE0_SOFT_RST_FLAG_CLR_MASK 0x02000000
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#define DEBUG1_IO_FULLRESET_FLAG_CLR_OFFSET 24
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#define DEBUG1_IO_FULLRESET_FLAG_CLR_MASK 0x01000000
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#define DEBUG0_IO_FULLRESET_FLAG_CLR_OFFSET 23
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#define DEBUG0_IO_FULLRESET_FLAG_CLR_MASK 0x00800000
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#define DEBUG1_IO_NDRESET_FLAG_CLR_OFFSET 22
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#define DEBUG1_IO_NDRESET_FLAG_CLR_MASK 0x00400000
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#define DEBUG0_IO_NDRESET_FLAG_CLR_OFFSET 21
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#define DEBUG0_IO_NDRESET_FLAG_CLR_MASK 0x00200000
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#define WDG1_FULLRST_FLAG_CLR_OFFSET 20
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#define WDG1_FULLRST_FLAG_CLR_MASK 0x00100000
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#define WDG0_FULLRST_FLAG_CLR_OFFSET 19
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#define WDG0_FULLRST_FLAG_CLR_MASK 0x00080000
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#define WDG1_CPURST_FLAG_CLR_OFFSET 18
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#define WDG1_CPURST_FLAG_CLR_MASK 0x00040000
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#define WDG0_CPURST_FLAG_CLR_OFFSET 17
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#define WDG0_CPURST_FLAG_CLR_MASK 0x00020000
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#define POR_RST_FLAG_CLR_OFFSET 16
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#define POR_RST_FLAG_CLR_MASK 0x00010000
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#define CHIP_SOFT_RST_FLAG_OFFSET 11
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#define CHIP_SOFT_RST_FLAG_MASK 0x00000800
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#define CORE1_SOFT_RST_FLAG_OFFSET 10
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#define CORE1_SOFT_RST_FLAG_MASK 0x00000400
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#define CORE0_SOFT_RST_FLAG_OFFSET 9
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#define CORE0_SOFT_RST_FLAG_MASK 0x00000200
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#define DEBUG1_IO_FULLRESET_FLAG_OFFSET 8
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#define DEBUG1_IO_FULLRESET_FLAG_MASK 0x00000100
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#define DEBUG0_IO_FULLRESET_FLAG_OFFSET 7
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#define DEBUG0_IO_FULLRESET_FLAG_MASK 0x00000080
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#define DEBUG1_IO_NDRESET_FLAG_OFFSET 6
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#define DEBUG1_IO_NDRESET_FLAG_MASK 0x00000040
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#define DEBUG0_IO_NDRESET_FLAG_OFFSET 5
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#define DEBUG0_IO_NDRESET_FLAG_MASK 0x00000020
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#define WDG1_FULLRST_FLAG_OFFSET 4
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#define WDG1_FULLRST_FLAG_MASK 0x00000010
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#define WDG0_FULLRST_FLAG_OFFSET 3
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#define WDG0_FULLRST_FLAG_MASK 0x00000008
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#define WDG1_CPURST_FLAG_OFFSET 2
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#define WDG1_CPURST_FLAG_MASK 0x00000004
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#define WDG0_CPURST_FLAG_OFFSET 1
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#define WDG0_CPURST_FLAG_MASK 0x00000002
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#define POR_RST_FLAG_OFFSET 0
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#define POR_RST_FLAG_MASK 0x00000001
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//-----------------------------------
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#define CFG_AHB_MTX_PRI_CFG_ADDR 0x0054
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#define MTX_M11_PRI_SEL_OFFSET 14
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#define MTX_M11_PRI_SEL_MASK 0x0000C000
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#define MTX_M11_PRI_RND_EN_OFFSET 13
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#define MTX_M11_PRI_RND_EN_MASK 0x00002000
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#define MTX_M11_PRI_ADJ_EN_OFFSET 12
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#define MTX_M11_PRI_ADJ_EN_MASK 0x00001000
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#define MTX_M11_PRI_RND_TH_OFFSET 8
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#define MTX_M11_PRI_RND_TH_MASK 0x00000F00
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#define MTX_M10_PRI_SEL_OFFSET 6
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#define MTX_M10_PRI_SEL_MASK 0x000000C0
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#define MTX_M10_PRI_RND_EN_OFFSET 5
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#define MTX_M10_PRI_RND_EN_MASK 0x00000020
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#define MTX_M10_PRI_ADJ_EN_OFFSET 4
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#define MTX_M10_PRI_ADJ_EN_MASK 0x00000010
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#define MTX_M10_PRI_RND_TH_OFFSET 0
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#define MTX_M10_PRI_RND_TH_MASK 0x0000000F
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//-----------------------------------
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#define CFG_AHB_MTX_ERR_ST_ADDR 0x0058
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#define MTX_M11_ERR_CLR_OFFSET 27
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#define MTX_M11_ERR_CLR_MASK 0x08000000
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#define MTX_M10_ERR_CLR_OFFSET 26
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#define MTX_M10_ERR_CLR_MASK 0x04000000
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#define MTX_M9_ERR_CLR_OFFSET 25
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#define MTX_M9_ERR_CLR_MASK 0x02000000
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#define MTX_M8_ERR_CLR_OFFSET 24
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#define MTX_M8_ERR_CLR_MASK 0x01000000
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#define MTX_M7_ERR_CLR_OFFSET 23
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#define MTX_M7_ERR_CLR_MASK 0x00800000
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#define MTX_M6_ERR_CLR_OFFSET 22
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#define MTX_M6_ERR_CLR_MASK 0x00400000
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#define MTX_M5_ERR_CLR_OFFSET 21
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#define MTX_M5_ERR_CLR_MASK 0x00200000
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#define MTX_M4_ERR_CLR_OFFSET 20
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#define MTX_M4_ERR_CLR_MASK 0x00100000
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#define MTX_M3_ERR_CLR_OFFSET 19
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#define MTX_M3_ERR_CLR_MASK 0x00080000
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#define MTX_M2_ERR_CLR_OFFSET 18
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#define MTX_M2_ERR_CLR_MASK 0x00040000
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#define MTX_M1_ERR_CLR_OFFSET 17
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#define MTX_M1_ERR_CLR_MASK 0x00020000
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#define MTX_M0_ERR_CLR_OFFSET 16
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#define MTX_M0_ERR_CLR_MASK 0x00010000
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#define MTX_M11_ERR_OFFSET 11
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#define MTX_M11_ERR_MASK 0x00000800
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#define MTX_M10_ERR_OFFSET 10
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#define MTX_M10_ERR_MASK 0x00000400
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#define MTX_M9_ERR_OFFSET 9
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#define MTX_M9_ERR_MASK 0x00000200
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#define MTX_M8_ERR_OFFSET 8
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#define MTX_M8_ERR_MASK 0x00000100
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#define MTX_M7_ERR_OFFSET 7
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#define MTX_M7_ERR_MASK 0x00000080
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#define MTX_M6_ERR_OFFSET 6
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#define MTX_M6_ERR_MASK 0x00000040
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#define MTX_M5_ERR_OFFSET 5
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#define MTX_M5_ERR_MASK 0x00000020
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#define MTX_M4_ERR_OFFSET 4
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#define MTX_M4_ERR_MASK 0x00000010
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#define MTX_M3_ERR_OFFSET 3
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#define MTX_M3_ERR_MASK 0x00000008
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#define MTX_M2_ERR_OFFSET 2
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#define MTX_M2_ERR_MASK 0x00000004
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#define MTX_M1_ERR_OFFSET 1
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#define MTX_M1_ERR_MASK 0x00000002
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#define MTX_M0_ERR_OFFSET 0
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#define MTX_M0_ERR_MASK 0x00000001
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//-----------------------------------
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#define CFG_CHIP_INIT_CFG_ADDR 0x005c
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#define CHIP_INIT_DONE_OFFSET 1
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#define CHIP_INIT_DONE_MASK 0x00000002
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#define CHIP_INIT_DONE_SET_OFFSET 0
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#define CHIP_INIT_DONE_SET_MASK 0x00000001
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//-----------------------------------
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#define CFG_MTX_HREADY_ST_ADDR 0x0060
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#define MTX_HREADY_STS_CLR_OFFSET 25
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#define MTX_HREADY_STS_CLR_MASK 0x02000000
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#define MTX_SLV_HREADY_STS_OFFSET 12
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#define MTX_SLV_HREADY_STS_MASK 0x01FFF000
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#define MTX_MST_HREADY_STS_OFFSET 0
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#define MTX_MST_HREADY_STS_MASK 0x00000FFF
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//HW module read/write macro
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#define AHB_RF_READ_REG(addr) SOC_READ_REG(AHB_RF_BASEADDR + addr)
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#define AHB_RF_WRITE_REG(addr,value) SOC_WRITE_REG(AHB_RF_BASEADDR + addr,value)
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