kunlun/inc/hw/reg/riscv/14/efuse_dig_reg.h

//-----------------------------------
#define CFG_EFUSE_INFO_ADDR 0x0000
#define APB_RF_VER_OFFSET 0
#define APB_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_EFUSE_CMD_ADDR 0x0004
#define REG_IDLE_OFFSET 24
#define REG_IDLE_MASK 0x01000000
#define REG_PGM_OFFSET 16
#define REG_PGM_MASK 0x00010000
#define REG_A_OFFSET 0
#define REG_A_MASK 0x000007FF

//-----------------------------------
#define CFG_EFUSE_BITS32_0_ADDR 0x0100
#define EFUSE_0_OFFSET 0
#define EFUSE_0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_1_ADDR 0x0104
#define EFUSE_1_OFFSET 0
#define EFUSE_1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_2_ADDR 0x0108
#define EFUSE_2_OFFSET 0
#define EFUSE_2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_3_ADDR 0x010C
#define EFUSE_3_OFFSET 0
#define EFUSE_3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_4_ADDR 0x0110
#define EFUSE_4_OFFSET 0
#define EFUSE_4_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_5_ADDR 0x0114
#define EFUSE_5_OFFSET 0
#define EFUSE_5_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_6_ADDR 0x0118
#define EFUSE_6_OFFSET 0
#define EFUSE_6_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_7_ADDR 0x011C
#define EFUSE_7_OFFSET 0
#define EFUSE_7_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_8_ADDR 0x0120
#define EFUSE_8_OFFSET 0
#define EFUSE_8_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_9_ADDR 0x0124
#define EFUSE_9_OFFSET 0
#define EFUSE_9_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_10_ADDR 0x0128
#define EFUSE_10_OFFSET 0
#define EFUSE_10_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_11_ADDR 0x012C
#define EFUSE_11_OFFSET 0
#define EFUSE_11_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_12_ADDR 0x0130
#define EFUSE_12_OFFSET 0
#define EFUSE_12_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_13_ADDR 0x0134
#define EFUSE_13_OFFSET 0
#define EFUSE_13_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_14_ADDR 0x0138
#define EFUSE_14_OFFSET 0
#define EFUSE_14_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_15_ADDR 0x013C
#define EFUSE_15_OFFSET 0
#define EFUSE_15_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_16_ADDR 0x0140
#define EFUSE_16_OFFSET 0
#define EFUSE_16_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_17_ADDR 0x0144
#define EFUSE_17_OFFSET 0
#define EFUSE_17_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_18_ADDR 0x0148
#define EFUSE_18_OFFSET 0
#define EFUSE_18_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_19_ADDR 0x014C
#define EFUSE_19_OFFSET 0
#define EFUSE_19_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_20_ADDR 0x0150
#define EFUSE_20_OFFSET 0
#define EFUSE_20_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_21_ADDR 0x0154
#define EFUSE_21_OFFSET 0
#define EFUSE_21_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_22_ADDR 0x0158
#define EFUSE_22_OFFSET 0
#define EFUSE_22_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_23_ADDR 0x015C
#define EFUSE_23_OFFSET 0
#define EFUSE_23_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_24_ADDR 0x0160
#define EFUSE_24_OFFSET 0
#define EFUSE_24_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_25_ADDR 0x0164
#define EFUSE_25_OFFSET 0
#define EFUSE_25_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_26_ADDR 0x0168
#define EFUSE_26_OFFSET 0
#define EFUSE_26_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_27_ADDR 0x016C
#define EFUSE_27_OFFSET 0
#define EFUSE_27_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_28_ADDR 0x0170
#define EFUSE_28_OFFSET 0
#define EFUSE_28_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_29_ADDR 0x0174
#define EFUSE_29_OFFSET 0
#define EFUSE_29_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_30_ADDR 0x0178
#define EFUSE_30_OFFSET 0
#define EFUSE_30_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_31_ADDR 0x017C
#define EFUSE_31_OFFSET 0
#define EFUSE_31_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_32_ADDR 0x0180
#define EFUSE_32_OFFSET 0
#define EFUSE_32_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_33_ADDR 0x0184
#define EFUSE_33_OFFSET 0
#define EFUSE_33_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_34_ADDR 0x0188
#define EFUSE_34_OFFSET 0
#define EFUSE_34_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_35_ADDR 0x018C
#define EFUSE_35_OFFSET 0
#define EFUSE_35_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_36_ADDR 0x0190
#define EFUSE_36_OFFSET 0
#define EFUSE_36_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_37_ADDR 0x0194
#define EFUSE_37_OFFSET 0
#define EFUSE_37_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_38_ADDR 0x0198
#define EFUSE_38_OFFSET 0
#define EFUSE_38_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_39_ADDR 0x019C
#define EFUSE_39_OFFSET 0
#define EFUSE_39_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_40_ADDR 0x01A0
#define EFUSE_40_OFFSET 0
#define EFUSE_40_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_41_ADDR 0x01A4
#define EFUSE_41_OFFSET 0
#define EFUSE_41_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_42_ADDR 0x01A8
#define EFUSE_42_OFFSET 0
#define EFUSE_42_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_43_ADDR 0x01AC
#define EFUSE_43_OFFSET 0
#define EFUSE_43_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_44_ADDR 0x01B0
#define EFUSE_44_OFFSET 0
#define EFUSE_44_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_45_ADDR 0x01B4
#define EFUSE_45_OFFSET 0
#define EFUSE_45_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_46_ADDR 0x01B8
#define EFUSE_46_OFFSET 0
#define EFUSE_46_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_47_ADDR 0x01BC
#define EFUSE_47_OFFSET 0
#define EFUSE_47_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_48_ADDR 0x01C0
#define EFUSE_48_OFFSET 0
#define EFUSE_48_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_49_ADDR 0x01C4
#define EFUSE_49_OFFSET 0
#define EFUSE_49_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_50_ADDR 0x01C8
#define EFUSE_50_OFFSET 0
#define EFUSE_50_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_51_ADDR 0x01CC
#define EFUSE_51_OFFSET 0
#define EFUSE_51_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_52_ADDR 0x01D0
#define EFUSE_52_OFFSET 0
#define EFUSE_52_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_53_ADDR 0x01D4
#define EFUSE_53_OFFSET 0
#define EFUSE_53_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_54_ADDR 0x01D8
#define EFUSE_54_OFFSET 0
#define EFUSE_54_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_55_ADDR 0x01DC
#define EFUSE_55_OFFSET 0
#define EFUSE_55_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_56_ADDR 0x01E0
#define EFUSE_56_OFFSET 0
#define EFUSE_56_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_57_ADDR 0x01E4
#define EFUSE_57_OFFSET 0
#define EFUSE_57_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_58_ADDR 0x01E8
#define EFUSE_58_OFFSET 0
#define EFUSE_58_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_59_ADDR 0x01EC
#define EFUSE_59_OFFSET 0
#define EFUSE_59_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_60_ADDR 0x01F0
#define EFUSE_60_OFFSET 0
#define EFUSE_60_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_61_ADDR 0x01F4
#define EFUSE_61_OFFSET 0
#define EFUSE_61_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_62_ADDR 0x01F8
#define EFUSE_62_OFFSET 0
#define EFUSE_62_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_63_ADDR 0x01FC
#define EFUSE_63_OFFSET 0
#define EFUSE_63_MASK 0xFFFFFFFF

//HW module read/write macro
#define EFUSE_DIG_READ_REG(addr) SOC_READ_REG(EFUSE_DIG_BASEADDR + addr)
#define EFUSE_DIG_WRITE_REG(addr,value) SOC_WRITE_REG(EFUSE_DIG_BASEADDR + addr,value)