492 lines
16 KiB
C
492 lines
16 KiB
C
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//-----------------------------------
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#define CFG_BB_ADA_FORMAT_CFG_ADDR 0x0000
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#define SW_SOC_ADC_SEL_OFFSET 8
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#define SW_SOC_ADC_SEL_MASK 0x00000300
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#define SW_MON_ADC_SEL_OFFSET 7
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#define SW_MON_ADC_SEL_MASK 0x00000080
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#define SW_AGC_RAW_DATA_SEL_OFFSET 6
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#define SW_AGC_RAW_DATA_SEL_MASK 0x00000040
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#define SW_SADC_DATA_FORMAT_OFFSET 5
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#define SW_SADC_DATA_FORMAT_MASK 0x00000020
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#define SW_DAC_DATA_FORMAT_OFFSET 4
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#define SW_DAC_DATA_FORMAT_MASK 0x00000010
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#define SW_ADC_DATA_FORMAT_OFFSET 3
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#define SW_ADC_DATA_FORMAT_MASK 0x00000008
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#define SW_CLK_SADC_INV_EN_OFFSET 2
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#define SW_CLK_SADC_INV_EN_MASK 0x00000004
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#define SW_CLK_DAC_INV_EN_OFFSET 1
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#define SW_CLK_DAC_INV_EN_MASK 0x00000002
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#define SW_CLK_ADC_INV_EN_OFFSET 0
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#define SW_CLK_ADC_INV_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_DC_COMP0_ADDR 0x0004
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#define SW_DC_COMP_GAIN1_OFFSET 16
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#define SW_DC_COMP_GAIN1_MASK 0x03FF0000
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#define SW_DC_COMP_GAIN0_OFFSET 0
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#define SW_DC_COMP_GAIN0_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BB_DC_COMP1_ADDR 0x0008
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#define SW_DC_COMP_GAIN3_OFFSET 16
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#define SW_DC_COMP_GAIN3_MASK 0x03FF0000
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#define SW_DC_COMP_GAIN2_OFFSET 0
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#define SW_DC_COMP_GAIN2_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BB_PPM_SETTING_ADDR 0x000C
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#define SW_TX_PPM_OFFSET 16
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#define SW_TX_PPM_MASK 0xFFFF0000
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#define SW_RX_PPM_OFFSET 0
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#define SW_RX_PPM_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BB_PPM_FIFO_SETTING_ADDR 0x0010
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#define SW_EN_RX_FREQ_PPM_OFFSET 29
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#define SW_EN_RX_FREQ_PPM_MASK 0x20000000
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#define SW_RX_PPM_FIFO_EMPTY_TH_OFFSET 24
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#define SW_RX_PPM_FIFO_EMPTY_TH_MASK 0x1F000000
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#define SW_RX_PPM_FIFO_FULL_TH_OFFSET 16
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#define SW_RX_PPM_FIFO_FULL_TH_MASK 0x001F0000
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#define SW_TX_PPM_FIFO_EMPTY_TH_OFFSET 8
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#define SW_TX_PPM_FIFO_EMPTY_TH_MASK 0x00001F00
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#define SW_TX_PPM_FIFO_FULL_TH_OFFSET 0
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#define SW_TX_PPM_FIFO_FULL_TH_MASK 0x0000001F
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//-----------------------------------
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#define CFG_BB_PPM_EST_SETTING_ADDR 0x0014
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#define SW_RO_FREQ_PPM_OFFSET 0
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#define SW_RO_FREQ_PPM_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BB_TX_CLIP_CFG_ADDR 0x0018
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#define SW_TXCLIP_EN_OFFSET 31
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#define SW_TXCLIP_EN_MASK 0x80000000
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#define SW_TXCLIP_16QAM_TH_OFFSET 20
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#define SW_TXCLIP_16QAM_TH_MASK 0x3FF00000
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#define SW_TXCLIP_QPSK_TH_OFFSET 10
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#define SW_TXCLIP_QPSK_TH_MASK 0x000FFC00
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#define SW_TXCLIP_BPSK_TH_OFFSET 0
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#define SW_TXCLIP_BPSK_TH_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BB_DEC_CIC_SETTING_ADDR 0x001C
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#define SW_RX_XR_SHIFT_EN_OFFSET 1
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#define SW_RX_XR_SHIFT_EN_MASK 0x00000002
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#define SW_RX_QR_SHIFT_EN_OFFSET 0
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#define SW_RX_QR_SHIFT_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_SW_ADJUST_GAIN_ADDR 0x0100
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#define SW_TX_PWR_SCALE_FACTOR_OFFSET 16
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#define SW_TX_PWR_SCALE_FACTOR_MASK 0x001F0000
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#define SW_TX_GAIN_LEFT_SHIFT_OFFSET 12
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#define SW_TX_GAIN_LEFT_SHIFT_MASK 0x00001000
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#define SW_TX_GAIN_SHIFT_BITS_OFFSET 8
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#define SW_TX_GAIN_SHIFT_BITS_MASK 0x00000F00
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#define SW_RX_GAIN_LEFT_SHIFT_OFFSET 4
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#define SW_RX_GAIN_LEFT_SHIFT_MASK 0x00000010
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#define SW_RX_GAIN_SHIFT_BITS_OFFSET 0
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#define SW_RX_GAIN_SHIFT_BITS_MASK 0x0000000F
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//-----------------------------------
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#define CFG_GAIN_SERIAL_CFG0_ADDR 0x0104
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#define SW_GAIN_CFG0_DATA_OFFSET 0
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#define SW_GAIN_CFG0_DATA_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GAIN_SERIAL_CFG0_START_ADDR 0x0108
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#define SW_GAIN_CFG0_START_OFFSET 0
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#define SW_GAIN_CFG0_START_MASK 0x00000001
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//-----------------------------------
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#define CFG_GAIN_SERIAL_CFG1_ADDR 0x010c
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#define SW_GAIN_CFG1_DATA_OFFSET 0
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#define SW_GAIN_CFG1_DATA_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GAIN_SERIAL_CFG1_START_ADDR 0x0110
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#define SW_GAIN_CFG1_START_OFFSET 0
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#define SW_GAIN_CFG1_START_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_STDY_RX_DLY_ADDR 0x0118
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#define SW_STDY_RX_DLY_OFFSET 0
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#define SW_STDY_RX_DLY_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_STDY_TX_DLY_ADDR 0x011c
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#define SW_STDY_TX_DLY_OFFSET 0
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#define SW_STDY_TX_DLY_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_GAIN_ADJ_TIME_ADDR 0x0120
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#define SW_GAIN_ADJ_TIME_OFFSET 0
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#define SW_GAIN_ADJ_TIME_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_AGC_SWCFG_EN_ADDR 0x0128
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#define AGC_BYPASS_MODE_OFFSET 31
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#define AGC_BYPASS_MODE_MASK 0x80000000
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#define SW_FAKE_LIC_EN_OFFSET 2
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#define SW_FAKE_LIC_EN_MASK 0x00000004
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#define SW_AR1540_EN_OFFSET 1
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#define SW_AR1540_EN_MASK 0x00000002
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#define SW_GAIN_CFG_EN_OFFSET 0
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#define SW_GAIN_CFG_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_ANA_TX_START_CFG_ADDR 0x012C
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#define SW_TX_START_CFG_DATA_OFFSET 0
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#define SW_TX_START_CFG_DATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_TX_START_CFG_MASK_ADDR 0x0130
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#define SW_TX_START_CFG_DATA_MASK_OFFSET 0
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#define SW_TX_START_CFG_DATA_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_TX_END_CFG_ADDR 0x0134
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#define SW_TX_END_CFG_DATA_OFFSET 0
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#define SW_TX_END_CFG_DATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_TX_END_CFG_MASK_ADDR 0x0138
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#define SW_TX_END_CFG_DATA_MASK_OFFSET 0
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#define SW_TX_END_CFG_DATA_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_RX_START_CFG_ADDR 0x013C
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#define SW_RX_START_CFG_DATA_OFFSET 0
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#define SW_RX_START_CFG_DATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_RX_START_CFG_MASK_ADDR 0x0140
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#define SW_RX_START_CFG_DATA_MASK_OFFSET 0
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#define SW_RX_START_CFG_DATA_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_RX_END_CFG_ADDR 0x0144
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#define SW_RX_END_CFG_DATA_OFFSET 0
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#define SW_RX_END_CFG_DATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_RX_END_CFG_MASK_ADDR 0x0148
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#define SW_RX_END_CFG_DATA_MASK_OFFSET 0
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#define SW_RX_END_CFG_DATA_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_RX_ON_CFG_ADDR 0x014C
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#define SW_RX_ON_CFG_DATA_OFFSET 0
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#define SW_RX_ON_CFG_DATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_RX_ON_CFG_MASK_ADDR 0x0150
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#define SW_RX_ON_CFG_DATA_MASK_OFFSET 0
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#define SW_RX_ON_CFG_DATA_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_REG_ADDR_0_ADDR 0x0154
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#define SW_ANA_PLL_ADDR_OFFSET 24
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#define SW_ANA_PLL_ADDR_MASK 0x3F000000
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#define SW_ANA_SADC_ADDR_OFFSET 18
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#define SW_ANA_SADC_ADDR_MASK 0x00FC0000
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#define SW_ANA_ADC_ADDR_OFFSET 12
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#define SW_ANA_ADC_ADDR_MASK 0x0003F000
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#define SW_ANA_RX1_ADDR_OFFSET 6
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#define SW_ANA_RX1_ADDR_MASK 0x00000FC0
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#define SW_ANA_RX0_ADDR_OFFSET 0
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#define SW_ANA_RX0_ADDR_MASK 0x0000003F
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//-----------------------------------
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#define CFG_BB_ANA_REG_ADDR_1_ADDR 0x0158
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#define SW_ANA_BIAS2_ADDR_OFFSET 24
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#define SW_ANA_BIAS2_ADDR_MASK 0x3F000000
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#define SW_ANA_BIAS1_ADDR_OFFSET 18
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#define SW_ANA_BIAS1_ADDR_MASK 0x00FC0000
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#define SW_ANA_BIAS0_ADDR_OFFSET 12
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#define SW_ANA_BIAS0_ADDR_MASK 0x0003F000
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#define SW_ANA_TXLGC_ADDR_OFFSET 6
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#define SW_ANA_TXLGC_ADDR_MASK 0x00000FC0
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#define SW_ANA_TXDAC_ADDR_OFFSET 0
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#define SW_ANA_TXDAC_ADDR_MASK 0x0000003F
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//-----------------------------------
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#define CFG_BB_ANA_REG_ADDR_2_ADDR 0x015C
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#define SW_ANA_TOP_ADDR_OFFSET 0
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#define SW_ANA_TOP_ADDR_MASK 0x0000003F
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//-----------------------------------
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#define CFG_BB_ANA_TX_START_EXT_CFG_ADDR 0x0160
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#define SW_TX_START_EXT_CFG_DATA_OFFSET 0
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#define SW_TX_START_EXT_CFG_DATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_TX_END_EXT_CFG_ADDR 0x0164
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#define SW_TX_END_EXT_CFG_DATA_OFFSET 0
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#define SW_TX_END_EXT_CFG_DATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_RX_START_EXT_CFG_ADDR 0x0168
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#define SW_RX_START_EXT_CFG_DATA_OFFSET 0
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#define SW_RX_START_EXT_CFG_DATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_RX_END_EXT_CFG_ADDR 0x016C
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#define SW_RX_END_EXT_CFG_DATA_OFFSET 0
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#define SW_RX_END_EXT_CFG_DATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_EXT_ADDR_CFG_ADDR 0x0170
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#define SW_TX_START_EXT_CFG_ADDR_OFFSET 24
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#define SW_TX_START_EXT_CFG_ADDR_MASK 0x3F000000
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#define SW_TX_END_EXT_CFG_ADDR_OFFSET 16
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#define SW_TX_END_EXT_CFG_ADDR_MASK 0x003F0000
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#define SW_RX_START_EXT_CFG_ADDR_OFFSET 8
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#define SW_RX_START_EXT_CFG_ADDR_MASK 0x00003F00
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#define SW_RX_END_EXT_CFG_ADDR_OFFSET 0
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#define SW_RX_END_EXT_CFG_ADDR_MASK 0x0000003F
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//-----------------------------------
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#define CFG_BB_ANA_REG_WDATA_ADDR 0x0174
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#define SW_ANA_REG_WDATA_OFFSET 0
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#define SW_ANA_REG_WDATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_REG_WDATA_MASK_ADDR 0x0178
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#define SW_ANA_REG_WDATA_MASK_OFFSET 0
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#define SW_ANA_REG_WDATA_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_REG_RDATA_ADDR 0x017C
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#define SW_ANA_REG_RDATA_OFFSET 0
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#define SW_ANA_REG_RDATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_REG_CTRL_ADDR 0x0180
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#define ANA_I2C_BUSY_OFFSET 18
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#define ANA_I2C_BUSY_MASK 0x00040000
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#define RX_I2C_BUSY_OFFSET 17
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#define RX_I2C_BUSY_MASK 0x00020000
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#define TOP_I2C_BUSY_OFFSET 16
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#define TOP_I2C_BUSY_MASK 0x00010000
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#define SW_ANA_REG_RO_DATA_OFFSET 8
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#define SW_ANA_REG_RO_DATA_MASK 0x0000FF00
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#define SW_ANA_REG_ADDR_OFFSET 2
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#define SW_ANA_REG_ADDR_MASK 0x000000FC
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#define SW_ANA_REG_WR_OFFSET 1
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#define SW_ANA_REG_WR_MASK 0x00000002
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#define SW_ANA_REG_START_OFFSET 0
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#define SW_ANA_REG_START_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_ANA_TOP_I2C_CFG_ADDR 0x0184
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#define SW_TOP_I2C_STATUS_OFFSET 24
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#define SW_TOP_I2C_STATUS_MASK 0xFF000000
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#define SW_TOP_I2C_CFG_OFFSET 0
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#define SW_TOP_I2C_CFG_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_RX_I2C_CFG_ADDR 0x0188
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#define SW_RX_I2C_STATUS_OFFSET 24
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#define SW_RX_I2C_STATUS_MASK 0xFF000000
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#define SW_RX_I2C_CFG_OFFSET 0
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#define SW_RX_I2C_CFG_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_REST_I2C_CFG_ADDR 0x018C
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#define SW_ANA_I2C_STATUS_OFFSET 24
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#define SW_ANA_I2C_STATUS_MASK 0xFF000000
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#define SW_ANA_I2C_CFG_OFFSET 0
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#define SW_ANA_I2C_CFG_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_BB_DC_BLK_STEP_ADDR 0x0300
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#define SW_DC_BLK_ALPHA_STEP3_OFFSET 16
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#define SW_DC_BLK_ALPHA_STEP3_MASK 0x00FF0000
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#define SW_DC_BLK_ALPHA_STEP2_OFFSET 8
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#define SW_DC_BLK_ALPHA_STEP2_MASK 0x0000FF00
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#define SW_DC_BLK_ALPHA_STEP1_OFFSET 0
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#define SW_DC_BLK_ALPHA_STEP1_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_DC_BLK_STAGE_DLY_ADDR 0x0304
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#define SW_DC_BLK_BYPASS_OFFSET 16
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#define SW_DC_BLK_BYPASS_MASK 0x00010000
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#define SW_DC_BLK_STAGE2_DLY_OFFSET 8
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#define SW_DC_BLK_STAGE2_DLY_MASK 0x0000FF00
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#define SW_DC_BLK_STAGE1_DLY_OFFSET 0
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#define SW_DC_BLK_STAGE1_DLY_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_DC_TH_CFG_ADDR 0x0308
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#define SW_DC_LARGE_TH_OFFSET 0
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#define SW_DC_LARGE_TH_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BB_ANF_CFG_ADDR 0x0310
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#define SW_ANF_UNLOCK_THR_SEL_OFFSET 14
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#define SW_ANF_UNLOCK_THR_SEL_MASK 0x0001C000
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#define SW_ANF_LOCK_THR_SEL_OFFSET 11
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#define SW_ANF_LOCK_THR_SEL_MASK 0x00003800
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#define SW_ANF_LAMD_SEL_OFFSET 8
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#define SW_ANF_LAMD_SEL_MASK 0x00000700
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#define SW_ANF_MIU_LOW_SEL_OFFSET 5
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#define SW_ANF_MIU_LOW_SEL_MASK 0x000000E0
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#define SW_ANF_MIU_HIGH_SEL_OFFSET 2
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#define SW_ANF_MIU_HIGH_SEL_MASK 0x0000001C
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#define SW_ANF_OPTION_OFFSET 0
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#define SW_ANF_OPTION_MASK 0x00000003
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//-----------------------------------
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#define CFG_BB_ANF_1_ALPHA_BETA_ADDR 0x0314
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#define SW_ANF_OPTION1_OFFSET 30
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#define SW_ANF_OPTION1_MASK 0xC0000000
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#define SW_ANF_BETA_SEL1_OFFSET 16
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#define SW_ANF_BETA_SEL1_MASK 0x00070000
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#define SW_ANF_ALPHA1_OFFSET 0
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#define SW_ANF_ALPHA1_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BB_ANF_2_ALPHA_BETA_ADDR 0x0318
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#define SW_ANF_OPTION2_OFFSET 30
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#define SW_ANF_OPTION2_MASK 0xC0000000
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#define SW_ANF_BETA_SEL2_OFFSET 16
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#define SW_ANF_BETA_SEL2_MASK 0x00070000
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#define SW_ANF_ALPHA2_OFFSET 0
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#define SW_ANF_ALPHA2_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BB_ANF_0_FSK_ADDR 0x0320
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#define SW_ANF_FSK_START0_OFFSET 31
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#define SW_ANF_FSK_START0_MASK 0x80000000
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#define SW_ANF_FSK_OUT0_OFFSET 0
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#define SW_ANF_FSK_OUT0_MASK 0x000FFFFF
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//-----------------------------------
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#define CFG_BB_ANF_1_FSK_ADDR 0x0324
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#define SW_ANF_FSK_START1_OFFSET 31
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#define SW_ANF_FSK_START1_MASK 0x80000000
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#define SW_ANF_FSK_OUT1_OFFSET 0
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#define SW_ANF_FSK_OUT1_MASK 0x000FFFFF
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//-----------------------------------
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#define CFG_BB_FSK_MODE_EN_ADDR 0x0328
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#define SW_FSK_RX_EN_OFFSET 0
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#define SW_FSK_RX_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_SADC_EXT_CFG_ADDR 0x032C
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#define SW_SADC_ANF_EN_OFFSET 31
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#define SW_SADC_ANF_EN_MASK 0x80000000
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#define SW_SADC_ANF_OUT_SEL_OFFSET 30
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#define SW_SADC_ANF_OUT_SEL_MASK 0x40000000
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#define SW_SADC_HIGH_THRD_OFFSET 16
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#define SW_SADC_HIGH_THRD_MASK 0x03FF0000
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#define SW_SADC_LOW_THRD_OFFSET 0
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#define SW_SADC_LOW_THRD_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BB_LOOPBACK_TEST_CFG_ADDR 0x0330
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#define SW_LOOPBACK_EN_OFFSET 31
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#define SW_LOOPBACK_EN_MASK 0x80000000
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#define LOOP_FFT_DONE_OFFSET 8
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#define LOOP_FFT_DONE_MASK 0x00000100
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#define SW_LOOP_FFT_START_OFFSET 4
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#define SW_LOOP_FFT_START_MASK 0x00000010
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#define SW_LOOP_FFT_CYCLE_OFFSET 0
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#define SW_LOOP_FFT_CYCLE_MASK 0x0000000F
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//-----------------------------------
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#define CFG_BB_TX_TONE_0_CFG_ADDR 0x0400
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#define SW_TONE_CFG_EN_OFFSET 31
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#define SW_TONE_CFG_EN_MASK 0x80000000
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#define SW_TONE_DC_OFFSET_OFFSET 20
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#define SW_TONE_DC_OFFSET_MASK 0x3FF00000
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#define SW_TONE_0_CFG_NUM_OFFSET 8
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#define SW_TONE_0_CFG_NUM_MASK 0x0003FF00
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#define SW_TONE_0_ATTEN_OFFSET 0
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#define SW_TONE_0_ATTEN_MASK 0x0000000F
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//-----------------------------------
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#define CFG_BB_TX_TONE_1_CFG_ADDR 0x0404
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#define SW_TONE_1_CFG_NUM_OFFSET 8
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#define SW_TONE_1_CFG_NUM_MASK 0x0003FF00
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#define SW_TONE_1_ATTEN_OFFSET 0
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#define SW_TONE_1_ATTEN_MASK 0x0000000F
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//-----------------------------------
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#define CFG_BB_DFE_OPTION_0_ADDR 0x0408
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#define SW_CCA_OVR_OFFSET 24
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#define SW_CCA_OVR_MASK 0x01000000
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#define SW_CCA_OVR_EN_OFFSET 23
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#define SW_CCA_OVR_EN_MASK 0x00800000
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#define SW_DAC_DATA_OVR_OFFSET 13
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#define SW_DAC_DATA_OVR_MASK 0x007FE000
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#define SW_DAC_DATA_OVR_EN_OFFSET 12
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#define SW_DAC_DATA_OVR_EN_MASK 0x00001000
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#define SW_ENLIC_C_OVR_OFFSET 10
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#define SW_ENLIC_C_OVR_MASK 0x00000C00
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#define SW_ENLIC_C_OVR_EN_OFFSET 9
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#define SW_ENLIC_C_OVR_EN_MASK 0x00000200
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#define SW_ENLIC_B_OVR_OFFSET 7
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#define SW_ENLIC_B_OVR_MASK 0x00000180
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#define SW_ENLIC_B_OVR_EN_OFFSET 6
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#define SW_ENLIC_B_OVR_EN_MASK 0x00000040
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#define SW_ENLIC_A_OVR_OFFSET 4
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#define SW_ENLIC_A_OVR_MASK 0x00000030
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#define SW_ENLIC_A_OVR_EN_OFFSET 3
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#define SW_ENLIC_A_OVR_EN_MASK 0x00000008
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#define SW_MAC_TXRX_OVR_OFFSET 1
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#define SW_MAC_TXRX_OVR_MASK 0x00000006
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#define SW_MAC_TXRX_OVR_EN_OFFSET 0
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#define SW_MAC_TXRX_OVR_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_DFE_OPTION_1_ADDR 0x040C
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#define SW_GAIN_TABLE_OVR_OFFSET 8
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#define SW_GAIN_TABLE_OVR_MASK 0x00000100
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#define SW_GAIN_TABLE_OVR_EN_OFFSET 7
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#define SW_GAIN_TABLE_OVR_EN_MASK 0x00000080
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#define SW_RX_RATE_MODE_OVR_OFFSET 4
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#define SW_RX_RATE_MODE_OVR_MASK 0x00000070
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#define SW_RX_RATE_MODE_OVR_EN_OFFSET 3
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#define SW_RX_RATE_MODE_OVR_EN_MASK 0x00000008
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#define SW_TX_RATE_MODE_OVR_OFFSET 1
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#define SW_TX_RATE_MODE_OVR_MASK 0x00000006
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#define SW_TX_RATE_MODE_OVR_EN_OFFSET 0
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#define SW_TX_RATE_MODE_OVR_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_LIC_FLAG_CFG_ADDR 0x0410
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#define LIC_OVR_STRESS_STATUS_OFFSET 31
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#define LIC_OVR_STRESS_STATUS_MASK 0x80000000
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#define SW_LIC_FLAG_HIGH_SEL_OFFSET 5
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#define SW_LIC_FLAG_HIGH_SEL_MASK 0x00000060
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#define SW_LIC_INT_LEVEL_OFFSET 4
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#define SW_LIC_INT_LEVEL_MASK 0x00000010
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#define SW_LIC_INT_EDGE_OFFSET 3
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#define SW_LIC_INT_EDGE_MASK 0x00000008
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#define SW_LIC_INT_NEG_OFFSET 2
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#define SW_LIC_INT_NEG_MASK 0x00000004
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#define SW_LIC_INT_POS_OFFSET 1
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#define SW_LIC_INT_POS_MASK 0x00000002
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#define SW_LIC_FLAG_INT_EN_OFFSET 0
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#define SW_LIC_FLAG_INT_EN_MASK 0x00000001
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|
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//-----------------------------------
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#define CFG_BB_ADC_CNT_DBG_ADDR 0x0480
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#define EOC_SADC_OFFSET 12
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#define EOC_SADC_MASK 0x00007000
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#define TIMEOUT_SADC_OFFSET 8
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#define TIMEOUT_SADC_MASK 0x00000700
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#define EOC_ADC_OFFSET 4
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#define EOC_ADC_MASK 0x00000070
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#define TIMEOUT_ADC_OFFSET 0
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#define TIMEOUT_ADC_MASK 0x00000007
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//HW module read/write macro
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#define PHY_DFE_READ_REG(addr) SOC_READ_REG(PHY_DFE_BASEADDR + addr)
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#define PHY_DFE_WRITE_REG(addr,value) SOC_WRITE_REG(PHY_DFE_BASEADDR + addr,value)
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