213 lines
6.6 KiB
C
213 lines
6.6 KiB
C
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//-----------------------------------
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#define CFG_RX_ATTEN_ADDR 0x0000
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#define RX_RATE_MODE_OFFSET 30
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#define RX_RATE_MODE_MASK 0xC0000000
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#define ATTEN_RX_PROTO_OFFSET 28
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#define ATTEN_RX_PROTO_MASK 0x30000000
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#define ATTEN_RX_ABORT_OFFSET 27
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#define ATTEN_RX_ABORT_MASK 0x08000000
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#define ATTEN_RX_BAND_SEL_OFFSET 25
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#define ATTEN_RX_BAND_SEL_MASK 0x06000000
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#define ATTEN_RX_PHASE_OFFSET 23
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#define ATTEN_RX_PHASE_MASK 0x01800000
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#define ATTEN_RX_PORT_OFFSET 21
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#define ATTEN_RX_PORT_MASK 0x00600000
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#define ATTEN_PB_NUM_OFFSET 17
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#define ATTEN_PB_NUM_MASK 0x001E0000
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#define ATTEN_RING_ID_OFFSET 14
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#define ATTEN_RING_ID_MASK 0x0001C000
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#define ATTEN_DIRECTED_OFFSET 13
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#define ATTEN_DIRECTED_MASK 0x00002000
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#define ATTEN_RX_BUF_NUM_OFFSET 9
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#define ATTEN_RX_BUF_NUM_MASK 0x00001E00
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#define ATTEN_IS_FCSERR_OFFSET 8
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#define ATTEN_IS_FCSERR_MASK 0x00000100
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#define ATTEN_IS_OVERFLOW_OFFSET 7
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#define ATTEN_IS_OVERFLOW_MASK 0x00000080
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#define ATTEN_IS_PHYERR_OFFSET 6
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#define ATTEN_IS_PHYERR_MASK 0x00000040
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#define ATTEN_ENCRYPTED_OFFSET 5
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#define ATTEN_ENCRYPTED_MASK 0x00000020
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#define ATTEN_PB_BITMAP_OFFSET 1
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#define ATTEN_PB_BITMAP_MASK 0x0000001E
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#define ATTEN_RX_MPDU_DONE_OFFSET 0
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#define ATTEN_RX_MPDU_DONE_MASK 0x00000001
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//-----------------------------------
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#define CFG_RX_MPDU_START_0_ADDR 0x0004
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#define FC0_OFFSET 0
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#define FC0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_RX_MPDU_START_1_ADDR 0x0008
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#define FC1_OFFSET 0
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#define FC1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_RX_MPDU_START_2_ADDR 0x000c
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#define FC2_OFFSET 0
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#define FC2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_RX_MPDU_START_3_ADDR 0x0010
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#define FC3_OFFSET 0
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#define FC3_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_RX_MPDU_START_4_ADDR 0x0014
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#define ESTIMATED_PPM_OFFSET 24
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#define ESTIMATED_PPM_MASK 0xFF000000
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#define ESTIMATED_DC_OFFSET 16
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#define ESTIMATED_DC_MASK 0x00FF0000
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#define AGC_GAIN_ENTRY_OFFSET 8
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#define AGC_GAIN_ENTRY_MASK 0x0000FF00
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#define ADC_POWER_OFFSET 0
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#define ADC_POWER_MASK 0x000000FF
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//-----------------------------------
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#define CFG_RX_MPDU_START_5_ADDR 0x0018
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#define MAX_SPUR_ID_OFFSET 24
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#define MAX_SPUR_ID_MASK 0xFF000000
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#define REMAINED_PHASE_FRAC_OFFSET 16
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#define REMAINED_PHASE_FRAC_MASK 0x00FF0000
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#define PREAMBLE_SYMB_FOR_DETECT_OFFSET 8
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#define PREAMBLE_SYMB_FOR_DETECT_MASK 0x0000FF00
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#define AVG_SNR_OFFSET 0
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#define AVG_SNR_MASK 0x000000FF
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//-----------------------------------
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#define CFG_RX_MPDU_START_6_ADDR 0x001c
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#define RX_RATE_MODE_OFFSET 30
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#define RX_RATE_MODE_MASK 0xC0000000
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#define AES_KEY_IDX_OFFSET 21
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#define AES_KEY_IDX_MASK 0x3FE00000
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#define RX_BAND_SEL_OFFSET 19
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#define RX_BAND_SEL_MASK 0x00180000
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#define RX_PHASE_OFFSET 17
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#define RX_PHASE_MASK 0x00060000
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#define RX_PORT_OFFSET 15
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#define RX_PORT_MASK 0x00018000
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#define RX_PROTO_OFFSET 13
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#define RX_PROTO_MASK 0x00006000
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#define HP10FC_OFFSET 12
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#define HP10FC_MASK 0x00001000
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#define RX_PB_NUM_OFFSET 9
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#define RX_PB_NUM_MASK 0x00000E00
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#define RING_ID_OFFSET 6
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#define RING_ID_MASK 0x000001C0
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#define DIRECTED_OFFSET 5
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#define DIRECTED_MASK 0x00000020
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#define START_RESV2_OFFSET 0
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#define START_RESV2_MASK 0x0000001F
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//-----------------------------------
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#define CFG_RX_MPDU_END_0_ADDR 0x0020
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#define END_RESV1_OFFSET 30
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#define END_RESV1_MASK 0xC0000000
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#define RX_ERR_FD_OVERFLOW_OFFSET 29
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#define RX_ERR_FD_OVERFLOW_MASK 0x20000000
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#define RX_ERR_FC_PARSER_TIMEOUT_OFFSET 28
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#define RX_ERR_FC_PARSER_TIMEOUT_MASK 0x10000000
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#define RX_ERR_POWER_UP_OFFSET 27
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#define RX_ERR_POWER_UP_MASK 0x08000000
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#define RX_ERR_POWER_SAT_OFFSET 26
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#define RX_ERR_POWER_SAT_MASK 0x04000000
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#define RX_ERR_POWER_DROP_OFFSET 25
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#define RX_ERR_POWER_DROP_MASK 0x02000000
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#define IS_FCSERR_OFFSET 24
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#define IS_FCSERR_MASK 0x01000000
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#define IS_OVERFLOW_OFFSET 23
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#define IS_OVERFLOW_MASK 0x00800000
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#define RX_PHYERR_ID_OFFSET 18
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#define RX_PHYERR_ID_MASK 0x007C0000
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#define RX_IS_PHYERR_OFFSET 17
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#define RX_IS_PHYERR_MASK 0x00020000
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#define ENCRYPTED_OFFSET 16
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#define ENCRYPTED_MASK 0x00010000
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#define SNR_OFFSET 8
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#define SNR_MASK 0x0000FF00
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#define PB_BITMAP_OFFSET 4
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#define PB_BITMAP_MASK 0x000000F0
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#define RX_ABNORMAL_ID_OFFSET 1
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#define RX_ABNORMAL_ID_MASK 0x0000000E
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#define RX_MPDU_DONE_OFFSET 0
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#define RX_MPDU_DONE_MASK 0x00000001
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//-----------------------------------
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#define CFG_RX_MPDU_END_1_ADDR 0x0024
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#define NTB_TIMESTAMP_OFFSET 0
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#define NTB_TIMESTAMP_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_RX_MPDU_END_2_ADDR 0x0028
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#define LOCAL_TIMESTAMP_OFFSET 0
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#define LOCAL_TIMESTAMP_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_RX_MPDU_END_3_ADDR 0x002c
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#define RX_BB_LEN_OFFSET 23
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#define RX_BB_LEN_MASK 0xFF800000
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#define RX_ABORT_OFFSET 22
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#define RX_ABORT_MASK 0x00400000
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#define DESC_RX_ZC_OFFSET_OFFSET 6
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#define DESC_RX_ZC_OFFSET_MASK 0x003FFFC0
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#define RX_NTB_TIMESTAMP_CYCLE_OFFSET 4
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#define RX_NTB_TIMESTAMP_CYCLE_MASK 0x00000030
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#define RX_BUF_NUM_OFFSET 0
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#define RX_BUF_NUM_MASK 0x0000000F
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//-----------------------------------
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#define CFG_RX_PB_START_0_ADDR 0x0030
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#define PB_START_RESV0_OFFSET 8
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#define PB_START_RESV0_MASK 0xFFFFFF00
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#define FIRST_PB_OFFSET 7
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#define FIRST_PB_MASK 0x00000080
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#define LAST_PB_OFFSET 6
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#define LAST_PB_MASK 0x00000040
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#define PB_START_RESV1_OFFSET 0
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#define PB_START_RESV1_MASK 0x0000003F
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//-----------------------------------
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#define CFG_RX_PB_START_1_ADDR 0x0034
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#define PB_START_RESV2_OFFSET 31
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#define PB_START_RESV2_MASK 0x80000000
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#define VPBF_OFFSET 30
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#define VPBF_MASK 0x40000000
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#define OPSF_OFFSET 29
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#define OPSF_MASK 0x20000000
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#define IS_MGMT_OFFSET 28
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#define IS_MGMT_MASK 0x10000000
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#define BOUNDARY_OFFSET_OFFSET 19
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#define BOUNDARY_OFFSET_MASK 0x0FF80000
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#define BOUNDARY_FLAG_OFFSET 18
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#define BOUNDARY_FLAG_MASK 0x00040000
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#define MSDU_END_OFFSET 17
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#define MSDU_END_MASK 0x00020000
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#define MSDU_START_OFFSET 16
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#define MSDU_START_MASK 0x00010000
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#define SSN_OFFSET 0
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#define SSN_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_RX_PB_END_0_ADDR 0x0038
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#define PB_END_RESV0_OFFSET 5
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#define PB_END_RESV0_MASK 0xFFFFFFE0
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#define RX_PB_CRC_ERR_OFFSET 4
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#define RX_PB_CRC_ERR_MASK 0x00000010
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#define RX_PB_DONE_OFFSET 3
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#define RX_PB_DONE_MASK 0x00000008
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#define RX_BEACON_PLD_CRC_ERR_OFFSET 2
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#define RX_BEACON_PLD_CRC_ERR_MASK 0x00000004
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#define PB_END_RESV1_OFFSET 0
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#define PB_END_RESV1_MASK 0x00000003
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//-----------------------------------
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#define CFG_RX_PB_END_1_ADDR 0x003c
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#define PB_CRC_OFFSET 0
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#define PB_CRC_MASK 0xFFFFFFFF
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//HW module read/write macro
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#define RGF_MAC_RX_DESC_READ_REG(addr) SOC_READ_REG(RGF_MAC_RX_DESC_BASEADDR + addr)
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#define RGF_MAC_RX_DESC_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_MAC_RX_DESC_BASEADDR + addr,value)
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