2078 lines
83 KiB
C
Executable File
2078 lines
83 KiB
C
Executable File
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//-----------------------------------
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#define CFG_DMA_HW_REG_RVER_ADDR 0x0
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#define DMA_HW_RF_VER_OFFSET 0
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#define DMA_HW_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DMA_HW_RESET_CFG_ADDR 0x4
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#define DMA_HW_TX_FSM_RST_OFFSET 3
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#define DMA_HW_TX_FSM_RST_MASK 0x00000008
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#define DMA_HW_TX_RST_OFFSET 2
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#define DMA_HW_TX_RST_MASK 0x00000004
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#define DMA_HW_RX_FSM_RST_OFFSET 1
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#define DMA_HW_RX_FSM_RST_MASK 0x00000002
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#define DMA_HW_RX_RST_OFFSET 0
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#define DMA_HW_RX_RST_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_CLK_CFG_ADDR 0x8
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#define DMA_HW_TX_MEM_CLK_FRC_ON_OFFSET 3
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#define DMA_HW_TX_MEM_CLK_FRC_ON_MASK 0x00000008
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#define DMA_HW_RX_MEM_CLK_FRC_ON_OFFSET 2
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#define DMA_HW_RX_MEM_CLK_FRC_ON_MASK 0x00000004
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#define DMA_HW_TX_CLK_EN_OFFSET 1
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#define DMA_HW_TX_CLK_EN_MASK 0x00000002
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#define DMA_HW_RX_CLK_EN_OFFSET 0
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#define DMA_HW_RX_CLK_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_COM_CFG_ADDR 0xC
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#define DMA_HW_RX_ENDIAN_SEL_OFFSET 5
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#define DMA_HW_RX_ENDIAN_SEL_MASK 0x00000020
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#define DMA_HW_TX_ENDIAN_SEL_OFFSET 4
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#define DMA_HW_TX_ENDIAN_SEL_MASK 0x00000010
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#define DMA_HW_TX_ARBIT_INIT_OFFSET 1
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#define DMA_HW_TX_ARBIT_INIT_MASK 0x00000002
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#define DMA_HW_RX_ARBIT_INIT_OFFSET 0
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#define DMA_HW_RX_ARBIT_INIT_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_RX_STATUS0_ADDR 0x10
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#define DMA_HW_RX_STATUS0_OFFSET 0
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#define DMA_HW_RX_STATUS0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMA_HW_RX_STATUS1_ADDR 0x14
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#define DMA_HW_RX_STATUS1_OFFSET 0
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#define DMA_HW_RX_STATUS1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMA_HW_TX_STATUS0_ADDR 0x18
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#define DMA_HW_TX_STATUS0_OFFSET 0
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#define DMA_HW_TX_STATUS0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMA_HW_TX_STATUS1_ADDR 0x1C
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#define DMA_HW_TX_STATUS1_OFFSET 0
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#define DMA_HW_TX_STATUS1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMA_HW_TX_SET_DECR_ADDR_ADDR 0x20
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#define DMA_HW_TX_SET_DECR_ADDR_OFFSET 0
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#define DMA_HW_TX_SET_DECR_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMA_HW_RX_SET_DECR_ADDR_ADDR 0x24
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#define DMA_HW_RX_SET_DECR_ADDR_OFFSET 0
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#define DMA_HW_RX_SET_DECR_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN_FIFO_ST_ADDR 0x28
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#define DMA_HW_RX_CHN_FIFO_ST_OFFSET 0
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#define DMA_HW_RX_CHN_FIFO_ST_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMA_HW_TX_CHN_FIFO_ST_ADDR 0x2C
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#define DMA_HW_TX_CHN_FIFO_ST_OFFSET 0
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#define DMA_HW_TX_CHN_FIFO_ST_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMA_HW_MEM_CFG_ADDR 0x30
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#define DMA_HW_MEM_DS_OFFSET 2
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#define DMA_HW_MEM_DS_MASK 0x00000004
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#define DMA_HW_MEM_LS_OFFSET 1
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#define DMA_HW_MEM_LS_MASK 0x00000002
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#define DMA_HW_MEM_SD_OFFSET 0
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#define DMA_HW_MEM_SD_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_RX_ALLCHN_INTR_ST_ADDR 0x34
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#define DMA_HW_RX_CHN_INT_ST_OFFSET 0
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#define DMA_HW_RX_CHN_INT_ST_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMA_HW_TX_ALLCHN_INTR_ST_ADDR 0x38
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#define DMA_HW_TX_CHN_INT_ST_OFFSET 0
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#define DMA_HW_TX_CHN_INT_ST_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN0_CFG0_ADDR 0x100
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#define CHN0_RX_LINK_ADDR_OFFSET 0
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#define CHN0_RX_LINK_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN0_CFG1_ADDR 0x104
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#define CHN0_RX_OUT_BIT_ORDER_SEL_OFFSET 23
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#define CHN0_RX_OUT_BIT_ORDER_SEL_MASK 0x00800000
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#define CHN0_RX_OUT_BYTE_ORDER_SEL_OFFSET 22
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#define CHN0_RX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
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#define CHN0_RX_IN_BIT_ORDER_SEL_OFFSET 21
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#define CHN0_RX_IN_BIT_ORDER_SEL_MASK 0x00200000
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#define CHN0_RX_IN_BYTE_ORDER_SEL_OFFSET 20
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#define CHN0_RX_IN_BYTE_ORDER_SEL_MASK 0x00100000
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#define CHN0_RX_OWNER_FLAG_ENA_OFFSET 17
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#define CHN0_RX_OWNER_FLAG_ENA_MASK 0x00020000
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#define CHN0_RX_FULL_THRS_OFFSET 5
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#define CHN0_RX_FULL_THRS_MASK 0x0001FFE0
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#define CHN0_RX_STOP_OFFSET 4
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#define CHN0_RX_STOP_MASK 0x00000010
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#define CHN0_RX_RESTART_OFFSET 3
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#define CHN0_RX_RESTART_MASK 0x00000008
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#define CHN0_RX_START_OFFSET 2
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#define CHN0_RX_START_MASK 0x00000004
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#define CHN0_RX_PRIORITY_OFFSET 0
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#define CHN0_RX_PRIORITY_MASK 0x00000003
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN0_INTR_RAW_ADDR 0x108
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#define CHN0_RX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 5
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#define CHN0_RX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000020
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#define CHN0_RX_BUFF_FULL_INT_RAW_OFFSET 4
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#define CHN0_RX_BUFF_FULL_INT_RAW_MASK 0x00000010
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#define CHN0_RX_EXCEED_THRS_INT_RAW_OFFSET 3
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#define CHN0_RX_EXCEED_THRS_INT_RAW_MASK 0x00000008
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#define CHN0_RX_EOF_INT_RAW_OFFSET 2
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#define CHN0_RX_EOF_INT_RAW_MASK 0x00000004
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#define CHN0_RX_ALL_DECR_INT_RAW_OFFSET 1
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#define CHN0_RX_ALL_DECR_INT_RAW_MASK 0x00000002
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#define CHN0_RX_CURR_DECR_INT_RAW_OFFSET 0
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#define CHN0_RX_CURR_DECR_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN0_INTR_ST_ADDR 0x10C
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#define CHN0_RX_OWNER_IS_NOT_HW_INT_ST_OFFSET 5
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#define CHN0_RX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000020
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#define CHN0_RX_BUFF_FULL_INT_ST_OFFSET 4
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#define CHN0_RX_BUFF_FULL_INT_ST_MASK 0x00000010
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#define CHN0_RX_EXCEED_THRS_INT_ST_OFFSET 3
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#define CHN0_RX_EXCEED_THRS_INT_ST_MASK 0x00000008
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#define CHN0_RX_EOF_INT_ST_OFFSET 2
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#define CHN0_RX_EOF_INT_ST_MASK 0x00000004
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#define CHN0_RX_ALL_DECR_INT_ST_OFFSET 1
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#define CHN0_RX_ALL_DECR_INT_ST_MASK 0x00000002
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#define CHN0_RX_CURR_DECR_INT_ST_OFFSET 0
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#define CHN0_RX_CURR_DECR_INT_ST_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN0_INTR_ENA_ADDR 0x110
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#define CHN0_RX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 5
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#define CHN0_RX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000020
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#define CHN0_RX_BUFF_FULL_INT_ENA_OFFSET 4
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#define CHN0_RX_BUFF_FULL_INT_ENA_MASK 0x00000010
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#define CHN0_RX_EXCEED_THRS_INT_ENA_OFFSET 3
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#define CHN0_RX_EXCEED_THRS_INT_ENA_MASK 0x00000008
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#define CHN0_RX_EOF_INT_ENA_OFFSET 2
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#define CHN0_RX_EOF_INT_ENA_MASK 0x00000004
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#define CHN0_RX_ALL_DECR_INT_ENA_OFFSET 1
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#define CHN0_RX_ALL_DECR_INT_ENA_MASK 0x00000002
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#define CHN0_RX_CURR_DECR_INT_ENA_OFFSET 0
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#define CHN0_RX_CURR_DECR_INT_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN0_INTR_CLR_ADDR 0x114
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#define CHN0_RX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 5
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#define CHN0_RX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000020
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#define CHN0_RX_BUFF_FULL_INT_CLR_OFFSET 4
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#define CHN0_RX_BUFF_FULL_INT_CLR_MASK 0x00000010
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#define CHN0_RX_EXCEED_THRS_INT_CLR_OFFSET 3
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#define CHN0_RX_EXCEED_THRS_INT_CLR_MASK 0x00000008
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#define CHN0_RX_EOF_INT_CLR_OFFSET 2
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#define CHN0_RX_EOF_INT_CLR_MASK 0x00000004
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#define CHN0_RX_ALL_DECR_INT_CLR_OFFSET 1
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#define CHN0_RX_ALL_DECR_INT_CLR_MASK 0x00000002
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#define CHN0_RX_CURR_DECR_INT_CLR_OFFSET 0
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#define CHN0_RX_CURR_DECR_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN1_CFG0_ADDR 0x120
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#define CHN1_RX_LINK_ADDR_OFFSET 0
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#define CHN1_RX_LINK_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN1_CFG1_ADDR 0x124
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#define CHN1_RX_OUT_BIT_ORDER_SEL_OFFSET 23
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#define CHN1_RX_OUT_BIT_ORDER_SEL_MASK 0x00800000
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#define CHN1_RX_OUT_BYTE_ORDER_SEL_OFFSET 22
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#define CHN1_RX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
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#define CHN1_RX_IN_BIT_ORDER_SEL_OFFSET 21
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#define CHN1_RX_IN_BIT_ORDER_SEL_MASK 0x00200000
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#define CHN1_RX_IN_BYTE_ORDER_SEL_OFFSET 20
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#define CHN1_RX_IN_BYTE_ORDER_SEL_MASK 0x00100000
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#define CHN1_RX_OWNER_FLAG_ENA_OFFSET 17
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#define CHN1_RX_OWNER_FLAG_ENA_MASK 0x00020000
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#define CHN1_RX_FULL_THRS_OFFSET 5
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#define CHN1_RX_FULL_THRS_MASK 0x0001FFE0
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#define CHN1_RX_STOP_OFFSET 4
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#define CHN1_RX_STOP_MASK 0x00000010
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#define CHN1_RX_RESTART_OFFSET 3
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#define CHN1_RX_RESTART_MASK 0x00000008
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#define CHN1_RX_START_OFFSET 2
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#define CHN1_RX_START_MASK 0x00000004
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#define CHN1_RX_PRIORITY_OFFSET 0
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#define CHN1_RX_PRIORITY_MASK 0x00000003
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN1_INTR_RAW_ADDR 0x128
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#define CHN1_RX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 5
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#define CHN1_RX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000020
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#define CHN1_RX_BUFF_FULL_INT_RAW_OFFSET 4
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#define CHN1_RX_BUFF_FULL_INT_RAW_MASK 0x00000010
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#define CHN1_RX_EXCEED_THRS_INT_RAW_OFFSET 3
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#define CHN1_RX_EXCEED_THRS_INT_RAW_MASK 0x00000008
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#define CHN1_RX_EOF_INT_RAW_OFFSET 2
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#define CHN1_RX_EOF_INT_RAW_MASK 0x00000004
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#define CHN1_RX_ALL_DECR_INT_RAW_OFFSET 1
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#define CHN1_RX_ALL_DECR_INT_RAW_MASK 0x00000002
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#define CHN1_RX_CURR_DECR_INT_RAW_OFFSET 0
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#define CHN1_RX_CURR_DECR_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN1_INTR_ST_ADDR 0x12C
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#define CHN1_RX_OWNER_IS_NOT_HW_INT_ST_OFFSET 5
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#define CHN1_RX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000020
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#define CHN1_RX_BUFF_FULL_INT_ST_OFFSET 4
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#define CHN1_RX_BUFF_FULL_INT_ST_MASK 0x00000010
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#define CHN1_RX_EXCEED_THRS_INT_ST_OFFSET 3
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#define CHN1_RX_EXCEED_THRS_INT_ST_MASK 0x00000008
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#define CHN1_RX_EOF_INT_ST_OFFSET 2
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#define CHN1_RX_EOF_INT_ST_MASK 0x00000004
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#define CHN1_RX_ALL_DECR_INT_ST_OFFSET 1
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#define CHN1_RX_ALL_DECR_INT_ST_MASK 0x00000002
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#define CHN1_RX_CURR_DECR_INT_ST_OFFSET 0
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#define CHN1_RX_CURR_DECR_INT_ST_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN1_INTR_ENA_ADDR 0x130
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#define CHN1_RX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 5
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#define CHN1_RX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000020
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#define CHN1_RX_BUFF_FULL_INT_ENA_OFFSET 4
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#define CHN1_RX_BUFF_FULL_INT_ENA_MASK 0x00000010
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#define CHN1_RX_EXCEED_THRS_INT_ENA_OFFSET 3
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#define CHN1_RX_EXCEED_THRS_INT_ENA_MASK 0x00000008
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#define CHN1_RX_EOF_INT_ENA_OFFSET 2
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#define CHN1_RX_EOF_INT_ENA_MASK 0x00000004
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#define CHN1_RX_ALL_DECR_INT_ENA_OFFSET 1
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#define CHN1_RX_ALL_DECR_INT_ENA_MASK 0x00000002
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#define CHN1_RX_CURR_DECR_INT_ENA_OFFSET 0
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#define CHN1_RX_CURR_DECR_INT_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN1_INTR_CLR_ADDR 0x134
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#define CHN1_RX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 5
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#define CHN1_RX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000020
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#define CHN1_RX_BUFF_FULL_INT_CLR_OFFSET 4
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#define CHN1_RX_BUFF_FULL_INT_CLR_MASK 0x00000010
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#define CHN1_RX_EXCEED_THRS_INT_CLR_OFFSET 3
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#define CHN1_RX_EXCEED_THRS_INT_CLR_MASK 0x00000008
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#define CHN1_RX_EOF_INT_CLR_OFFSET 2
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#define CHN1_RX_EOF_INT_CLR_MASK 0x00000004
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#define CHN1_RX_ALL_DECR_INT_CLR_OFFSET 1
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#define CHN1_RX_ALL_DECR_INT_CLR_MASK 0x00000002
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#define CHN1_RX_CURR_DECR_INT_CLR_OFFSET 0
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#define CHN1_RX_CURR_DECR_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN2_CFG0_ADDR 0x140
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#define CHN2_RX_LINK_ADDR_OFFSET 0
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#define CHN2_RX_LINK_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN2_CFG1_ADDR 0x144
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#define CHN2_RX_OUT_BIT_ORDER_SEL_OFFSET 23
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#define CHN2_RX_OUT_BIT_ORDER_SEL_MASK 0x00800000
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#define CHN2_RX_OUT_BYTE_ORDER_SEL_OFFSET 22
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#define CHN2_RX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
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#define CHN2_RX_IN_BIT_ORDER_SEL_OFFSET 21
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#define CHN2_RX_IN_BIT_ORDER_SEL_MASK 0x00200000
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#define CHN2_RX_IN_BYTE_ORDER_SEL_OFFSET 20
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#define CHN2_RX_IN_BYTE_ORDER_SEL_MASK 0x00100000
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#define CHN2_RX_OWNER_FLAG_ENA_OFFSET 17
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#define CHN2_RX_OWNER_FLAG_ENA_MASK 0x00020000
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#define CHN2_RX_FULL_THRS_OFFSET 5
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#define CHN2_RX_FULL_THRS_MASK 0x0001FFE0
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#define CHN2_RX_STOP_OFFSET 4
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#define CHN2_RX_STOP_MASK 0x00000010
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#define CHN2_RX_RESTART_OFFSET 3
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#define CHN2_RX_RESTART_MASK 0x00000008
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#define CHN2_RX_START_OFFSET 2
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#define CHN2_RX_START_MASK 0x00000004
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#define CHN2_RX_PRIORITY_OFFSET 0
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#define CHN2_RX_PRIORITY_MASK 0x00000003
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN2_INTR_RAW_ADDR 0x148
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#define CHN2_RX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 5
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#define CHN2_RX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000020
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#define CHN2_RX_BUFF_FULL_INT_RAW_OFFSET 4
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#define CHN2_RX_BUFF_FULL_INT_RAW_MASK 0x00000010
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#define CHN2_RX_EXCEED_THRS_INT_RAW_OFFSET 3
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#define CHN2_RX_EXCEED_THRS_INT_RAW_MASK 0x00000008
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#define CHN2_RX_EOF_INT_RAW_OFFSET 2
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#define CHN2_RX_EOF_INT_RAW_MASK 0x00000004
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#define CHN2_RX_ALL_DECR_INT_RAW_OFFSET 1
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#define CHN2_RX_ALL_DECR_INT_RAW_MASK 0x00000002
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#define CHN2_RX_CURR_DECR_INT_RAW_OFFSET 0
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#define CHN2_RX_CURR_DECR_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN2_INTR_ST_ADDR 0x14C
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#define CHN2_RX_OWNER_IS_NOT_HW_INT_ST_OFFSET 5
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#define CHN2_RX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000020
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#define CHN2_RX_BUFF_FULL_INT_ST_OFFSET 4
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#define CHN2_RX_BUFF_FULL_INT_ST_MASK 0x00000010
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#define CHN2_RX_EXCEED_THRS_INT_ST_OFFSET 3
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#define CHN2_RX_EXCEED_THRS_INT_ST_MASK 0x00000008
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#define CHN2_RX_EOF_INT_ST_OFFSET 2
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#define CHN2_RX_EOF_INT_ST_MASK 0x00000004
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#define CHN2_RX_ALL_DECR_INT_ST_OFFSET 1
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#define CHN2_RX_ALL_DECR_INT_ST_MASK 0x00000002
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#define CHN2_RX_CURR_DECR_INT_ST_OFFSET 0
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#define CHN2_RX_CURR_DECR_INT_ST_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_RX_CHN2_INTR_ENA_ADDR 0x150
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#define CHN2_RX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 5
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#define CHN2_RX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000020
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#define CHN2_RX_BUFF_FULL_INT_ENA_OFFSET 4
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#define CHN2_RX_BUFF_FULL_INT_ENA_MASK 0x00000010
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#define CHN2_RX_EXCEED_THRS_INT_ENA_OFFSET 3
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#define CHN2_RX_EXCEED_THRS_INT_ENA_MASK 0x00000008
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#define CHN2_RX_EOF_INT_ENA_OFFSET 2
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#define CHN2_RX_EOF_INT_ENA_MASK 0x00000004
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#define CHN2_RX_ALL_DECR_INT_ENA_OFFSET 1
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#define CHN2_RX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN2_RX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN2_RX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN2_INTR_CLR_ADDR 0x154
|
|
#define CHN2_RX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 5
|
|
#define CHN2_RX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000020
|
|
#define CHN2_RX_BUFF_FULL_INT_CLR_OFFSET 4
|
|
#define CHN2_RX_BUFF_FULL_INT_CLR_MASK 0x00000010
|
|
#define CHN2_RX_EXCEED_THRS_INT_CLR_OFFSET 3
|
|
#define CHN2_RX_EXCEED_THRS_INT_CLR_MASK 0x00000008
|
|
#define CHN2_RX_EOF_INT_CLR_OFFSET 2
|
|
#define CHN2_RX_EOF_INT_CLR_MASK 0x00000004
|
|
#define CHN2_RX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN2_RX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN2_RX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN2_RX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN3_CFG0_ADDR 0x160
|
|
#define CHN3_RX_LINK_ADDR_OFFSET 0
|
|
#define CHN3_RX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN3_CFG1_ADDR 0x164
|
|
#define CHN3_RX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN3_RX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN3_RX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN3_RX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN3_RX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN3_RX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN3_RX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN3_RX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN3_RX_OWNER_FLAG_ENA_OFFSET 17
|
|
#define CHN3_RX_OWNER_FLAG_ENA_MASK 0x00020000
|
|
#define CHN3_RX_FULL_THRS_OFFSET 5
|
|
#define CHN3_RX_FULL_THRS_MASK 0x0001FFE0
|
|
#define CHN3_RX_STOP_OFFSET 4
|
|
#define CHN3_RX_STOP_MASK 0x00000010
|
|
#define CHN3_RX_RESTART_OFFSET 3
|
|
#define CHN3_RX_RESTART_MASK 0x00000008
|
|
#define CHN3_RX_START_OFFSET 2
|
|
#define CHN3_RX_START_MASK 0x00000004
|
|
#define CHN3_RX_PRIORITY_OFFSET 0
|
|
#define CHN3_RX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN3_INTR_RAW_ADDR 0x168
|
|
#define CHN3_RX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 5
|
|
#define CHN3_RX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000020
|
|
#define CHN3_RX_BUFF_FULL_INT_RAW_OFFSET 4
|
|
#define CHN3_RX_BUFF_FULL_INT_RAW_MASK 0x00000010
|
|
#define CHN3_RX_EXCEED_THRS_INT_RAW_OFFSET 3
|
|
#define CHN3_RX_EXCEED_THRS_INT_RAW_MASK 0x00000008
|
|
#define CHN3_RX_EOF_INT_RAW_OFFSET 2
|
|
#define CHN3_RX_EOF_INT_RAW_MASK 0x00000004
|
|
#define CHN3_RX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN3_RX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN3_RX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN3_RX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN3_INTR_ST_ADDR 0x16C
|
|
#define CHN3_RX_OWNER_IS_NOT_HW_INT_ST_OFFSET 5
|
|
#define CHN3_RX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000020
|
|
#define CHN3_RX_BUFF_FULL_INT_ST_OFFSET 4
|
|
#define CHN3_RX_BUFF_FULL_INT_ST_MASK 0x00000010
|
|
#define CHN3_RX_EXCEED_THRS_INT_ST_OFFSET 3
|
|
#define CHN3_RX_EXCEED_THRS_INT_ST_MASK 0x00000008
|
|
#define CHN3_RX_EOF_INT_ST_OFFSET 2
|
|
#define CHN3_RX_EOF_INT_ST_MASK 0x00000004
|
|
#define CHN3_RX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN3_RX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN3_RX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN3_RX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN3_INTR_ENA_ADDR 0x170
|
|
#define CHN3_RX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 5
|
|
#define CHN3_RX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000020
|
|
#define CHN3_RX_BUFF_FULL_INT_ENA_OFFSET 4
|
|
#define CHN3_RX_BUFF_FULL_INT_ENA_MASK 0x00000010
|
|
#define CHN3_RX_EXCEED_THRS_INT_ENA_OFFSET 3
|
|
#define CHN3_RX_EXCEED_THRS_INT_ENA_MASK 0x00000008
|
|
#define CHN3_RX_EOF_INT_ENA_OFFSET 2
|
|
#define CHN3_RX_EOF_INT_ENA_MASK 0x00000004
|
|
#define CHN3_RX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN3_RX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN3_RX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN3_RX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN3_INTR_CLR_ADDR 0x174
|
|
#define CHN3_RX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 5
|
|
#define CHN3_RX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000020
|
|
#define CHN3_RX_BUFF_FULL_INT_CLR_OFFSET 4
|
|
#define CHN3_RX_BUFF_FULL_INT_CLR_MASK 0x00000010
|
|
#define CHN3_RX_EXCEED_THRS_INT_CLR_OFFSET 3
|
|
#define CHN3_RX_EXCEED_THRS_INT_CLR_MASK 0x00000008
|
|
#define CHN3_RX_EOF_INT_CLR_OFFSET 2
|
|
#define CHN3_RX_EOF_INT_CLR_MASK 0x00000004
|
|
#define CHN3_RX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN3_RX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN3_RX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN3_RX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN4_CFG0_ADDR 0x180
|
|
#define CHN4_RX_LINK_ADDR_OFFSET 0
|
|
#define CHN4_RX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN4_CFG1_ADDR 0x184
|
|
#define CHN4_RX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN4_RX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN4_RX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN4_RX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN4_RX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN4_RX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN4_RX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN4_RX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN4_RX_OWNER_FLAG_ENA_OFFSET 17
|
|
#define CHN4_RX_OWNER_FLAG_ENA_MASK 0x00020000
|
|
#define CHN4_RX_FULL_THRS_OFFSET 5
|
|
#define CHN4_RX_FULL_THRS_MASK 0x0001FFE0
|
|
#define CHN4_RX_STOP_OFFSET 4
|
|
#define CHN4_RX_STOP_MASK 0x00000010
|
|
#define CHN4_RX_RESTART_OFFSET 3
|
|
#define CHN4_RX_RESTART_MASK 0x00000008
|
|
#define CHN4_RX_START_OFFSET 2
|
|
#define CHN4_RX_START_MASK 0x00000004
|
|
#define CHN4_RX_PRIORITY_OFFSET 0
|
|
#define CHN4_RX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN4_INTR_RAW_ADDR 0x188
|
|
#define CHN4_RX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 5
|
|
#define CHN4_RX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000020
|
|
#define CHN4_RX_BUFF_FULL_INT_RAW_OFFSET 4
|
|
#define CHN4_RX_BUFF_FULL_INT_RAW_MASK 0x00000010
|
|
#define CHN4_RX_EXCEED_THRS_INT_RAW_OFFSET 3
|
|
#define CHN4_RX_EXCEED_THRS_INT_RAW_MASK 0x00000008
|
|
#define CHN4_RX_EOF_INT_RAW_OFFSET 2
|
|
#define CHN4_RX_EOF_INT_RAW_MASK 0x00000004
|
|
#define CHN4_RX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN4_RX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN4_RX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN4_RX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN4_INTR_ST_ADDR 0x18C
|
|
#define CHN4_RX_OWNER_IS_NOT_HW_INT_ST_OFFSET 5
|
|
#define CHN4_RX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000020
|
|
#define CHN4_RX_BUFF_FULL_INT_ST_OFFSET 4
|
|
#define CHN4_RX_BUFF_FULL_INT_ST_MASK 0x00000010
|
|
#define CHN4_RX_EXCEED_THRS_INT_ST_OFFSET 3
|
|
#define CHN4_RX_EXCEED_THRS_INT_ST_MASK 0x00000008
|
|
#define CHN4_RX_EOF_INT_ST_OFFSET 2
|
|
#define CHN4_RX_EOF_INT_ST_MASK 0x00000004
|
|
#define CHN4_RX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN4_RX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN4_RX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN4_RX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN4_INTR_ENA_ADDR 0x190
|
|
#define CHN4_RX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 5
|
|
#define CHN4_RX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000020
|
|
#define CHN4_RX_BUFF_FULL_INT_ENA_OFFSET 4
|
|
#define CHN4_RX_BUFF_FULL_INT_ENA_MASK 0x00000010
|
|
#define CHN4_RX_EXCEED_THRS_INT_ENA_OFFSET 3
|
|
#define CHN4_RX_EXCEED_THRS_INT_ENA_MASK 0x00000008
|
|
#define CHN4_RX_EOF_INT_ENA_OFFSET 2
|
|
#define CHN4_RX_EOF_INT_ENA_MASK 0x00000004
|
|
#define CHN4_RX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN4_RX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN4_RX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN4_RX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN4_INTR_CLR_ADDR 0x194
|
|
#define CHN4_RX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 5
|
|
#define CHN4_RX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000020
|
|
#define CHN4_RX_BUFF_FULL_INT_CLR_OFFSET 4
|
|
#define CHN4_RX_BUFF_FULL_INT_CLR_MASK 0x00000010
|
|
#define CHN4_RX_EXCEED_THRS_INT_CLR_OFFSET 3
|
|
#define CHN4_RX_EXCEED_THRS_INT_CLR_MASK 0x00000008
|
|
#define CHN4_RX_EOF_INT_CLR_OFFSET 2
|
|
#define CHN4_RX_EOF_INT_CLR_MASK 0x00000004
|
|
#define CHN4_RX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN4_RX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN4_RX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN4_RX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN5_CFG0_ADDR 0x1A0
|
|
#define CHN5_RX_LINK_ADDR_OFFSET 0
|
|
#define CHN5_RX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN5_CFG1_ADDR 0x1A4
|
|
#define CHN5_RX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN5_RX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN5_RX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN5_RX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN5_RX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN5_RX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN5_RX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN5_RX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN5_RX_OWNER_FLAG_ENA_OFFSET 17
|
|
#define CHN5_RX_OWNER_FLAG_ENA_MASK 0x00020000
|
|
#define CHN5_RX_FULL_THRS_OFFSET 5
|
|
#define CHN5_RX_FULL_THRS_MASK 0x0001FFE0
|
|
#define CHN5_RX_STOP_OFFSET 4
|
|
#define CHN5_RX_STOP_MASK 0x00000010
|
|
#define CHN5_RX_RESTART_OFFSET 3
|
|
#define CHN5_RX_RESTART_MASK 0x00000008
|
|
#define CHN5_RX_START_OFFSET 2
|
|
#define CHN5_RX_START_MASK 0x00000004
|
|
#define CHN5_RX_PRIORITY_OFFSET 0
|
|
#define CHN5_RX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN5_INTR_RAW_ADDR 0x1A8
|
|
#define CHN5_RX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 5
|
|
#define CHN5_RX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000020
|
|
#define CHN5_RX_BUFF_FULL_INT_RAW_OFFSET 4
|
|
#define CHN5_RX_BUFF_FULL_INT_RAW_MASK 0x00000010
|
|
#define CHN5_RX_EXCEED_THRS_INT_RAW_OFFSET 3
|
|
#define CHN5_RX_EXCEED_THRS_INT_RAW_MASK 0x00000008
|
|
#define CHN5_RX_EOF_INT_RAW_OFFSET 2
|
|
#define CHN5_RX_EOF_INT_RAW_MASK 0x00000004
|
|
#define CHN5_RX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN5_RX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN5_RX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN5_RX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN5_INTR_ST_ADDR 0x1AC
|
|
#define CHN5_RX_OWNER_IS_NOT_HW_INT_ST_OFFSET 5
|
|
#define CHN5_RX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000020
|
|
#define CHN5_RX_BUFF_FULL_INT_ST_OFFSET 4
|
|
#define CHN5_RX_BUFF_FULL_INT_ST_MASK 0x00000010
|
|
#define CHN5_RX_EXCEED_THRS_INT_ST_OFFSET 3
|
|
#define CHN5_RX_EXCEED_THRS_INT_ST_MASK 0x00000008
|
|
#define CHN5_RX_EOF_INT_ST_OFFSET 2
|
|
#define CHN5_RX_EOF_INT_ST_MASK 0x00000004
|
|
#define CHN5_RX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN5_RX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN5_RX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN5_RX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN5_INTR_ENA_ADDR 0x1B0
|
|
#define CHN5_RX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 5
|
|
#define CHN5_RX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000020
|
|
#define CHN5_RX_BUFF_FULL_INT_ENA_OFFSET 4
|
|
#define CHN5_RX_BUFF_FULL_INT_ENA_MASK 0x00000010
|
|
#define CHN5_RX_EXCEED_THRS_INT_ENA_OFFSET 3
|
|
#define CHN5_RX_EXCEED_THRS_INT_ENA_MASK 0x00000008
|
|
#define CHN5_RX_EOF_INT_ENA_OFFSET 2
|
|
#define CHN5_RX_EOF_INT_ENA_MASK 0x00000004
|
|
#define CHN5_RX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN5_RX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN5_RX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN5_RX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN5_INTR_CLR_ADDR 0x1B4
|
|
#define CHN5_RX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 5
|
|
#define CHN5_RX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000020
|
|
#define CHN5_RX_BUFF_FULL_INT_CLR_OFFSET 4
|
|
#define CHN5_RX_BUFF_FULL_INT_CLR_MASK 0x00000010
|
|
#define CHN5_RX_EXCEED_THRS_INT_CLR_OFFSET 3
|
|
#define CHN5_RX_EXCEED_THRS_INT_CLR_MASK 0x00000008
|
|
#define CHN5_RX_EOF_INT_CLR_OFFSET 2
|
|
#define CHN5_RX_EOF_INT_CLR_MASK 0x00000004
|
|
#define CHN5_RX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN5_RX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN5_RX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN5_RX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN6_CFG0_ADDR 0x1C0
|
|
#define CHN6_RX_LINK_ADDR_OFFSET 0
|
|
#define CHN6_RX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN6_CFG1_ADDR 0x1C4
|
|
#define CHN6_RX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN6_RX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN6_RX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN6_RX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN6_RX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN6_RX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN6_RX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN6_RX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN6_RX_OWNER_FLAG_ENA_OFFSET 17
|
|
#define CHN6_RX_OWNER_FLAG_ENA_MASK 0x00020000
|
|
#define CHN6_RX_FULL_THRS_OFFSET 5
|
|
#define CHN6_RX_FULL_THRS_MASK 0x0001FFE0
|
|
#define CHN6_RX_STOP_OFFSET 4
|
|
#define CHN6_RX_STOP_MASK 0x00000010
|
|
#define CHN6_RX_RESTART_OFFSET 3
|
|
#define CHN6_RX_RESTART_MASK 0x00000008
|
|
#define CHN6_RX_START_OFFSET 2
|
|
#define CHN6_RX_START_MASK 0x00000004
|
|
#define CHN6_RX_PRIORITY_OFFSET 0
|
|
#define CHN6_RX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN6_INTR_RAW_ADDR 0x1C8
|
|
#define CHN6_RX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 5
|
|
#define CHN6_RX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000020
|
|
#define CHN6_RX_BUFF_FULL_INT_RAW_OFFSET 4
|
|
#define CHN6_RX_BUFF_FULL_INT_RAW_MASK 0x00000010
|
|
#define CHN6_RX_EXCEED_THRS_INT_RAW_OFFSET 3
|
|
#define CHN6_RX_EXCEED_THRS_INT_RAW_MASK 0x00000008
|
|
#define CHN6_RX_EOF_INT_RAW_OFFSET 2
|
|
#define CHN6_RX_EOF_INT_RAW_MASK 0x00000004
|
|
#define CHN6_RX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN6_RX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN6_RX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN6_RX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN6_INTR_ST_ADDR 0x1CC
|
|
#define CHN6_RX_OWNER_IS_NOT_HW_INT_ST_OFFSET 5
|
|
#define CHN6_RX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000020
|
|
#define CHN6_RX_BUFF_FULL_INT_ST_OFFSET 4
|
|
#define CHN6_RX_BUFF_FULL_INT_ST_MASK 0x00000010
|
|
#define CHN6_RX_EXCEED_THRS_INT_ST_OFFSET 3
|
|
#define CHN6_RX_EXCEED_THRS_INT_ST_MASK 0x00000008
|
|
#define CHN6_RX_EOF_INT_ST_OFFSET 2
|
|
#define CHN6_RX_EOF_INT_ST_MASK 0x00000004
|
|
#define CHN6_RX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN6_RX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN6_RX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN6_RX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN6_INTR_ENA_ADDR 0x1D0
|
|
#define CHN6_RX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 5
|
|
#define CHN6_RX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000020
|
|
#define CHN6_RX_BUFF_FULL_INT_ENA_OFFSET 4
|
|
#define CHN6_RX_BUFF_FULL_INT_ENA_MASK 0x00000010
|
|
#define CHN6_RX_EXCEED_THRS_INT_ENA_OFFSET 3
|
|
#define CHN6_RX_EXCEED_THRS_INT_ENA_MASK 0x00000008
|
|
#define CHN6_RX_EOF_INT_ENA_OFFSET 2
|
|
#define CHN6_RX_EOF_INT_ENA_MASK 0x00000004
|
|
#define CHN6_RX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN6_RX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN6_RX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN6_RX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN6_INTR_CLR_ADDR 0x1D4
|
|
#define CHN6_RX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 5
|
|
#define CHN6_RX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000020
|
|
#define CHN6_RX_BUFF_FULL_INT_CLR_OFFSET 4
|
|
#define CHN6_RX_BUFF_FULL_INT_CLR_MASK 0x00000010
|
|
#define CHN6_RX_EXCEED_THRS_INT_CLR_OFFSET 3
|
|
#define CHN6_RX_EXCEED_THRS_INT_CLR_MASK 0x00000008
|
|
#define CHN6_RX_EOF_INT_CLR_OFFSET 2
|
|
#define CHN6_RX_EOF_INT_CLR_MASK 0x00000004
|
|
#define CHN6_RX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN6_RX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN6_RX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN6_RX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN7_CFG0_ADDR 0x1E0
|
|
#define CHN7_RX_LINK_ADDR_OFFSET 0
|
|
#define CHN7_RX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN7_CFG1_ADDR 0x1E4
|
|
#define CHN7_RX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN7_RX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN7_RX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN7_RX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN7_RX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN7_RX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN7_RX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN7_RX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN7_RX_OWNER_FLAG_ENA_OFFSET 17
|
|
#define CHN7_RX_OWNER_FLAG_ENA_MASK 0x00020000
|
|
#define CHN7_RX_FULL_THRS_OFFSET 5
|
|
#define CHN7_RX_FULL_THRS_MASK 0x0001FFE0
|
|
#define CHN7_RX_STOP_OFFSET 4
|
|
#define CHN7_RX_STOP_MASK 0x00000010
|
|
#define CHN7_RX_RESTART_OFFSET 3
|
|
#define CHN7_RX_RESTART_MASK 0x00000008
|
|
#define CHN7_RX_START_OFFSET 2
|
|
#define CHN7_RX_START_MASK 0x00000004
|
|
#define CHN7_RX_PRIORITY_OFFSET 0
|
|
#define CHN7_RX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN7_INTR_RAW_ADDR 0x1E8
|
|
#define CHN7_RX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 5
|
|
#define CHN7_RX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000020
|
|
#define CHN7_RX_BUFF_FULL_INT_RAW_OFFSET 4
|
|
#define CHN7_RX_BUFF_FULL_INT_RAW_MASK 0x00000010
|
|
#define CHN7_RX_EXCEED_THRS_INT_RAW_OFFSET 3
|
|
#define CHN7_RX_EXCEED_THRS_INT_RAW_MASK 0x00000008
|
|
#define CHN7_RX_EOF_INT_RAW_OFFSET 2
|
|
#define CHN7_RX_EOF_INT_RAW_MASK 0x00000004
|
|
#define CHN7_RX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN7_RX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN7_RX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN7_RX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN7_INTR_ST_ADDR 0x1EC
|
|
#define CHN7_RX_OWNER_IS_NOT_HW_INT_ST_OFFSET 5
|
|
#define CHN7_RX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000020
|
|
#define CHN7_RX_BUFF_FULL_INT_ST_OFFSET 4
|
|
#define CHN7_RX_BUFF_FULL_INT_ST_MASK 0x00000010
|
|
#define CHN7_RX_EXCEED_THRS_INT_ST_OFFSET 3
|
|
#define CHN7_RX_EXCEED_THRS_INT_ST_MASK 0x00000008
|
|
#define CHN7_RX_EOF_INT_ST_OFFSET 2
|
|
#define CHN7_RX_EOF_INT_ST_MASK 0x00000004
|
|
#define CHN7_RX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN7_RX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN7_RX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN7_RX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN7_INTR_ENA_ADDR 0x1F0
|
|
#define CHN7_RX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 5
|
|
#define CHN7_RX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000020
|
|
#define CHN7_RX_BUFF_FULL_INT_ENA_OFFSET 4
|
|
#define CHN7_RX_BUFF_FULL_INT_ENA_MASK 0x00000010
|
|
#define CHN7_RX_EXCEED_THRS_INT_ENA_OFFSET 3
|
|
#define CHN7_RX_EXCEED_THRS_INT_ENA_MASK 0x00000008
|
|
#define CHN7_RX_EOF_INT_ENA_OFFSET 2
|
|
#define CHN7_RX_EOF_INT_ENA_MASK 0x00000004
|
|
#define CHN7_RX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN7_RX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN7_RX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN7_RX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN7_INTR_CLR_ADDR 0x1F4
|
|
#define CHN7_RX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 5
|
|
#define CHN7_RX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000020
|
|
#define CHN7_RX_BUFF_FULL_INT_CLR_OFFSET 4
|
|
#define CHN7_RX_BUFF_FULL_INT_CLR_MASK 0x00000010
|
|
#define CHN7_RX_EXCEED_THRS_INT_CLR_OFFSET 3
|
|
#define CHN7_RX_EXCEED_THRS_INT_CLR_MASK 0x00000008
|
|
#define CHN7_RX_EOF_INT_CLR_OFFSET 2
|
|
#define CHN7_RX_EOF_INT_CLR_MASK 0x00000004
|
|
#define CHN7_RX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN7_RX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN7_RX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN7_RX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN8_CFG0_ADDR 0x200
|
|
#define CHN8_RX_LINK_ADDR_OFFSET 0
|
|
#define CHN8_RX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN8_CFG1_ADDR 0x204
|
|
#define CHN8_RX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN8_RX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN8_RX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN8_RX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN8_RX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN8_RX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN8_RX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN8_RX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN8_RX_OWNER_FLAG_ENA_OFFSET 17
|
|
#define CHN8_RX_OWNER_FLAG_ENA_MASK 0x00020000
|
|
#define CHN8_RX_FULL_THRS_OFFSET 5
|
|
#define CHN8_RX_FULL_THRS_MASK 0x0001FFE0
|
|
#define CHN8_RX_STOP_OFFSET 4
|
|
#define CHN8_RX_STOP_MASK 0x00000010
|
|
#define CHN8_RX_RESTART_OFFSET 3
|
|
#define CHN8_RX_RESTART_MASK 0x00000008
|
|
#define CHN8_RX_START_OFFSET 2
|
|
#define CHN8_RX_START_MASK 0x00000004
|
|
#define CHN8_RX_PRIORITY_OFFSET 0
|
|
#define CHN8_RX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN8_INTR_RAW_ADDR 0x208
|
|
#define CHN8_RX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 5
|
|
#define CHN8_RX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000020
|
|
#define CHN8_RX_BUFF_FULL_INT_RAW_OFFSET 4
|
|
#define CHN8_RX_BUFF_FULL_INT_RAW_MASK 0x00000010
|
|
#define CHN8_RX_EXCEED_THRS_INT_RAW_OFFSET 3
|
|
#define CHN8_RX_EXCEED_THRS_INT_RAW_MASK 0x00000008
|
|
#define CHN8_RX_EOF_INT_RAW_OFFSET 2
|
|
#define CHN8_RX_EOF_INT_RAW_MASK 0x00000004
|
|
#define CHN8_RX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN8_RX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN8_RX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN8_RX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN8_INTR_ST_ADDR 0x20C
|
|
#define CHN8_RX_OWNER_IS_NOT_HW_INT_ST_OFFSET 5
|
|
#define CHN8_RX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000020
|
|
#define CHN8_RX_BUFF_FULL_INT_ST_OFFSET 4
|
|
#define CHN8_RX_BUFF_FULL_INT_ST_MASK 0x00000010
|
|
#define CHN8_RX_EXCEED_THRS_INT_ST_OFFSET 3
|
|
#define CHN8_RX_EXCEED_THRS_INT_ST_MASK 0x00000008
|
|
#define CHN8_RX_EOF_INT_ST_OFFSET 2
|
|
#define CHN8_RX_EOF_INT_ST_MASK 0x00000004
|
|
#define CHN8_RX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN8_RX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN8_RX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN8_RX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN8_INTR_ENA_ADDR 0x210
|
|
#define CHN8_RX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 5
|
|
#define CHN8_RX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000020
|
|
#define CHN8_RX_BUFF_FULL_INT_ENA_OFFSET 4
|
|
#define CHN8_RX_BUFF_FULL_INT_ENA_MASK 0x00000010
|
|
#define CHN8_RX_EXCEED_THRS_INT_ENA_OFFSET 3
|
|
#define CHN8_RX_EXCEED_THRS_INT_ENA_MASK 0x00000008
|
|
#define CHN8_RX_EOF_INT_ENA_OFFSET 2
|
|
#define CHN8_RX_EOF_INT_ENA_MASK 0x00000004
|
|
#define CHN8_RX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN8_RX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN8_RX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN8_RX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN8_INTR_CLR_ADDR 0x214
|
|
#define CHN8_RX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 5
|
|
#define CHN8_RX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000020
|
|
#define CHN8_RX_BUFF_FULL_INT_CLR_OFFSET 4
|
|
#define CHN8_RX_BUFF_FULL_INT_CLR_MASK 0x00000010
|
|
#define CHN8_RX_EXCEED_THRS_INT_CLR_OFFSET 3
|
|
#define CHN8_RX_EXCEED_THRS_INT_CLR_MASK 0x00000008
|
|
#define CHN8_RX_EOF_INT_CLR_OFFSET 2
|
|
#define CHN8_RX_EOF_INT_CLR_MASK 0x00000004
|
|
#define CHN8_RX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN8_RX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN8_RX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN8_RX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN9_CFG0_ADDR 0x220
|
|
#define CHN9_RX_LINK_ADDR_OFFSET 0
|
|
#define CHN9_RX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN9_CFG1_ADDR 0x224
|
|
#define CHN9_RX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN9_RX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN9_RX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN9_RX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN9_RX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN9_RX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN9_RX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN9_RX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN9_RX_OWNER_FLAG_ENA_OFFSET 17
|
|
#define CHN9_RX_OWNER_FLAG_ENA_MASK 0x00020000
|
|
#define CHN9_RX_FULL_THRS_OFFSET 5
|
|
#define CHN9_RX_FULL_THRS_MASK 0x0001FFE0
|
|
#define CHN9_RX_STOP_OFFSET 4
|
|
#define CHN9_RX_STOP_MASK 0x00000010
|
|
#define CHN9_RX_RESTART_OFFSET 3
|
|
#define CHN9_RX_RESTART_MASK 0x00000008
|
|
#define CHN9_RX_START_OFFSET 2
|
|
#define CHN9_RX_START_MASK 0x00000004
|
|
#define CHN9_RX_PRIORITY_OFFSET 0
|
|
#define CHN9_RX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN9_INTR_RAW_ADDR 0x228
|
|
#define CHN9_RX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 5
|
|
#define CHN9_RX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000020
|
|
#define CHN9_RX_BUFF_FULL_INT_RAW_OFFSET 4
|
|
#define CHN9_RX_BUFF_FULL_INT_RAW_MASK 0x00000010
|
|
#define CHN9_RX_EXCEED_THRS_INT_RAW_OFFSET 3
|
|
#define CHN9_RX_EXCEED_THRS_INT_RAW_MASK 0x00000008
|
|
#define CHN9_RX_EOF_INT_RAW_OFFSET 2
|
|
#define CHN9_RX_EOF_INT_RAW_MASK 0x00000004
|
|
#define CHN9_RX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN9_RX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN9_RX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN9_RX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN9_INTR_ST_ADDR 0x22C
|
|
#define CHN9_RX_OWNER_IS_NOT_HW_INT_ST_OFFSET 5
|
|
#define CHN9_RX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000020
|
|
#define CHN9_RX_BUFF_FULL_INT_ST_OFFSET 4
|
|
#define CHN9_RX_BUFF_FULL_INT_ST_MASK 0x00000010
|
|
#define CHN9_RX_EXCEED_THRS_INT_ST_OFFSET 3
|
|
#define CHN9_RX_EXCEED_THRS_INT_ST_MASK 0x00000008
|
|
#define CHN9_RX_EOF_INT_ST_OFFSET 2
|
|
#define CHN9_RX_EOF_INT_ST_MASK 0x00000004
|
|
#define CHN9_RX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN9_RX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN9_RX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN9_RX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN9_INTR_ENA_ADDR 0x230
|
|
#define CHN9_RX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 5
|
|
#define CHN9_RX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000020
|
|
#define CHN9_RX_BUFF_FULL_INT_ENA_OFFSET 4
|
|
#define CHN9_RX_BUFF_FULL_INT_ENA_MASK 0x00000010
|
|
#define CHN9_RX_EXCEED_THRS_INT_ENA_OFFSET 3
|
|
#define CHN9_RX_EXCEED_THRS_INT_ENA_MASK 0x00000008
|
|
#define CHN9_RX_EOF_INT_ENA_OFFSET 2
|
|
#define CHN9_RX_EOF_INT_ENA_MASK 0x00000004
|
|
#define CHN9_RX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN9_RX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN9_RX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN9_RX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN9_INTR_CLR_ADDR 0x234
|
|
#define CHN9_RX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 5
|
|
#define CHN9_RX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000020
|
|
#define CHN9_RX_BUFF_FULL_INT_CLR_OFFSET 4
|
|
#define CHN9_RX_BUFF_FULL_INT_CLR_MASK 0x00000010
|
|
#define CHN9_RX_EXCEED_THRS_INT_CLR_OFFSET 3
|
|
#define CHN9_RX_EXCEED_THRS_INT_CLR_MASK 0x00000008
|
|
#define CHN9_RX_EOF_INT_CLR_OFFSET 2
|
|
#define CHN9_RX_EOF_INT_CLR_MASK 0x00000004
|
|
#define CHN9_RX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN9_RX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN9_RX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN9_RX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN10_CFG0_ADDR 0x240
|
|
#define CHN10_RX_LINK_ADDR_OFFSET 0
|
|
#define CHN10_RX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN10_CFG1_ADDR 0x244
|
|
#define CHN10_RX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN10_RX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN10_RX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN10_RX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN10_RX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN10_RX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN10_RX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN10_RX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN10_RX_OWNER_FLAG_ENA_OFFSET 17
|
|
#define CHN10_RX_OWNER_FLAG_ENA_MASK 0x00020000
|
|
#define CHN10_RX_FULL_THRS_OFFSET 5
|
|
#define CHN10_RX_FULL_THRS_MASK 0x0001FFE0
|
|
#define CHN10_RX_STOP_OFFSET 4
|
|
#define CHN10_RX_STOP_MASK 0x00000010
|
|
#define CHN10_RX_RESTART_OFFSET 3
|
|
#define CHN10_RX_RESTART_MASK 0x00000008
|
|
#define CHN10_RX_START_OFFSET 2
|
|
#define CHN10_RX_START_MASK 0x00000004
|
|
#define CHN10_RX_PRIORITY_OFFSET 0
|
|
#define CHN10_RX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN10_INTR_RAW_ADDR 0x248
|
|
#define CHN10_RX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 5
|
|
#define CHN10_RX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000020
|
|
#define CHN10_RX_BUFF_FULL_INT_RAW_OFFSET 4
|
|
#define CHN10_RX_BUFF_FULL_INT_RAW_MASK 0x00000010
|
|
#define CHN10_RX_EXCEED_THRS_INT_RAW_OFFSET 3
|
|
#define CHN10_RX_EXCEED_THRS_INT_RAW_MASK 0x00000008
|
|
#define CHN10_RX_EOF_INT_RAW_OFFSET 2
|
|
#define CHN10_RX_EOF_INT_RAW_MASK 0x00000004
|
|
#define CHN10_RX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN10_RX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN10_RX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN10_RX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN10_INTR_ST_ADDR 0x24C
|
|
#define CHN10_RX_OWNER_IS_NOT_HW_INT_ST_OFFSET 5
|
|
#define CHN10_RX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000020
|
|
#define CHN10_RX_BUFF_FULL_INT_ST_OFFSET 4
|
|
#define CHN10_RX_BUFF_FULL_INT_ST_MASK 0x00000010
|
|
#define CHN10_RX_EXCEED_THRS_INT_ST_OFFSET 3
|
|
#define CHN10_RX_EXCEED_THRS_INT_ST_MASK 0x00000008
|
|
#define CHN10_RX_EOF_INT_ST_OFFSET 2
|
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#define CHN10_RX_EOF_INT_ST_MASK 0x00000004
|
|
#define CHN10_RX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN10_RX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN10_RX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN10_RX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN10_INTR_ENA_ADDR 0x250
|
|
#define CHN10_RX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 5
|
|
#define CHN10_RX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000020
|
|
#define CHN10_RX_BUFF_FULL_INT_ENA_OFFSET 4
|
|
#define CHN10_RX_BUFF_FULL_INT_ENA_MASK 0x00000010
|
|
#define CHN10_RX_EXCEED_THRS_INT_ENA_OFFSET 3
|
|
#define CHN10_RX_EXCEED_THRS_INT_ENA_MASK 0x00000008
|
|
#define CHN10_RX_EOF_INT_ENA_OFFSET 2
|
|
#define CHN10_RX_EOF_INT_ENA_MASK 0x00000004
|
|
#define CHN10_RX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN10_RX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN10_RX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN10_RX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN10_INTR_CLR_ADDR 0x254
|
|
#define CHN10_RX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 5
|
|
#define CHN10_RX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000020
|
|
#define CHN10_RX_BUFF_FULL_INT_CLR_OFFSET 4
|
|
#define CHN10_RX_BUFF_FULL_INT_CLR_MASK 0x00000010
|
|
#define CHN10_RX_EXCEED_THRS_INT_CLR_OFFSET 3
|
|
#define CHN10_RX_EXCEED_THRS_INT_CLR_MASK 0x00000008
|
|
#define CHN10_RX_EOF_INT_CLR_OFFSET 2
|
|
#define CHN10_RX_EOF_INT_CLR_MASK 0x00000004
|
|
#define CHN10_RX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN10_RX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN10_RX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN10_RX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN11_CFG0_ADDR 0x260
|
|
#define CHN11_RX_LINK_ADDR_OFFSET 0
|
|
#define CHN11_RX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN11_CFG1_ADDR 0x264
|
|
#define CHN11_RX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN11_RX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN11_RX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN11_RX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN11_RX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN11_RX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN11_RX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN11_RX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN11_RX_OWNER_FLAG_ENA_OFFSET 17
|
|
#define CHN11_RX_OWNER_FLAG_ENA_MASK 0x00020000
|
|
#define CHN11_RX_FULL_THRS_OFFSET 5
|
|
#define CHN11_RX_FULL_THRS_MASK 0x0001FFE0
|
|
#define CHN11_RX_STOP_OFFSET 4
|
|
#define CHN11_RX_STOP_MASK 0x00000010
|
|
#define CHN11_RX_RESTART_OFFSET 3
|
|
#define CHN11_RX_RESTART_MASK 0x00000008
|
|
#define CHN11_RX_START_OFFSET 2
|
|
#define CHN11_RX_START_MASK 0x00000004
|
|
#define CHN11_RX_PRIORITY_OFFSET 0
|
|
#define CHN11_RX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN11_INTR_RAW_ADDR 0x268
|
|
#define CHN11_RX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 5
|
|
#define CHN11_RX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000020
|
|
#define CHN11_RX_BUFF_FULL_INT_RAW_OFFSET 4
|
|
#define CHN11_RX_BUFF_FULL_INT_RAW_MASK 0x00000010
|
|
#define CHN11_RX_EXCEED_THRS_INT_RAW_OFFSET 3
|
|
#define CHN11_RX_EXCEED_THRS_INT_RAW_MASK 0x00000008
|
|
#define CHN11_RX_EOF_INT_RAW_OFFSET 2
|
|
#define CHN11_RX_EOF_INT_RAW_MASK 0x00000004
|
|
#define CHN11_RX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN11_RX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN11_RX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN11_RX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN11_INTR_ST_ADDR 0x26C
|
|
#define CHN11_RX_OWNER_IS_NOT_HW_INT_ST_OFFSET 5
|
|
#define CHN11_RX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000020
|
|
#define CHN11_RX_BUFF_FULL_INT_ST_OFFSET 4
|
|
#define CHN11_RX_BUFF_FULL_INT_ST_MASK 0x00000010
|
|
#define CHN11_RX_EXCEED_THRS_INT_ST_OFFSET 3
|
|
#define CHN11_RX_EXCEED_THRS_INT_ST_MASK 0x00000008
|
|
#define CHN11_RX_EOF_INT_ST_OFFSET 2
|
|
#define CHN11_RX_EOF_INT_ST_MASK 0x00000004
|
|
#define CHN11_RX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN11_RX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN11_RX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN11_RX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN11_INTR_ENA_ADDR 0x270
|
|
#define CHN11_RX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 5
|
|
#define CHN11_RX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000020
|
|
#define CHN11_RX_BUFF_FULL_INT_ENA_OFFSET 4
|
|
#define CHN11_RX_BUFF_FULL_INT_ENA_MASK 0x00000010
|
|
#define CHN11_RX_EXCEED_THRS_INT_ENA_OFFSET 3
|
|
#define CHN11_RX_EXCEED_THRS_INT_ENA_MASK 0x00000008
|
|
#define CHN11_RX_EOF_INT_ENA_OFFSET 2
|
|
#define CHN11_RX_EOF_INT_ENA_MASK 0x00000004
|
|
#define CHN11_RX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN11_RX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN11_RX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN11_RX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN11_INTR_CLR_ADDR 0x274
|
|
#define CHN11_RX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 5
|
|
#define CHN11_RX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000020
|
|
#define CHN11_RX_BUFF_FULL_INT_CLR_OFFSET 4
|
|
#define CHN11_RX_BUFF_FULL_INT_CLR_MASK 0x00000010
|
|
#define CHN11_RX_EXCEED_THRS_INT_CLR_OFFSET 3
|
|
#define CHN11_RX_EXCEED_THRS_INT_CLR_MASK 0x00000008
|
|
#define CHN11_RX_EOF_INT_CLR_OFFSET 2
|
|
#define CHN11_RX_EOF_INT_CLR_MASK 0x00000004
|
|
#define CHN11_RX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN11_RX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN11_RX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN11_RX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN12_CFG0_ADDR 0x280
|
|
#define CHN12_RX_LINK_ADDR_OFFSET 0
|
|
#define CHN12_RX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN12_CFG1_ADDR 0x284
|
|
#define CHN12_RX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN12_RX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN12_RX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN12_RX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN12_RX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN12_RX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN12_RX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN12_RX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN12_RX_OWNER_FLAG_ENA_OFFSET 17
|
|
#define CHN12_RX_OWNER_FLAG_ENA_MASK 0x00020000
|
|
#define CHN12_RX_FULL_THRS_OFFSET 5
|
|
#define CHN12_RX_FULL_THRS_MASK 0x0001FFE0
|
|
#define CHN12_RX_STOP_OFFSET 4
|
|
#define CHN12_RX_STOP_MASK 0x00000010
|
|
#define CHN12_RX_RESTART_OFFSET 3
|
|
#define CHN12_RX_RESTART_MASK 0x00000008
|
|
#define CHN12_RX_START_OFFSET 2
|
|
#define CHN12_RX_START_MASK 0x00000004
|
|
#define CHN12_RX_PRIORITY_OFFSET 0
|
|
#define CHN12_RX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN12_INTR_RAW_ADDR 0x288
|
|
#define CHN12_RX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 5
|
|
#define CHN12_RX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000020
|
|
#define CHN12_RX_BUFF_FULL_INT_RAW_OFFSET 4
|
|
#define CHN12_RX_BUFF_FULL_INT_RAW_MASK 0x00000010
|
|
#define CHN12_RX_EXCEED_THRS_INT_RAW_OFFSET 3
|
|
#define CHN12_RX_EXCEED_THRS_INT_RAW_MASK 0x00000008
|
|
#define CHN12_RX_EOF_INT_RAW_OFFSET 2
|
|
#define CHN12_RX_EOF_INT_RAW_MASK 0x00000004
|
|
#define CHN12_RX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN12_RX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN12_RX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN12_RX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN12_INTR_ST_ADDR 0x28C
|
|
#define CHN12_RX_OWNER_IS_NOT_HW_INT_ST_OFFSET 5
|
|
#define CHN12_RX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000020
|
|
#define CHN12_RX_BUFF_FULL_INT_ST_OFFSET 4
|
|
#define CHN12_RX_BUFF_FULL_INT_ST_MASK 0x00000010
|
|
#define CHN12_RX_EXCEED_THRS_INT_ST_OFFSET 3
|
|
#define CHN12_RX_EXCEED_THRS_INT_ST_MASK 0x00000008
|
|
#define CHN12_RX_EOF_INT_ST_OFFSET 2
|
|
#define CHN12_RX_EOF_INT_ST_MASK 0x00000004
|
|
#define CHN12_RX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN12_RX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN12_RX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN12_RX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN12_INTR_ENA_ADDR 0x290
|
|
#define CHN12_RX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 5
|
|
#define CHN12_RX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000020
|
|
#define CHN12_RX_BUFF_FULL_INT_ENA_OFFSET 4
|
|
#define CHN12_RX_BUFF_FULL_INT_ENA_MASK 0x00000010
|
|
#define CHN12_RX_EXCEED_THRS_INT_ENA_OFFSET 3
|
|
#define CHN12_RX_EXCEED_THRS_INT_ENA_MASK 0x00000008
|
|
#define CHN12_RX_EOF_INT_ENA_OFFSET 2
|
|
#define CHN12_RX_EOF_INT_ENA_MASK 0x00000004
|
|
#define CHN12_RX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN12_RX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN12_RX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN12_RX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN12_INTR_CLR_ADDR 0x294
|
|
#define CHN12_RX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 5
|
|
#define CHN12_RX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000020
|
|
#define CHN12_RX_BUFF_FULL_INT_CLR_OFFSET 4
|
|
#define CHN12_RX_BUFF_FULL_INT_CLR_MASK 0x00000010
|
|
#define CHN12_RX_EXCEED_THRS_INT_CLR_OFFSET 3
|
|
#define CHN12_RX_EXCEED_THRS_INT_CLR_MASK 0x00000008
|
|
#define CHN12_RX_EOF_INT_CLR_OFFSET 2
|
|
#define CHN12_RX_EOF_INT_CLR_MASK 0x00000004
|
|
#define CHN12_RX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN12_RX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN12_RX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN12_RX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN13_CFG0_ADDR 0x2A0
|
|
#define CHN13_RX_LINK_ADDR_OFFSET 0
|
|
#define CHN13_RX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN13_CFG1_ADDR 0x2A4
|
|
#define CHN13_RX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN13_RX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN13_RX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN13_RX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN13_RX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN13_RX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN13_RX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN13_RX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN13_RX_OWNER_FLAG_ENA_OFFSET 17
|
|
#define CHN13_RX_OWNER_FLAG_ENA_MASK 0x00020000
|
|
#define CHN13_RX_FULL_THRS_OFFSET 5
|
|
#define CHN13_RX_FULL_THRS_MASK 0x0001FFE0
|
|
#define CHN13_RX_STOP_OFFSET 4
|
|
#define CHN13_RX_STOP_MASK 0x00000010
|
|
#define CHN13_RX_RESTART_OFFSET 3
|
|
#define CHN13_RX_RESTART_MASK 0x00000008
|
|
#define CHN13_RX_START_OFFSET 2
|
|
#define CHN13_RX_START_MASK 0x00000004
|
|
#define CHN13_RX_PRIORITY_OFFSET 0
|
|
#define CHN13_RX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN13_INTR_RAW_ADDR 0x2A8
|
|
#define CHN13_RX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 5
|
|
#define CHN13_RX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000020
|
|
#define CHN13_RX_BUFF_FULL_INT_RAW_OFFSET 4
|
|
#define CHN13_RX_BUFF_FULL_INT_RAW_MASK 0x00000010
|
|
#define CHN13_RX_EXCEED_THRS_INT_RAW_OFFSET 3
|
|
#define CHN13_RX_EXCEED_THRS_INT_RAW_MASK 0x00000008
|
|
#define CHN13_RX_EOF_INT_RAW_OFFSET 2
|
|
#define CHN13_RX_EOF_INT_RAW_MASK 0x00000004
|
|
#define CHN13_RX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN13_RX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN13_RX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN13_RX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN13_INTR_ST_ADDR 0x2AC
|
|
#define CHN13_RX_OWNER_IS_NOT_HW_INT_ST_OFFSET 5
|
|
#define CHN13_RX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000020
|
|
#define CHN13_RX_BUFF_FULL_INT_ST_OFFSET 4
|
|
#define CHN13_RX_BUFF_FULL_INT_ST_MASK 0x00000010
|
|
#define CHN13_RX_EXCEED_THRS_INT_ST_OFFSET 3
|
|
#define CHN13_RX_EXCEED_THRS_INT_ST_MASK 0x00000008
|
|
#define CHN13_RX_EOF_INT_ST_OFFSET 2
|
|
#define CHN13_RX_EOF_INT_ST_MASK 0x00000004
|
|
#define CHN13_RX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN13_RX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN13_RX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN13_RX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN13_INTR_ENA_ADDR 0x2B0
|
|
#define CHN13_RX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 5
|
|
#define CHN13_RX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000020
|
|
#define CHN13_RX_BUFF_FULL_INT_ENA_OFFSET 4
|
|
#define CHN13_RX_BUFF_FULL_INT_ENA_MASK 0x00000010
|
|
#define CHN13_RX_EXCEED_THRS_INT_ENA_OFFSET 3
|
|
#define CHN13_RX_EXCEED_THRS_INT_ENA_MASK 0x00000008
|
|
#define CHN13_RX_EOF_INT_ENA_OFFSET 2
|
|
#define CHN13_RX_EOF_INT_ENA_MASK 0x00000004
|
|
#define CHN13_RX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN13_RX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN13_RX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN13_RX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_RX_CHN13_INTR_CLR_ADDR 0x2B4
|
|
#define CHN13_RX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 5
|
|
#define CHN13_RX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000020
|
|
#define CHN13_RX_BUFF_FULL_INT_CLR_OFFSET 4
|
|
#define CHN13_RX_BUFF_FULL_INT_CLR_MASK 0x00000010
|
|
#define CHN13_RX_EXCEED_THRS_INT_CLR_OFFSET 3
|
|
#define CHN13_RX_EXCEED_THRS_INT_CLR_MASK 0x00000008
|
|
#define CHN13_RX_EOF_INT_CLR_OFFSET 2
|
|
#define CHN13_RX_EOF_INT_CLR_MASK 0x00000004
|
|
#define CHN13_RX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN13_RX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN13_RX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN13_RX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN0_CFG0_ADDR 0x400
|
|
#define CHN0_TX_LINK_ADDR_OFFSET 0
|
|
#define CHN0_TX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN0_CFG1_ADDR 0x404
|
|
#define CHN0_TX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN0_TX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN0_TX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN0_TX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN0_TX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN0_TX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN0_TX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN0_TX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN0_TX_OWNER_FLAG_ENA_OFFSET 5
|
|
#define CHN0_TX_OWNER_FLAG_ENA_MASK 0x00000020
|
|
#define CHN0_TX_STOP_OFFSET 4
|
|
#define CHN0_TX_STOP_MASK 0x00000010
|
|
#define CHN0_TX_RESTART_OFFSET 3
|
|
#define CHN0_TX_RESTART_MASK 0x00000008
|
|
#define CHN0_TX_START_OFFSET 2
|
|
#define CHN0_TX_START_MASK 0x00000004
|
|
#define CHN0_TX_PRIORITY_OFFSET 0
|
|
#define CHN0_TX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN0_INTR_RAW_ADDR 0x408
|
|
#define CHN0_TX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 2
|
|
#define CHN0_TX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000004
|
|
#define CHN0_TX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN0_TX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN0_TX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN0_TX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN0_INTR_ST_ADDR 0x40C
|
|
#define CHN0_TX_OWNER_IS_NOT_HW_INT_ST_OFFSET 2
|
|
#define CHN0_TX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000004
|
|
#define CHN0_TX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN0_TX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN0_TX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN0_TX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN0_INTR_ENA_ADDR 0x410
|
|
#define CHN0_TX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 2
|
|
#define CHN0_TX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000004
|
|
#define CHN0_TX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN0_TX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN0_TX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN0_TX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN0_INTR_CLR_ADDR 0x414
|
|
#define CHN0_TX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 2
|
|
#define CHN0_TX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000004
|
|
#define CHN0_TX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN0_TX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN0_TX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN0_TX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN1_CFG0_ADDR 0x420
|
|
#define CHN1_TX_LINK_ADDR_OFFSET 0
|
|
#define CHN1_TX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN1_CFG1_ADDR 0x424
|
|
#define CHN1_TX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN1_TX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN1_TX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN1_TX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN1_TX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN1_TX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN1_TX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN1_TX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN1_TX_OWNER_FLAG_ENA_OFFSET 5
|
|
#define CHN1_TX_OWNER_FLAG_ENA_MASK 0x00000020
|
|
#define CHN1_TX_STOP_OFFSET 4
|
|
#define CHN1_TX_STOP_MASK 0x00000010
|
|
#define CHN1_TX_RESTART_OFFSET 3
|
|
#define CHN1_TX_RESTART_MASK 0x00000008
|
|
#define CHN1_TX_START_OFFSET 2
|
|
#define CHN1_TX_START_MASK 0x00000004
|
|
#define CHN1_TX_PRIORITY_OFFSET 0
|
|
#define CHN1_TX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN1_INTR_RAW_ADDR 0x428
|
|
#define CHN1_TX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 2
|
|
#define CHN1_TX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000004
|
|
#define CHN1_TX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN1_TX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN1_TX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN1_TX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN1_INTR_ST_ADDR 0x42C
|
|
#define CHN1_TX_OWNER_IS_NOT_HW_INT_ST_OFFSET 2
|
|
#define CHN1_TX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000004
|
|
#define CHN1_TX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN1_TX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN1_TX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN1_TX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN1_INTR_ENA_ADDR 0x430
|
|
#define CHN1_TX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 2
|
|
#define CHN1_TX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000004
|
|
#define CHN1_TX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN1_TX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN1_TX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN1_TX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN1_INTR_CLR_ADDR 0x434
|
|
#define CHN1_TX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 2
|
|
#define CHN1_TX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000004
|
|
#define CHN1_TX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN1_TX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN1_TX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN1_TX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN2_CFG0_ADDR 0x440
|
|
#define CHN2_TX_LINK_ADDR_OFFSET 0
|
|
#define CHN2_TX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN2_CFG1_ADDR 0x444
|
|
#define CHN2_TX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN2_TX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN2_TX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN2_TX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN2_TX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN2_TX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN2_TX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN2_TX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN2_TX_OWNER_FLAG_ENA_OFFSET 5
|
|
#define CHN2_TX_OWNER_FLAG_ENA_MASK 0x00000020
|
|
#define CHN2_TX_STOP_OFFSET 4
|
|
#define CHN2_TX_STOP_MASK 0x00000010
|
|
#define CHN2_TX_RESTART_OFFSET 3
|
|
#define CHN2_TX_RESTART_MASK 0x00000008
|
|
#define CHN2_TX_START_OFFSET 2
|
|
#define CHN2_TX_START_MASK 0x00000004
|
|
#define CHN2_TX_PRIORITY_OFFSET 0
|
|
#define CHN2_TX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN2_INTR_RAW_ADDR 0x448
|
|
#define CHN2_TX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 2
|
|
#define CHN2_TX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000004
|
|
#define CHN2_TX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN2_TX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN2_TX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN2_TX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN2_INTR_ST_ADDR 0x44C
|
|
#define CHN2_TX_OWNER_IS_NOT_HW_INT_ST_OFFSET 2
|
|
#define CHN2_TX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000004
|
|
#define CHN2_TX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN2_TX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN2_TX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN2_TX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN2_INTR_ENA_ADDR 0x450
|
|
#define CHN2_TX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 2
|
|
#define CHN2_TX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000004
|
|
#define CHN2_TX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN2_TX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN2_TX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN2_TX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN2_INTR_CLR_ADDR 0x454
|
|
#define CHN2_TX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 2
|
|
#define CHN2_TX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000004
|
|
#define CHN2_TX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN2_TX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN2_TX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN2_TX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN3_CFG0_ADDR 0x460
|
|
#define CHN3_TX_LINK_ADDR_OFFSET 0
|
|
#define CHN3_TX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN3_CFG1_ADDR 0x464
|
|
#define CHN3_TX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN3_TX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN3_TX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN3_TX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN3_TX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN3_TX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN3_TX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN3_TX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN3_TX_OWNER_FLAG_ENA_OFFSET 5
|
|
#define CHN3_TX_OWNER_FLAG_ENA_MASK 0x00000020
|
|
#define CHN3_TX_STOP_OFFSET 4
|
|
#define CHN3_TX_STOP_MASK 0x00000010
|
|
#define CHN3_TX_RESTART_OFFSET 3
|
|
#define CHN3_TX_RESTART_MASK 0x00000008
|
|
#define CHN3_TX_START_OFFSET 2
|
|
#define CHN3_TX_START_MASK 0x00000004
|
|
#define CHN3_TX_PRIORITY_OFFSET 0
|
|
#define CHN3_TX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN3_INTR_RAW_ADDR 0x468
|
|
#define CHN3_TX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 2
|
|
#define CHN3_TX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000004
|
|
#define CHN3_TX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN3_TX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN3_TX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN3_TX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN3_INTR_ST_ADDR 0x46C
|
|
#define CHN3_TX_OWNER_IS_NOT_HW_INT_ST_OFFSET 2
|
|
#define CHN3_TX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000004
|
|
#define CHN3_TX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN3_TX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN3_TX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN3_TX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN3_INTR_ENA_ADDR 0x470
|
|
#define CHN3_TX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 2
|
|
#define CHN3_TX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000004
|
|
#define CHN3_TX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN3_TX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN3_TX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN3_TX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN3_INTR_CLR_ADDR 0x474
|
|
#define CHN3_TX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 2
|
|
#define CHN3_TX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000004
|
|
#define CHN3_TX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN3_TX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN3_TX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN3_TX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN4_CFG0_ADDR 0x480
|
|
#define CHN4_TX_LINK_ADDR_OFFSET 0
|
|
#define CHN4_TX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN4_CFG1_ADDR 0x484
|
|
#define CHN4_TX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN4_TX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN4_TX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN4_TX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN4_TX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN4_TX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN4_TX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN4_TX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN4_TX_OWNER_FLAG_ENA_OFFSET 5
|
|
#define CHN4_TX_OWNER_FLAG_ENA_MASK 0x00000020
|
|
#define CHN4_TX_STOP_OFFSET 4
|
|
#define CHN4_TX_STOP_MASK 0x00000010
|
|
#define CHN4_TX_RESTART_OFFSET 3
|
|
#define CHN4_TX_RESTART_MASK 0x00000008
|
|
#define CHN4_TX_START_OFFSET 2
|
|
#define CHN4_TX_START_MASK 0x00000004
|
|
#define CHN4_TX_PRIORITY_OFFSET 0
|
|
#define CHN4_TX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN4_INTR_RAW_ADDR 0x488
|
|
#define CHN4_TX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 2
|
|
#define CHN4_TX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000004
|
|
#define CHN4_TX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN4_TX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN4_TX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN4_TX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN4_INTR_ST_ADDR 0x48C
|
|
#define CHN4_TX_OWNER_IS_NOT_HW_INT_ST_OFFSET 2
|
|
#define CHN4_TX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000004
|
|
#define CHN4_TX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN4_TX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN4_TX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN4_TX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN4_INTR_ENA_ADDR 0x490
|
|
#define CHN4_TX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 2
|
|
#define CHN4_TX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000004
|
|
#define CHN4_TX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN4_TX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN4_TX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN4_TX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN4_INTR_CLR_ADDR 0x494
|
|
#define CHN4_TX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 2
|
|
#define CHN4_TX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000004
|
|
#define CHN4_TX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN4_TX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN4_TX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN4_TX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN5_CFG0_ADDR 0x4A0
|
|
#define CHN5_TX_LINK_ADDR_OFFSET 0
|
|
#define CHN5_TX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN5_CFG1_ADDR 0x4A4
|
|
#define CHN5_TX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN5_TX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN5_TX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN5_TX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN5_TX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN5_TX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN5_TX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN5_TX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN5_TX_OWNER_FLAG_ENA_OFFSET 5
|
|
#define CHN5_TX_OWNER_FLAG_ENA_MASK 0x00000020
|
|
#define CHN5_TX_STOP_OFFSET 4
|
|
#define CHN5_TX_STOP_MASK 0x00000010
|
|
#define CHN5_TX_RESTART_OFFSET 3
|
|
#define CHN5_TX_RESTART_MASK 0x00000008
|
|
#define CHN5_TX_START_OFFSET 2
|
|
#define CHN5_TX_START_MASK 0x00000004
|
|
#define CHN5_TX_PRIORITY_OFFSET 0
|
|
#define CHN5_TX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN5_INTR_RAW_ADDR 0x4A8
|
|
#define CHN5_TX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 2
|
|
#define CHN5_TX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000004
|
|
#define CHN5_TX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN5_TX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN5_TX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN5_TX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN5_INTR_ST_ADDR 0x4AC
|
|
#define CHN5_TX_OWNER_IS_NOT_HW_INT_ST_OFFSET 2
|
|
#define CHN5_TX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000004
|
|
#define CHN5_TX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN5_TX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN5_TX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN5_TX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN5_INTR_ENA_ADDR 0x4B0
|
|
#define CHN5_TX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 2
|
|
#define CHN5_TX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000004
|
|
#define CHN5_TX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN5_TX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN5_TX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN5_TX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN5_INTR_CLR_ADDR 0x4B4
|
|
#define CHN5_TX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 2
|
|
#define CHN5_TX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000004
|
|
#define CHN5_TX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN5_TX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN5_TX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN5_TX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN6_CFG0_ADDR 0x4C0
|
|
#define CHN6_TX_LINK_ADDR_OFFSET 0
|
|
#define CHN6_TX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN6_CFG1_ADDR 0x4C4
|
|
#define CHN6_TX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN6_TX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN6_TX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN6_TX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN6_TX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN6_TX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN6_TX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN6_TX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN6_TX_OWNER_FLAG_ENA_OFFSET 5
|
|
#define CHN6_TX_OWNER_FLAG_ENA_MASK 0x00000020
|
|
#define CHN6_TX_STOP_OFFSET 4
|
|
#define CHN6_TX_STOP_MASK 0x00000010
|
|
#define CHN6_TX_RESTART_OFFSET 3
|
|
#define CHN6_TX_RESTART_MASK 0x00000008
|
|
#define CHN6_TX_START_OFFSET 2
|
|
#define CHN6_TX_START_MASK 0x00000004
|
|
#define CHN6_TX_PRIORITY_OFFSET 0
|
|
#define CHN6_TX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN6_INTR_RAW_ADDR 0x4C8
|
|
#define CHN6_TX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 2
|
|
#define CHN6_TX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000004
|
|
#define CHN6_TX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN6_TX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN6_TX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN6_TX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN6_INTR_ST_ADDR 0x4CC
|
|
#define CHN6_TX_OWNER_IS_NOT_HW_INT_ST_OFFSET 2
|
|
#define CHN6_TX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000004
|
|
#define CHN6_TX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN6_TX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN6_TX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN6_TX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN6_INTR_ENA_ADDR 0x4D0
|
|
#define CHN6_TX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 2
|
|
#define CHN6_TX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000004
|
|
#define CHN6_TX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN6_TX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN6_TX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN6_TX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN6_INTR_CLR_ADDR 0x4D4
|
|
#define CHN6_TX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 2
|
|
#define CHN6_TX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000004
|
|
#define CHN6_TX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN6_TX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN6_TX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN6_TX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN7_CFG0_ADDR 0x4E0
|
|
#define CHN7_TX_LINK_ADDR_OFFSET 0
|
|
#define CHN7_TX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN7_CFG1_ADDR 0x4E4
|
|
#define CHN7_TX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN7_TX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN7_TX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN7_TX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN7_TX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN7_TX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN7_TX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN7_TX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN7_TX_OWNER_FLAG_ENA_OFFSET 5
|
|
#define CHN7_TX_OWNER_FLAG_ENA_MASK 0x00000020
|
|
#define CHN7_TX_STOP_OFFSET 4
|
|
#define CHN7_TX_STOP_MASK 0x00000010
|
|
#define CHN7_TX_RESTART_OFFSET 3
|
|
#define CHN7_TX_RESTART_MASK 0x00000008
|
|
#define CHN7_TX_START_OFFSET 2
|
|
#define CHN7_TX_START_MASK 0x00000004
|
|
#define CHN7_TX_PRIORITY_OFFSET 0
|
|
#define CHN7_TX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN7_INTR_RAW_ADDR 0x4E8
|
|
#define CHN7_TX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 2
|
|
#define CHN7_TX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000004
|
|
#define CHN7_TX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN7_TX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN7_TX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN7_TX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN7_INTR_ST_ADDR 0x4EC
|
|
#define CHN7_TX_OWNER_IS_NOT_HW_INT_ST_OFFSET 2
|
|
#define CHN7_TX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000004
|
|
#define CHN7_TX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN7_TX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN7_TX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN7_TX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN7_INTR_ENA_ADDR 0x4F0
|
|
#define CHN7_TX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 2
|
|
#define CHN7_TX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000004
|
|
#define CHN7_TX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN7_TX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN7_TX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN7_TX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN7_INTR_CLR_ADDR 0x4F4
|
|
#define CHN7_TX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 2
|
|
#define CHN7_TX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000004
|
|
#define CHN7_TX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN7_TX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN7_TX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN7_TX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN8_CFG0_ADDR 0x500
|
|
#define CHN8_TX_LINK_ADDR_OFFSET 0
|
|
#define CHN8_TX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN8_CFG1_ADDR 0x504
|
|
#define CHN8_TX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN8_TX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN8_TX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN8_TX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN8_TX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN8_TX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN8_TX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN8_TX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN8_TX_OWNER_FLAG_ENA_OFFSET 5
|
|
#define CHN8_TX_OWNER_FLAG_ENA_MASK 0x00000020
|
|
#define CHN8_TX_STOP_OFFSET 4
|
|
#define CHN8_TX_STOP_MASK 0x00000010
|
|
#define CHN8_TX_RESTART_OFFSET 3
|
|
#define CHN8_TX_RESTART_MASK 0x00000008
|
|
#define CHN8_TX_START_OFFSET 2
|
|
#define CHN8_TX_START_MASK 0x00000004
|
|
#define CHN8_TX_PRIORITY_OFFSET 0
|
|
#define CHN8_TX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN8_INTR_RAW_ADDR 0x508
|
|
#define CHN8_TX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 2
|
|
#define CHN8_TX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000004
|
|
#define CHN8_TX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN8_TX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN8_TX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN8_TX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN8_INTR_ST_ADDR 0x50C
|
|
#define CHN8_TX_OWNER_IS_NOT_HW_INT_ST_OFFSET 2
|
|
#define CHN8_TX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000004
|
|
#define CHN8_TX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN8_TX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN8_TX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN8_TX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN8_INTR_ENA_ADDR 0x510
|
|
#define CHN8_TX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 2
|
|
#define CHN8_TX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000004
|
|
#define CHN8_TX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN8_TX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN8_TX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN8_TX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN8_INTR_CLR_ADDR 0x514
|
|
#define CHN8_TX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 2
|
|
#define CHN8_TX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000004
|
|
#define CHN8_TX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN8_TX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN8_TX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN8_TX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN9_CFG0_ADDR 0x520
|
|
#define CHN9_TX_LINK_ADDR_OFFSET 0
|
|
#define CHN9_TX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN9_CFG1_ADDR 0x524
|
|
#define CHN9_TX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN9_TX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN9_TX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN9_TX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN9_TX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN9_TX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN9_TX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN9_TX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN9_TX_OWNER_FLAG_ENA_OFFSET 5
|
|
#define CHN9_TX_OWNER_FLAG_ENA_MASK 0x00000020
|
|
#define CHN9_TX_STOP_OFFSET 4
|
|
#define CHN9_TX_STOP_MASK 0x00000010
|
|
#define CHN9_TX_RESTART_OFFSET 3
|
|
#define CHN9_TX_RESTART_MASK 0x00000008
|
|
#define CHN9_TX_START_OFFSET 2
|
|
#define CHN9_TX_START_MASK 0x00000004
|
|
#define CHN9_TX_PRIORITY_OFFSET 0
|
|
#define CHN9_TX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN9_INTR_RAW_ADDR 0x528
|
|
#define CHN9_TX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 2
|
|
#define CHN9_TX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000004
|
|
#define CHN9_TX_ALL_DECR_INT_RAW_OFFSET 1
|
|
#define CHN9_TX_ALL_DECR_INT_RAW_MASK 0x00000002
|
|
#define CHN9_TX_CURR_DECR_INT_RAW_OFFSET 0
|
|
#define CHN9_TX_CURR_DECR_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN9_INTR_ST_ADDR 0x52C
|
|
#define CHN9_TX_OWNER_IS_NOT_HW_INT_ST_OFFSET 2
|
|
#define CHN9_TX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000004
|
|
#define CHN9_TX_ALL_DECR_INT_ST_OFFSET 1
|
|
#define CHN9_TX_ALL_DECR_INT_ST_MASK 0x00000002
|
|
#define CHN9_TX_CURR_DECR_INT_ST_OFFSET 0
|
|
#define CHN9_TX_CURR_DECR_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN9_INTR_ENA_ADDR 0x530
|
|
#define CHN9_TX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 2
|
|
#define CHN9_TX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000004
|
|
#define CHN9_TX_ALL_DECR_INT_ENA_OFFSET 1
|
|
#define CHN9_TX_ALL_DECR_INT_ENA_MASK 0x00000002
|
|
#define CHN9_TX_CURR_DECR_INT_ENA_OFFSET 0
|
|
#define CHN9_TX_CURR_DECR_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN9_INTR_CLR_ADDR 0x534
|
|
#define CHN9_TX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 2
|
|
#define CHN9_TX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000004
|
|
#define CHN9_TX_ALL_DECR_INT_CLR_OFFSET 1
|
|
#define CHN9_TX_ALL_DECR_INT_CLR_MASK 0x00000002
|
|
#define CHN9_TX_CURR_DECR_INT_CLR_OFFSET 0
|
|
#define CHN9_TX_CURR_DECR_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN10_CFG0_ADDR 0x540
|
|
#define CHN10_TX_LINK_ADDR_OFFSET 0
|
|
#define CHN10_TX_LINK_ADDR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN10_CFG1_ADDR 0x544
|
|
#define CHN10_TX_OUT_BIT_ORDER_SEL_OFFSET 23
|
|
#define CHN10_TX_OUT_BIT_ORDER_SEL_MASK 0x00800000
|
|
#define CHN10_TX_OUT_BYTE_ORDER_SEL_OFFSET 22
|
|
#define CHN10_TX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
|
|
#define CHN10_TX_IN_BIT_ORDER_SEL_OFFSET 21
|
|
#define CHN10_TX_IN_BIT_ORDER_SEL_MASK 0x00200000
|
|
#define CHN10_TX_IN_BYTE_ORDER_SEL_OFFSET 20
|
|
#define CHN10_TX_IN_BYTE_ORDER_SEL_MASK 0x00100000
|
|
#define CHN10_TX_OWNER_FLAG_ENA_OFFSET 5
|
|
#define CHN10_TX_OWNER_FLAG_ENA_MASK 0x00000020
|
|
#define CHN10_TX_STOP_OFFSET 4
|
|
#define CHN10_TX_STOP_MASK 0x00000010
|
|
#define CHN10_TX_RESTART_OFFSET 3
|
|
#define CHN10_TX_RESTART_MASK 0x00000008
|
|
#define CHN10_TX_START_OFFSET 2
|
|
#define CHN10_TX_START_MASK 0x00000004
|
|
#define CHN10_TX_PRIORITY_OFFSET 0
|
|
#define CHN10_TX_PRIORITY_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_DMA_HW_TX_CHN10_INTR_RAW_ADDR 0x548
|
|
#define CHN10_TX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 2
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#define CHN10_TX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000004
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#define CHN10_TX_ALL_DECR_INT_RAW_OFFSET 1
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#define CHN10_TX_ALL_DECR_INT_RAW_MASK 0x00000002
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#define CHN10_TX_CURR_DECR_INT_RAW_OFFSET 0
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#define CHN10_TX_CURR_DECR_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_TX_CHN10_INTR_ST_ADDR 0x54C
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#define CHN10_TX_OWNER_IS_NOT_HW_INT_ST_OFFSET 2
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#define CHN10_TX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000004
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#define CHN10_TX_ALL_DECR_INT_ST_OFFSET 1
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#define CHN10_TX_ALL_DECR_INT_ST_MASK 0x00000002
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#define CHN10_TX_CURR_DECR_INT_ST_OFFSET 0
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#define CHN10_TX_CURR_DECR_INT_ST_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_TX_CHN10_INTR_ENA_ADDR 0x550
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#define CHN10_TX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 2
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#define CHN10_TX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000004
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#define CHN10_TX_ALL_DECR_INT_ENA_OFFSET 1
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#define CHN10_TX_ALL_DECR_INT_ENA_MASK 0x00000002
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#define CHN10_TX_CURR_DECR_INT_ENA_OFFSET 0
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#define CHN10_TX_CURR_DECR_INT_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_TX_CHN10_INTR_CLR_ADDR 0x554
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#define CHN10_TX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 2
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#define CHN10_TX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000004
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#define CHN10_TX_ALL_DECR_INT_CLR_OFFSET 1
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#define CHN10_TX_ALL_DECR_INT_CLR_MASK 0x00000002
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#define CHN10_TX_CURR_DECR_INT_CLR_OFFSET 0
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#define CHN10_TX_CURR_DECR_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_TX_CHN11_CFG0_ADDR 0x560
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#define CHN11_TX_LINK_ADDR_OFFSET 0
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#define CHN11_TX_LINK_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMA_HW_TX_CHN11_CFG1_ADDR 0x564
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#define CHN11_TX_OUT_BIT_ORDER_SEL_OFFSET 23
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#define CHN11_TX_OUT_BIT_ORDER_SEL_MASK 0x00800000
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#define CHN11_TX_OUT_BYTE_ORDER_SEL_OFFSET 22
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#define CHN11_TX_OUT_BYTE_ORDER_SEL_MASK 0x00400000
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#define CHN11_TX_IN_BIT_ORDER_SEL_OFFSET 21
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#define CHN11_TX_IN_BIT_ORDER_SEL_MASK 0x00200000
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#define CHN11_TX_IN_BYTE_ORDER_SEL_OFFSET 20
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#define CHN11_TX_IN_BYTE_ORDER_SEL_MASK 0x00100000
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#define CHN11_TX_OWNER_FLAG_ENA_OFFSET 5
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#define CHN11_TX_OWNER_FLAG_ENA_MASK 0x00000020
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#define CHN11_TX_STOP_OFFSET 4
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#define CHN11_TX_STOP_MASK 0x00000010
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#define CHN11_TX_RESTART_OFFSET 3
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#define CHN11_TX_RESTART_MASK 0x00000008
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#define CHN11_TX_START_OFFSET 2
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#define CHN11_TX_START_MASK 0x00000004
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#define CHN11_TX_PRIORITY_OFFSET 0
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#define CHN11_TX_PRIORITY_MASK 0x00000003
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//-----------------------------------
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#define CFG_DMA_HW_TX_CHN11_INTR_RAW_ADDR 0x568
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#define CHN11_TX_OWNER_IS_NOT_HW_INT_RAW_OFFSET 2
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#define CHN11_TX_OWNER_IS_NOT_HW_INT_RAW_MASK 0x00000004
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#define CHN11_TX_ALL_DECR_INT_RAW_OFFSET 1
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#define CHN11_TX_ALL_DECR_INT_RAW_MASK 0x00000002
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#define CHN11_TX_CURR_DECR_INT_RAW_OFFSET 0
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#define CHN11_TX_CURR_DECR_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_TX_CHN11_INTR_ST_ADDR 0x56C
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#define CHN11_TX_OWNER_IS_NOT_HW_INT_ST_OFFSET 2
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#define CHN11_TX_OWNER_IS_NOT_HW_INT_ST_MASK 0x00000004
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#define CHN11_TX_ALL_DECR_INT_ST_OFFSET 1
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#define CHN11_TX_ALL_DECR_INT_ST_MASK 0x00000002
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#define CHN11_TX_CURR_DECR_INT_ST_OFFSET 0
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#define CHN11_TX_CURR_DECR_INT_ST_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_TX_CHN11_INTR_ENA_ADDR 0x570
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#define CHN11_TX_OWNER_IS_NOT_HW_INT_ENA_OFFSET 2
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#define CHN11_TX_OWNER_IS_NOT_HW_INT_ENA_MASK 0x00000004
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#define CHN11_TX_ALL_DECR_INT_ENA_OFFSET 1
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#define CHN11_TX_ALL_DECR_INT_ENA_MASK 0x00000002
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#define CHN11_TX_CURR_DECR_INT_ENA_OFFSET 0
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#define CHN11_TX_CURR_DECR_INT_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_HW_TX_CHN11_INTR_CLR_ADDR 0x574
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#define CHN11_TX_OWNER_IS_NOT_HW_INT_CLR_OFFSET 2
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#define CHN11_TX_OWNER_IS_NOT_HW_INT_CLR_MASK 0x00000004
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#define CHN11_TX_ALL_DECR_INT_CLR_OFFSET 1
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#define CHN11_TX_ALL_DECR_INT_CLR_MASK 0x00000002
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#define CHN11_TX_CURR_DECR_INT_CLR_OFFSET 0
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#define CHN11_TX_CURR_DECR_INT_CLR_MASK 0x00000001
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//HW module read/write macro
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#define DMA_HW_RF_READ_REG(addr) SOC_READ_REG(DMA_HW_RF_BASEADDR + addr)
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#define DMA_HW_RF_WRITE_REG(addr,value) SOC_WRITE_REG(DMA_HW_RF_BASEADDR + addr,value)
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