383 lines
13 KiB
C
Executable File
383 lines
13 KiB
C
Executable File
|
|
//-----------------------------------
|
|
#define CFG_BB_RATE0_DET_BAND_ADDR 0x0000
|
|
#define SW_RATE0_DET_END_TONE_OFFSET 16
|
|
#define SW_RATE0_DET_END_TONE_MASK 0x07FF0000
|
|
#define SW_RATE0_DET_START_TONE_OFFSET 0
|
|
#define SW_RATE0_DET_START_TONE_MASK 0x000007FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RATE1_DET_BAND_ADDR 0x0004
|
|
#define SW_RATE1_DET_END_TONE_OFFSET 16
|
|
#define SW_RATE1_DET_END_TONE_MASK 0x07FF0000
|
|
#define SW_RATE1_DET_START_TONE_OFFSET 0
|
|
#define SW_RATE1_DET_START_TONE_MASK 0x000007FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RATE_OFFET_ADDR 0x0008
|
|
#define SW_CSI_RATE1_OFFSET_OFFSET 0
|
|
#define SW_CSI_RATE1_OFFSET_MASK 0x000007FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PKT_DET_ADDR 0x000C
|
|
#define SW_FIND_PKT_DIS_OFFSET 31
|
|
#define SW_FIND_PKT_DIS_MASK 0x80000000
|
|
#define SW_SYMB_SYNC_OFFSET_OFFSET 19
|
|
#define SW_SYMB_SYNC_OFFSET_MASK 0x1FF80000
|
|
#define SW_SYMB_DET_ALPHA_OFFSET 16
|
|
#define SW_SYMB_DET_ALPHA_MASK 0x00070000
|
|
#define SW_SYMB_DET_THR1_OFFSET 10
|
|
#define SW_SYMB_DET_THR1_MASK 0x0000FC00
|
|
#define SW_SYMB_DET_THR0_NUM_OFFSET 6
|
|
#define SW_SYMB_DET_THR0_NUM_MASK 0x000001C0
|
|
#define SW_SYMB_DET_THR0_OFFSET 0
|
|
#define SW_SYMB_DET_THR0_MASK 0x0000003F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FRAME_SYNC_ADDR 0x0010
|
|
#define SW_2SYNCM_EN_OFFSET 17
|
|
#define SW_2SYNCM_EN_MASK 0x00020000
|
|
#define SW_SYNC_SYMB_ACC_EN_OFFSET 16
|
|
#define SW_SYNC_SYMB_ACC_EN_MASK 0x00010000
|
|
#define SW_CSI_SYMB_CNTR_OFFSET 6
|
|
#define SW_CSI_SYMB_CNTR_MASK 0x000003C0
|
|
#define SW_FRAME_SYNC_THR_OFFSET 0
|
|
#define SW_FRAME_SYNC_THR_MASK 0x0000003F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CH_EST_SPUR_ADDR 0x0014
|
|
#define SW_CH_EST_MAX_SPUR_OFFSET 12
|
|
#define SW_CH_EST_MAX_SPUR_MASK 0x007FF000
|
|
#define SW_CH_EST_SPUR_THR_OFFSET 4
|
|
#define SW_CH_EST_SPUR_THR_MASK 0x000003F0
|
|
#define SW_CH_EST_SPUR_LEN_OFFSET 2
|
|
#define SW_CH_EST_SPUR_LEN_MASK 0x0000000C
|
|
#define SW_CH_EST_SPUR_MASK_EN_OFFSET 1
|
|
#define SW_CH_EST_SPUR_MASK_EN_MASK 0x00000002
|
|
#define SW_CH_EST_SPUR_EN_OFFSET 0
|
|
#define SW_CH_EST_SPUR_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_WIENER_FILTER0_ADDR 0x0018
|
|
#define SW_WIENER_FILTER_EN_OFFSET 16
|
|
#define SW_WIENER_FILTER_EN_MASK 0x00010000
|
|
#define SW_FILTER0_RANGE_OFFSET 0
|
|
#define SW_FILTER0_RANGE_MASK 0x0000007F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_WIENER_FILTER1_ADDR 0x001C
|
|
#define SW_FILTER1_RANGE_OFFSET 0
|
|
#define SW_FILTER1_RANGE_MASK 0x0000007F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_WIENER_FILTER2_ADDR 0x0020
|
|
#define SW_FILTER2_RANGE_OFFSET 0
|
|
#define SW_FILTER2_RANGE_MASK 0x0000007F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_WIENER_FILTER3_ADDR 0x0024
|
|
#define SW_FILTER3_RANGE_OFFSET 0
|
|
#define SW_FILTER3_RANGE_MASK 0x0000007F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_WIENER_FILTER4_ADDR 0x0028
|
|
#define SW_FILTER4_RANGE_OFFSET 0
|
|
#define SW_FILTER4_RANGE_MASK 0x0000007F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TURBO_CTRL_ADDR 0x002C
|
|
#define SW_TURBO_DEC_FC_MIN_ITER_OFFSET 19
|
|
#define SW_TURBO_DEC_FC_MIN_ITER_MASK 0x00F80000
|
|
#define SW_TURBO_DEC_FC_MAX_ITER_OFFSET 14
|
|
#define SW_TURBO_DEC_FC_MAX_ITER_MASK 0x0007C000
|
|
#define SW_TURBO_DEC_PB_MIN_ITER_OFFSET 9
|
|
#define SW_TURBO_DEC_PB_MIN_ITER_MASK 0x00003E00
|
|
#define SW_TURBO_DEC_PB_MAX_ITER_OFFSET 4
|
|
#define SW_TURBO_DEC_PB_MAX_ITER_MASK 0x000001F0
|
|
#define SW_SCRAMBLE_PB_EN_OFFSET 3
|
|
#define SW_SCRAMBLE_PB_EN_MASK 0x00000008
|
|
#define SW_TURBO_DEC_CRC_EN_OFFSET 2
|
|
#define SW_TURBO_DEC_CRC_EN_MASK 0x00000004
|
|
#define SW_SCRAMBLE_RESET_MODE_OFFSET 1
|
|
#define SW_SCRAMBLE_RESET_MODE_MASK 0x00000002
|
|
#define SW_SCRAMBLE_MODE_OFFSET 0
|
|
#define SW_SCRAMBLE_MODE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_SNR_ADDR 0x0030
|
|
#define SW_SNR_DUMP_ALWAYS_EN_OFFSET 28
|
|
#define SW_SNR_DUMP_ALWAYS_EN_MASK 0x10000000
|
|
#define SW_SNR_DUMP_START_TONE_OFFSET 16
|
|
#define SW_SNR_DUMP_START_TONE_MASK 0x07FF0000
|
|
#define SW_DUMP_DATA_SHIFT_OFFSET 8
|
|
#define SW_DUMP_DATA_SHIFT_MASK 0x00001F00
|
|
#define SW_DUMP_RAW_PWR_EN_OFFSET 5
|
|
#define SW_DUMP_RAW_PWR_EN_MASK 0x00000020
|
|
#define SW_SNR_DUMP_MODE_OFFSET 2
|
|
#define SW_SNR_DUMP_MODE_MASK 0x0000001C
|
|
#define SW_SNR_DUMP_DONE_OFFSET 1
|
|
#define SW_SNR_DUMP_DONE_MASK 0x00000002
|
|
#define SW_SNR_DUMP_EN_OFFSET 0
|
|
#define SW_SNR_DUMP_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FREQ_ERROR_ADDR 0x0034
|
|
#define SW_FREQ_ERROR_PPM_OFFSET 18
|
|
#define SW_FREQ_ERROR_PPM_MASK 0x0FFC0000
|
|
#define SW_FREQ_ERROR_MAX_OFFSET 9
|
|
#define SW_FREQ_ERROR_MAX_MASK 0x0003FE00
|
|
#define SW_KALMAN_BETA_OFFSET 6
|
|
#define SW_KALMAN_BETA_MASK 0x000001C0
|
|
#define SW_KALMAN_ALPHA_OFFSET 3
|
|
#define SW_KALMAN_ALPHA_MASK 0x00000038
|
|
#define SW_TRACKING_EN_OFFSET 2
|
|
#define SW_TRACKING_EN_MASK 0x00000004
|
|
#define SW_FD_COMP_EN_OFFSET 1
|
|
#define SW_FD_COMP_EN_MASK 0x00000002
|
|
#define SW_TD_COMP_EN_OFFSET 0
|
|
#define SW_TD_COMP_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FC_SOFT_ERROR_CNT_ADDR 0x0040
|
|
#define SW_FC_SOFT_BIT_ERROR_CNTR_OFFSET 0
|
|
#define SW_FC_SOFT_BIT_ERROR_CNTR_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PLD_SOFT_ERROR_CNT_ADDR 0x0044
|
|
#define SW_PLD_SOFT_BIT_ERROR_CNTR_OFFSET 0
|
|
#define SW_PLD_SOFT_BIT_ERROR_CNTR_MASK 0x000FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TURBO_DEC_FC_INFO_ADDR 0x0048
|
|
#define FC_TURBO_FAIL_CNTR_OFFSET 16
|
|
#define FC_TURBO_FAIL_CNTR_MASK 0x001F0000
|
|
#define FC_TURBO_DEC_ERROR_CNTR_OFFSET 0
|
|
#define FC_TURBO_DEC_ERROR_CNTR_MASK 0x00001FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TURBO_DEC_PB_INFO_ADDR 0x004C
|
|
#define PLD_TURBO_FAIL_CNTR_OFFSET 24
|
|
#define PLD_TURBO_FAIL_CNTR_MASK 0xFF000000
|
|
#define PLD_TURBO_DEC_ERROR_CNTR_OFFSET 0
|
|
#define PLD_TURBO_DEC_ERROR_CNTR_MASK 0x00FFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FC101_ADDR 0x0050
|
|
#define SW_ALWAYS_FC101_EN_OFFSET 8
|
|
#define SW_ALWAYS_FC101_EN_MASK 0x00000100
|
|
#define SW_FC101_THR_OFFSET 1
|
|
#define SW_FC101_THR_MASK 0x0000007E
|
|
#define SW_FC101_EN_OFFSET 0
|
|
#define SW_FC101_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_DECISION_FEEDBACK_ADDR 0x0054
|
|
#define SW_DCFB_ALPHA_OFFSET 1
|
|
#define SW_DCFB_ALPHA_MASK 0x0000001E
|
|
#define SW_DCFB_EN_OFFSET 0
|
|
#define SW_DCFB_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TURBO_STOP_ADDR 0x0058
|
|
#define SW_TURBO_STOP_TIME_OFFSET 0
|
|
#define SW_TURBO_STOP_TIME_MASK 0x000FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_SEND_MAC_CTRL_ADDR 0x005C
|
|
#define SW_FC_CRC_ERR_CTRL_OFFSET 2
|
|
#define SW_FC_CRC_ERR_CTRL_MASK 0x00000004
|
|
#define SW_ALWAYS_SEND_FC_OFFSET 1
|
|
#define SW_ALWAYS_SEND_FC_MASK 0x00000002
|
|
#define SW_ALWAYS_SEND_PB_OFFSET 0
|
|
#define SW_ALWAYS_SEND_PB_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_SOFT_BIT_GEN_ADDR 0x0060
|
|
#define SW_SOFT_BIT_SIGN_RESERVE_OFFSET 16
|
|
#define SW_SOFT_BIT_SIGN_RESERVE_MASK 0x00010000
|
|
#define SW_SOFT_BIT_SHIFT3_OFFSET 12
|
|
#define SW_SOFT_BIT_SHIFT3_MASK 0x0000F000
|
|
#define SW_SOFT_BIT_SHIFT2_OFFSET 8
|
|
#define SW_SOFT_BIT_SHIFT2_MASK 0x00000F00
|
|
#define SW_SOFT_BIT_SHIFT1_OFFSET 4
|
|
#define SW_SOFT_BIT_SHIFT1_MASK 0x000000F0
|
|
#define SW_SOFT_BIT_SHIFT0_OFFSET 0
|
|
#define SW_SOFT_BIT_SHIFT0_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_AVE_SNR_ADDR 0x0064
|
|
#define CH_EQU_AVE_SNR_LOG2_OFFSET 16
|
|
#define CH_EQU_AVE_SNR_LOG2_MASK 0x03FF0000
|
|
#define CH_EST_AVE_SNR_LOG2_OFFSET 4
|
|
#define CH_EST_AVE_SNR_LOG2_MASK 0x00003FF0
|
|
#define SW_AVE_SNR_SEL_OFFSET 0
|
|
#define SW_AVE_SNR_SEL_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PHY_INFO_ADDR 0x0068
|
|
#define SW_PHY_INFO_WORD_NUM_OFFSET 4
|
|
#define SW_PHY_INFO_WORD_NUM_MASK 0x000000F0
|
|
#define SW_PHY_INFO_MUX_OFFSET 0
|
|
#define SW_PHY_INFO_MUX_MASK 0x00000007
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_MC_PER_SUBC_ADDR 0x006C
|
|
#define SW_MC_PER_SUBC_EN_OFFSET 0
|
|
#define SW_MC_PER_SUBC_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RX_PB_NUM_CTRL_ADDR 0x0070
|
|
#define SW_RXFD_OVERWRITE_PBNUM_EN_OFFSET 0
|
|
#define SW_RXFD_OVERWRITE_PBNUM_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RX_G3_CTRL_ADDR 0x0074
|
|
#define SW_DISABLE_DEFEC_EN_OFFSET 1
|
|
#define SW_DISABLE_DEFEC_EN_MASK 0x00000002
|
|
#define SW_DISABLE_TURBO_EN_OFFSET 0
|
|
#define SW_DISABLE_TURBO_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_SYMB_OFFSET_ADDR 0x0078
|
|
#define CH_EST_SYMB_OFFSET_OFFSET 0
|
|
#define CH_EST_SYMB_OFFSET_MASK 0x00001FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FC_ALL0_ADDR 0x007C
|
|
#define SW_FC_ALL0_CRC_ERR_EN_OFFSET 17
|
|
#define SW_FC_ALL0_CRC_ERR_EN_MASK 0x00020000
|
|
#define SW_FC_ALL0_CNTR_CLR_OFFSET 16
|
|
#define SW_FC_ALL0_CNTR_CLR_MASK 0x00010000
|
|
#define SW_FC_ALL0_CNTR_OFFSET 0
|
|
#define SW_FC_ALL0_CNTR_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_DBG_CNTR_ADDR 0x0080
|
|
#define SW_TMAP_TIME_OUT_CNTR_CLR_OFFSET 31
|
|
#define SW_TMAP_TIME_OUT_CNTR_CLR_MASK 0x80000000
|
|
#define SW_TMAP_TIME_OUT_CNTR_OFFSET 16
|
|
#define SW_TMAP_TIME_OUT_CNTR_MASK 0x7FFF0000
|
|
#define SW_PARSE_TIME_OUT_CNTR_CLR_OFFSET 15
|
|
#define SW_PARSE_TIME_OUT_CNTR_CLR_MASK 0x00008000
|
|
#define SW_PARSE_TIME_OUT_CNTR_OFFSET 0
|
|
#define SW_PARSE_TIME_OUT_CNTR_MASK 0x00007FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_SOUND_DUMP_ADDR 0x0084
|
|
#define SW_SOUND_DUMP_DONE_OFFSET 31
|
|
#define SW_SOUND_DUMP_DONE_MASK 0x80000000
|
|
#define SW_MATCH_DTEI_OFFSET 8
|
|
#define SW_MATCH_DTEI_MASK 0x0000FF00
|
|
#define SW_MATCH_SNID_OFFSET 4
|
|
#define SW_MATCH_SNID_MASK 0x000000F0
|
|
#define SW_MATCH_DTEI_EN_OFFSET 1
|
|
#define SW_MATCH_DTEI_EN_MASK 0x00000002
|
|
#define SW_MATCH_SNID_EN_OFFSET 0
|
|
#define SW_MATCH_SNID_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_SOUND_FC_INFO_ADDR 0x0088
|
|
#define SW_STEI_OF_DS_OFFSET 12
|
|
#define SW_STEI_OF_DS_MASK 0x000FF000
|
|
#define SW_DTEI_OF_DS_OFFSET 4
|
|
#define SW_DTEI_OF_DS_MASK 0x00000FF0
|
|
#define SW_SNID_OF_DS_OFFSET 0
|
|
#define SW_SNID_OF_DS_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_SPUR_MASK_ADDR 0x008C
|
|
#define SW_NOTCH_SPUR_MASK_WIDTH_OFFSET 28
|
|
#define SW_NOTCH_SPUR_MASK_WIDTH_MASK 0xF0000000
|
|
#define SW_SPUR_CAL_THR_OFFSET 12
|
|
#define SW_SPUR_CAL_THR_MASK 0x0003F000
|
|
#define SW_SPUR_CAL_LEN_OFFSET 8
|
|
#define SW_SPUR_CAL_LEN_MASK 0x00000300
|
|
#define SW_PLD_SPUR_EN_OFFSET 4
|
|
#define SW_PLD_SPUR_EN_MASK 0x00000010
|
|
#define SW_FC_SPUR_EN_OFFSET 3
|
|
#define SW_FC_SPUR_EN_MASK 0x00000008
|
|
#define SW_FREQ_ERROR_SPUR_EN_OFFSET 2
|
|
#define SW_FREQ_ERROR_SPUR_EN_MASK 0x00000004
|
|
#define SW_FRAME_SYNC_SPUR_EN_OFFSET 1
|
|
#define SW_FRAME_SYNC_SPUR_EN_MASK 0x00000002
|
|
#define SW_SYMB_DET_SPUR_EN_OFFSET 0
|
|
#define SW_SYMB_DET_SPUR_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PRS_DET_ADDR 0x0090
|
|
#define SW_PRS_DET_THR1_OFFSET 12
|
|
#define SW_PRS_DET_THR1_MASK 0x0003F000
|
|
#define SW_PRS_DET_THR0_OFFSET 4
|
|
#define SW_PRS_DET_THR0_MASK 0x000003F0
|
|
#define SW_PRS_DET_THR0_NUM_OFFSET 1
|
|
#define SW_PRS_DET_THR0_NUM_MASK 0x0000000E
|
|
#define SW_PRS_DET_EN_OFFSET 0
|
|
#define SW_PRS_DET_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FD_OVERFLOW_ADDR 0x0094
|
|
#define SW_OVERFLOW_RST_EN_OFFSET 0
|
|
#define SW_OVERFLOW_RST_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TURBO_STOP_BST_ADDR 0x0098
|
|
#define SW_TURBO_STOP_TIME_BST_OFFSET 0
|
|
#define SW_TURBO_STOP_TIME_BST_MASK 0x000FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_SYMB_DET_PWR_ADDR 0x009C
|
|
#define SW_SYMB_DET_PWR_THR_OFFSET 0
|
|
#define SW_SYMB_DET_PWR_THR_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_DUMP_PHY_INFO0_ADDR 0x0100
|
|
#define SW_DUMP_PHY_INFO0_OFFSET 0
|
|
#define SW_DUMP_PHY_INFO0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_DUMP_PHY_INFO1_ADDR 0x0104
|
|
#define SW_DUMP_PHY_INFO1_OFFSET 0
|
|
#define SW_DUMP_PHY_INFO1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_SPUR_STAT_ADDR 0x0108
|
|
#define SW_SPUR_STAT_NUM_OFFSET 16
|
|
#define SW_SPUR_STAT_NUM_MASK 0xFFFF0000
|
|
#define SW_SPUR_STAT_DONE_OFFSET 2
|
|
#define SW_SPUR_STAT_DONE_MASK 0x00000004
|
|
#define SW_SPUR_STAT_STOP_OFFSET 1
|
|
#define SW_SPUR_STAT_STOP_MASK 0x00000002
|
|
#define SW_SPUR_STAT_START_OFFSET 0
|
|
#define SW_SPUR_STAT_START_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TIMEOUT_CTRL_ADDR 0x0108
|
|
#define SW_TMAP_TIMEOUT_SRST_EN_OFFSET 1
|
|
#define SW_TMAP_TIMEOUT_SRST_EN_MASK 0x00000002
|
|
#define SW_PARSE_TIMEOUT_SRST_EN_OFFSET 0
|
|
#define SW_PARSE_TIMEOUT_SRST_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RXFD_SPARE0_ADDR 0x0200
|
|
#define RXFD_SPARE0_OFFSET 0
|
|
#define RXFD_SPARE0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RXFD_SPARE1_ADDR 0x0204
|
|
#define RXFD_SPARE1_OFFSET 0
|
|
#define RXFD_SPARE1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RXFD_SPARE2_ADDR 0x0208
|
|
#define RXFD_SPARE2_OFFSET 0
|
|
#define RXFD_SPARE2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RXFD_SPARE3_ADDR 0x020C
|
|
#define RXFD_SPARE3_OFFSET 0
|
|
#define RXFD_SPARE3_MASK 0xFFFFFFFF
|
|
|
|
//HW module read/write macro
|
|
#define PHY_RX_FD_READ_REG(addr) SOC_READ_REG(PHY_RX_FD_BASEADDR + addr)
|
|
#define PHY_RX_FD_WRITE_REG(addr,value) SOC_WRITE_REG(PHY_RX_FD_BASEADDR + addr,value)
|