3039 lines
99 KiB
C
3039 lines
99 KiB
C
|
|
//-----------------------------------
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#define CFG_GPIO00_PIN_CFG_ADDR 0x4
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#define GPIO00_SEC_OFFSET 21
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#define GPIO00_SEC_MASK 0x00200000
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#define GPIO00_DRV_OFFSET 19
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#define GPIO00_DRV_MASK 0x00180000
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#define GPIO00_SLP_SEL_OFFSET 18
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#define GPIO00_SLP_SEL_MASK 0x00040000
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#define GPIO00_ODRV_OFFSET 17
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#define GPIO00_ODRV_MASK 0x00020000
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#define GPIO00_IINV_OFFSET 16
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#define GPIO00_IINV_MASK 0x00010000
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#define GPIO00_OINV_OFFSET 15
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#define GPIO00_OINV_MASK 0x00008000
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#define GPIO00_OPOS_OFFSET 14
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#define GPIO00_OPOS_MASK 0x00004000
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#define GPIO00_ONEG_OFFSET 13
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#define GPIO00_ONEG_MASK 0x00002000
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#define GPIO00_IPOS_OFFSET 12
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#define GPIO00_IPOS_MASK 0x00001000
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#define GPIO00_INEG_OFFSET 11
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#define GPIO00_INEG_MASK 0x00000800
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#define GPIO00_ORE_OFFSET 10
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#define GPIO00_ORE_MASK 0x00000400
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#define GPIO00_IRE_OFFSET 9
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#define GPIO00_IRE_MASK 0x00000200
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#define GPIO00_FUNC_WPU_OFFSET 8
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#define GPIO00_FUNC_WPU_MASK 0x00000100
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#define GPIO00_FUNC_WPD_OFFSET 7
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#define GPIO00_FUNC_WPD_MASK 0x00000080
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#define GPIO00_FUNC_SEL_OFFSET 4
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#define GPIO00_FUNC_SEL_MASK 0x00000070
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#define GPIO00_SLP_WPU_OFFSET 3
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#define GPIO00_SLP_WPU_MASK 0x00000008
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#define GPIO00_SLP_WPD_OFFSET 2
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#define GPIO00_SLP_WPD_MASK 0x00000004
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#define GPIO00_SLP_IE_OFFSET 1
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#define GPIO00_SLP_IE_MASK 0x00000002
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#define GPIO00_SLP_OE_OFFSET 0
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#define GPIO00_SLP_OE_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO01_PIN_CFG_ADDR 0x8
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#define GPIO01_SEC_OFFSET 21
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#define GPIO01_SEC_MASK 0x00200000
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#define GPIO01_DRV_OFFSET 19
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#define GPIO01_DRV_MASK 0x00180000
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#define GPIO01_SLP_SEL_OFFSET 18
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#define GPIO01_SLP_SEL_MASK 0x00040000
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#define GPIO01_ODRV_OFFSET 17
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#define GPIO01_ODRV_MASK 0x00020000
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#define GPIO01_IINV_OFFSET 16
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#define GPIO01_IINV_MASK 0x00010000
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#define GPIO01_OINV_OFFSET 15
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#define GPIO01_OINV_MASK 0x00008000
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#define GPIO01_OPOS_OFFSET 14
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#define GPIO01_OPOS_MASK 0x00004000
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#define GPIO01_ONEG_OFFSET 13
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#define GPIO01_ONEG_MASK 0x00002000
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#define GPIO01_IPOS_OFFSET 12
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#define GPIO01_IPOS_MASK 0x00001000
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#define GPIO01_INEG_OFFSET 11
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#define GPIO01_INEG_MASK 0x00000800
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#define GPIO01_ORE_OFFSET 10
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#define GPIO01_ORE_MASK 0x00000400
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#define GPIO01_IRE_OFFSET 9
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#define GPIO01_IRE_MASK 0x00000200
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#define GPIO01_FUNC_WPU_OFFSET 8
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#define GPIO01_FUNC_WPU_MASK 0x00000100
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#define GPIO01_FUNC_WPD_OFFSET 7
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#define GPIO01_FUNC_WPD_MASK 0x00000080
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#define GPIO01_FUNC_SEL_OFFSET 4
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#define GPIO01_FUNC_SEL_MASK 0x00000070
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#define GPIO01_SLP_WPU_OFFSET 3
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#define GPIO01_SLP_WPU_MASK 0x00000008
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#define GPIO01_SLP_WPD_OFFSET 2
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#define GPIO01_SLP_WPD_MASK 0x00000004
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#define GPIO01_SLP_IE_OFFSET 1
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#define GPIO01_SLP_IE_MASK 0x00000002
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#define GPIO01_SLP_OE_OFFSET 0
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#define GPIO01_SLP_OE_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO02_PIN_CFG_ADDR 0xc
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#define GPIO02_SEC_OFFSET 21
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#define GPIO02_SEC_MASK 0x00200000
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#define GPIO02_DRV_OFFSET 19
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#define GPIO02_DRV_MASK 0x00180000
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#define GPIO02_SLP_SEL_OFFSET 18
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#define GPIO02_SLP_SEL_MASK 0x00040000
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#define GPIO02_ODRV_OFFSET 17
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#define GPIO02_ODRV_MASK 0x00020000
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#define GPIO02_IINV_OFFSET 16
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#define GPIO02_IINV_MASK 0x00010000
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#define GPIO02_OINV_OFFSET 15
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#define GPIO02_OINV_MASK 0x00008000
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#define GPIO02_OPOS_OFFSET 14
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#define GPIO02_OPOS_MASK 0x00004000
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#define GPIO02_ONEG_OFFSET 13
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#define GPIO02_ONEG_MASK 0x00002000
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#define GPIO02_IPOS_OFFSET 12
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#define GPIO02_IPOS_MASK 0x00001000
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#define GPIO02_INEG_OFFSET 11
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#define GPIO02_INEG_MASK 0x00000800
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#define GPIO02_ORE_OFFSET 10
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#define GPIO02_ORE_MASK 0x00000400
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#define GPIO02_IRE_OFFSET 9
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#define GPIO02_IRE_MASK 0x00000200
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#define GPIO02_FUNC_WPU_OFFSET 8
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#define GPIO02_FUNC_WPU_MASK 0x00000100
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#define GPIO02_FUNC_WPD_OFFSET 7
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#define GPIO02_FUNC_WPD_MASK 0x00000080
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#define GPIO02_FUNC_SEL_OFFSET 4
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#define GPIO02_FUNC_SEL_MASK 0x00000070
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#define GPIO02_SLP_WPU_OFFSET 3
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#define GPIO02_SLP_WPU_MASK 0x00000008
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#define GPIO02_SLP_WPD_OFFSET 2
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#define GPIO02_SLP_WPD_MASK 0x00000004
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#define GPIO02_SLP_IE_OFFSET 1
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#define GPIO02_SLP_IE_MASK 0x00000002
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#define GPIO02_SLP_OE_OFFSET 0
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#define GPIO02_SLP_OE_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO03_PIN_CFG_ADDR 0x10
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#define GPIO03_SEC_OFFSET 21
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#define GPIO03_SEC_MASK 0x00200000
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#define GPIO03_DRV_OFFSET 19
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#define GPIO03_DRV_MASK 0x00180000
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#define GPIO03_SLP_SEL_OFFSET 18
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#define GPIO03_SLP_SEL_MASK 0x00040000
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#define GPIO03_ODRV_OFFSET 17
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#define GPIO03_ODRV_MASK 0x00020000
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#define GPIO03_IINV_OFFSET 16
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#define GPIO03_IINV_MASK 0x00010000
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#define GPIO03_OINV_OFFSET 15
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#define GPIO03_OINV_MASK 0x00008000
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#define GPIO03_OPOS_OFFSET 14
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#define GPIO03_OPOS_MASK 0x00004000
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#define GPIO03_ONEG_OFFSET 13
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#define GPIO03_ONEG_MASK 0x00002000
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#define GPIO03_IPOS_OFFSET 12
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#define GPIO03_IPOS_MASK 0x00001000
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#define GPIO03_INEG_OFFSET 11
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#define GPIO03_INEG_MASK 0x00000800
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#define GPIO03_ORE_OFFSET 10
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#define GPIO03_ORE_MASK 0x00000400
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#define GPIO03_IRE_OFFSET 9
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#define GPIO03_IRE_MASK 0x00000200
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#define GPIO03_FUNC_WPU_OFFSET 8
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#define GPIO03_FUNC_WPU_MASK 0x00000100
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#define GPIO03_FUNC_WPD_OFFSET 7
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#define GPIO03_FUNC_WPD_MASK 0x00000080
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#define GPIO03_FUNC_SEL_OFFSET 4
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#define GPIO03_FUNC_SEL_MASK 0x00000070
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#define GPIO03_SLP_WPU_OFFSET 3
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#define GPIO03_SLP_WPU_MASK 0x00000008
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#define GPIO03_SLP_WPD_OFFSET 2
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#define GPIO03_SLP_WPD_MASK 0x00000004
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#define GPIO03_SLP_IE_OFFSET 1
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#define GPIO03_SLP_IE_MASK 0x00000002
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#define GPIO03_SLP_OE_OFFSET 0
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#define GPIO03_SLP_OE_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO04_PIN_CFG_ADDR 0x14
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#define GPIO04_SEC_OFFSET 21
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#define GPIO04_SEC_MASK 0x00200000
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#define GPIO04_DRV_OFFSET 19
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#define GPIO04_DRV_MASK 0x00180000
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#define GPIO04_SLP_SEL_OFFSET 18
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#define GPIO04_SLP_SEL_MASK 0x00040000
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#define GPIO04_ODRV_OFFSET 17
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#define GPIO04_ODRV_MASK 0x00020000
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#define GPIO04_IINV_OFFSET 16
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#define GPIO04_IINV_MASK 0x00010000
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#define GPIO04_OINV_OFFSET 15
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#define GPIO04_OINV_MASK 0x00008000
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#define GPIO04_OPOS_OFFSET 14
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#define GPIO04_OPOS_MASK 0x00004000
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#define GPIO04_ONEG_OFFSET 13
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#define GPIO04_ONEG_MASK 0x00002000
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#define GPIO04_IPOS_OFFSET 12
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#define GPIO04_IPOS_MASK 0x00001000
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#define GPIO04_INEG_OFFSET 11
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#define GPIO04_INEG_MASK 0x00000800
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#define GPIO04_ORE_OFFSET 10
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#define GPIO04_ORE_MASK 0x00000400
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#define GPIO04_IRE_OFFSET 9
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#define GPIO04_IRE_MASK 0x00000200
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#define GPIO04_FUNC_WPU_OFFSET 8
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#define GPIO04_FUNC_WPU_MASK 0x00000100
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#define GPIO04_FUNC_WPD_OFFSET 7
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#define GPIO04_FUNC_WPD_MASK 0x00000080
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#define GPIO04_FUNC_SEL_OFFSET 4
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#define GPIO04_FUNC_SEL_MASK 0x00000070
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#define GPIO04_SLP_WPU_OFFSET 3
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#define GPIO04_SLP_WPU_MASK 0x00000008
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#define GPIO04_SLP_WPD_OFFSET 2
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#define GPIO04_SLP_WPD_MASK 0x00000004
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#define GPIO04_SLP_IE_OFFSET 1
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#define GPIO04_SLP_IE_MASK 0x00000002
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#define GPIO04_SLP_OE_OFFSET 0
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#define GPIO04_SLP_OE_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO05_PIN_CFG_ADDR 0x18
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#define GPIO05_SEC_OFFSET 21
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#define GPIO05_SEC_MASK 0x00200000
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#define GPIO05_DRV_OFFSET 19
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#define GPIO05_DRV_MASK 0x00180000
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#define GPIO05_SLP_SEL_OFFSET 18
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#define GPIO05_SLP_SEL_MASK 0x00040000
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#define GPIO05_ODRV_OFFSET 17
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#define GPIO05_ODRV_MASK 0x00020000
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#define GPIO05_IINV_OFFSET 16
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#define GPIO05_IINV_MASK 0x00010000
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#define GPIO05_OINV_OFFSET 15
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#define GPIO05_OINV_MASK 0x00008000
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#define GPIO05_OPOS_OFFSET 14
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#define GPIO05_OPOS_MASK 0x00004000
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#define GPIO05_ONEG_OFFSET 13
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#define GPIO05_ONEG_MASK 0x00002000
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#define GPIO05_IPOS_OFFSET 12
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#define GPIO05_IPOS_MASK 0x00001000
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#define GPIO05_INEG_OFFSET 11
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#define GPIO05_INEG_MASK 0x00000800
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#define GPIO05_ORE_OFFSET 10
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#define GPIO05_ORE_MASK 0x00000400
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#define GPIO05_IRE_OFFSET 9
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#define GPIO05_IRE_MASK 0x00000200
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#define GPIO05_FUNC_WPU_OFFSET 8
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#define GPIO05_FUNC_WPU_MASK 0x00000100
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#define GPIO05_FUNC_WPD_OFFSET 7
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#define GPIO05_FUNC_WPD_MASK 0x00000080
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#define GPIO05_FUNC_SEL_OFFSET 4
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#define GPIO05_FUNC_SEL_MASK 0x00000070
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#define GPIO05_SLP_WPU_OFFSET 3
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#define GPIO05_SLP_WPU_MASK 0x00000008
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#define GPIO05_SLP_WPD_OFFSET 2
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#define GPIO05_SLP_WPD_MASK 0x00000004
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#define GPIO05_SLP_IE_OFFSET 1
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#define GPIO05_SLP_IE_MASK 0x00000002
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#define GPIO05_SLP_OE_OFFSET 0
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#define GPIO05_SLP_OE_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO06_PIN_CFG_ADDR 0x1c
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#define GPIO06_SEC_OFFSET 21
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#define GPIO06_SEC_MASK 0x00200000
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#define GPIO06_DRV_OFFSET 19
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#define GPIO06_DRV_MASK 0x00180000
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#define GPIO06_SLP_SEL_OFFSET 18
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#define GPIO06_SLP_SEL_MASK 0x00040000
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#define GPIO06_ODRV_OFFSET 17
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#define GPIO06_ODRV_MASK 0x00020000
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#define GPIO06_IINV_OFFSET 16
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#define GPIO06_IINV_MASK 0x00010000
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#define GPIO06_OINV_OFFSET 15
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#define GPIO06_OINV_MASK 0x00008000
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#define GPIO06_OPOS_OFFSET 14
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#define GPIO06_OPOS_MASK 0x00004000
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#define GPIO06_ONEG_OFFSET 13
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#define GPIO06_ONEG_MASK 0x00002000
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#define GPIO06_IPOS_OFFSET 12
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#define GPIO06_IPOS_MASK 0x00001000
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#define GPIO06_INEG_OFFSET 11
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#define GPIO06_INEG_MASK 0x00000800
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#define GPIO06_ORE_OFFSET 10
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#define GPIO06_ORE_MASK 0x00000400
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#define GPIO06_IRE_OFFSET 9
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#define GPIO06_IRE_MASK 0x00000200
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#define GPIO06_FUNC_WPU_OFFSET 8
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#define GPIO06_FUNC_WPU_MASK 0x00000100
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#define GPIO06_FUNC_WPD_OFFSET 7
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#define GPIO06_FUNC_WPD_MASK 0x00000080
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#define GPIO06_FUNC_SEL_OFFSET 4
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#define GPIO06_FUNC_SEL_MASK 0x00000070
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#define GPIO06_SLP_WPU_OFFSET 3
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#define GPIO06_SLP_WPU_MASK 0x00000008
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#define GPIO06_SLP_WPD_OFFSET 2
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#define GPIO06_SLP_WPD_MASK 0x00000004
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#define GPIO06_SLP_IE_OFFSET 1
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#define GPIO06_SLP_IE_MASK 0x00000002
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#define GPIO06_SLP_OE_OFFSET 0
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#define GPIO06_SLP_OE_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO07_PIN_CFG_ADDR 0x20
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#define GPIO07_SEC_OFFSET 21
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#define GPIO07_SEC_MASK 0x00200000
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#define GPIO07_DRV_OFFSET 19
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#define GPIO07_DRV_MASK 0x00180000
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#define GPIO07_SLP_SEL_OFFSET 18
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#define GPIO07_SLP_SEL_MASK 0x00040000
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#define GPIO07_ODRV_OFFSET 17
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#define GPIO07_ODRV_MASK 0x00020000
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#define GPIO07_IINV_OFFSET 16
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#define GPIO07_IINV_MASK 0x00010000
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#define GPIO07_OINV_OFFSET 15
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#define GPIO07_OINV_MASK 0x00008000
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#define GPIO07_OPOS_OFFSET 14
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#define GPIO07_OPOS_MASK 0x00004000
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#define GPIO07_ONEG_OFFSET 13
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#define GPIO07_ONEG_MASK 0x00002000
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#define GPIO07_IPOS_OFFSET 12
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#define GPIO07_IPOS_MASK 0x00001000
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#define GPIO07_INEG_OFFSET 11
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#define GPIO07_INEG_MASK 0x00000800
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#define GPIO07_ORE_OFFSET 10
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#define GPIO07_ORE_MASK 0x00000400
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#define GPIO07_IRE_OFFSET 9
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#define GPIO07_IRE_MASK 0x00000200
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#define GPIO07_FUNC_WPU_OFFSET 8
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#define GPIO07_FUNC_WPU_MASK 0x00000100
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#define GPIO07_FUNC_WPD_OFFSET 7
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#define GPIO07_FUNC_WPD_MASK 0x00000080
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#define GPIO07_FUNC_SEL_OFFSET 4
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#define GPIO07_FUNC_SEL_MASK 0x00000070
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#define GPIO07_SLP_WPU_OFFSET 3
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#define GPIO07_SLP_WPU_MASK 0x00000008
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#define GPIO07_SLP_WPD_OFFSET 2
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#define GPIO07_SLP_WPD_MASK 0x00000004
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#define GPIO07_SLP_IE_OFFSET 1
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#define GPIO07_SLP_IE_MASK 0x00000002
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#define GPIO07_SLP_OE_OFFSET 0
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#define GPIO07_SLP_OE_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO08_PIN_CFG_ADDR 0x24
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#define GPIO08_SEC_OFFSET 21
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#define GPIO08_SEC_MASK 0x00200000
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#define GPIO08_DRV_OFFSET 19
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#define GPIO08_DRV_MASK 0x00180000
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#define GPIO08_SLP_SEL_OFFSET 18
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#define GPIO08_SLP_SEL_MASK 0x00040000
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#define GPIO08_ODRV_OFFSET 17
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#define GPIO08_ODRV_MASK 0x00020000
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#define GPIO08_IINV_OFFSET 16
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#define GPIO08_IINV_MASK 0x00010000
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#define GPIO08_OINV_OFFSET 15
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#define GPIO08_OINV_MASK 0x00008000
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#define GPIO08_OPOS_OFFSET 14
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#define GPIO08_OPOS_MASK 0x00004000
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#define GPIO08_ONEG_OFFSET 13
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#define GPIO08_ONEG_MASK 0x00002000
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#define GPIO08_IPOS_OFFSET 12
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#define GPIO08_IPOS_MASK 0x00001000
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#define GPIO08_INEG_OFFSET 11
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#define GPIO08_INEG_MASK 0x00000800
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#define GPIO08_ORE_OFFSET 10
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#define GPIO08_ORE_MASK 0x00000400
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#define GPIO08_IRE_OFFSET 9
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#define GPIO08_IRE_MASK 0x00000200
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#define GPIO08_FUNC_WPU_OFFSET 8
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#define GPIO08_FUNC_WPU_MASK 0x00000100
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#define GPIO08_FUNC_WPD_OFFSET 7
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#define GPIO08_FUNC_WPD_MASK 0x00000080
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#define GPIO08_FUNC_SEL_OFFSET 4
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#define GPIO08_FUNC_SEL_MASK 0x00000070
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#define GPIO08_SLP_WPU_OFFSET 3
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#define GPIO08_SLP_WPU_MASK 0x00000008
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|
#define GPIO08_SLP_WPD_OFFSET 2
|
|
#define GPIO08_SLP_WPD_MASK 0x00000004
|
|
#define GPIO08_SLP_IE_OFFSET 1
|
|
#define GPIO08_SLP_IE_MASK 0x00000002
|
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#define GPIO08_SLP_OE_OFFSET 0
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#define GPIO08_SLP_OE_MASK 0x00000001
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|
|
//-----------------------------------
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#define CFG_GPIO09_PIN_CFG_ADDR 0x28
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#define GPIO09_SEC_OFFSET 21
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#define GPIO09_SEC_MASK 0x00200000
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#define GPIO09_DRV_OFFSET 19
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#define GPIO09_DRV_MASK 0x00180000
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#define GPIO09_SLP_SEL_OFFSET 18
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#define GPIO09_SLP_SEL_MASK 0x00040000
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#define GPIO09_ODRV_OFFSET 17
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#define GPIO09_ODRV_MASK 0x00020000
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#define GPIO09_IINV_OFFSET 16
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#define GPIO09_IINV_MASK 0x00010000
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#define GPIO09_OINV_OFFSET 15
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#define GPIO09_OINV_MASK 0x00008000
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#define GPIO09_OPOS_OFFSET 14
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#define GPIO09_OPOS_MASK 0x00004000
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#define GPIO09_ONEG_OFFSET 13
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#define GPIO09_ONEG_MASK 0x00002000
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#define GPIO09_IPOS_OFFSET 12
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#define GPIO09_IPOS_MASK 0x00001000
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#define GPIO09_INEG_OFFSET 11
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#define GPIO09_INEG_MASK 0x00000800
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#define GPIO09_ORE_OFFSET 10
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#define GPIO09_ORE_MASK 0x00000400
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|
#define GPIO09_IRE_OFFSET 9
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#define GPIO09_IRE_MASK 0x00000200
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#define GPIO09_FUNC_WPU_OFFSET 8
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#define GPIO09_FUNC_WPU_MASK 0x00000100
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#define GPIO09_FUNC_WPD_OFFSET 7
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#define GPIO09_FUNC_WPD_MASK 0x00000080
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#define GPIO09_FUNC_SEL_OFFSET 4
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#define GPIO09_FUNC_SEL_MASK 0x00000070
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#define GPIO09_SLP_WPU_OFFSET 3
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|
#define GPIO09_SLP_WPU_MASK 0x00000008
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|
#define GPIO09_SLP_WPD_OFFSET 2
|
|
#define GPIO09_SLP_WPD_MASK 0x00000004
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|
#define GPIO09_SLP_IE_OFFSET 1
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#define GPIO09_SLP_IE_MASK 0x00000002
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|
#define GPIO09_SLP_OE_OFFSET 0
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|
#define GPIO09_SLP_OE_MASK 0x00000001
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|
|
//-----------------------------------
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|
#define CFG_GPIO10_PIN_CFG_ADDR 0x2c
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|
#define GPIO10_SEC_OFFSET 21
|
|
#define GPIO10_SEC_MASK 0x00200000
|
|
#define GPIO10_DRV_OFFSET 19
|
|
#define GPIO10_DRV_MASK 0x00180000
|
|
#define GPIO10_SLP_SEL_OFFSET 18
|
|
#define GPIO10_SLP_SEL_MASK 0x00040000
|
|
#define GPIO10_ODRV_OFFSET 17
|
|
#define GPIO10_ODRV_MASK 0x00020000
|
|
#define GPIO10_IINV_OFFSET 16
|
|
#define GPIO10_IINV_MASK 0x00010000
|
|
#define GPIO10_OINV_OFFSET 15
|
|
#define GPIO10_OINV_MASK 0x00008000
|
|
#define GPIO10_OPOS_OFFSET 14
|
|
#define GPIO10_OPOS_MASK 0x00004000
|
|
#define GPIO10_ONEG_OFFSET 13
|
|
#define GPIO10_ONEG_MASK 0x00002000
|
|
#define GPIO10_IPOS_OFFSET 12
|
|
#define GPIO10_IPOS_MASK 0x00001000
|
|
#define GPIO10_INEG_OFFSET 11
|
|
#define GPIO10_INEG_MASK 0x00000800
|
|
#define GPIO10_ORE_OFFSET 10
|
|
#define GPIO10_ORE_MASK 0x00000400
|
|
#define GPIO10_IRE_OFFSET 9
|
|
#define GPIO10_IRE_MASK 0x00000200
|
|
#define GPIO10_FUNC_WPU_OFFSET 8
|
|
#define GPIO10_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO10_FUNC_WPD_OFFSET 7
|
|
#define GPIO10_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO10_FUNC_SEL_OFFSET 4
|
|
#define GPIO10_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO10_SLP_WPU_OFFSET 3
|
|
#define GPIO10_SLP_WPU_MASK 0x00000008
|
|
#define GPIO10_SLP_WPD_OFFSET 2
|
|
#define GPIO10_SLP_WPD_MASK 0x00000004
|
|
#define GPIO10_SLP_IE_OFFSET 1
|
|
#define GPIO10_SLP_IE_MASK 0x00000002
|
|
#define GPIO10_SLP_OE_OFFSET 0
|
|
#define GPIO10_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO11_PIN_CFG_ADDR 0x30
|
|
#define GPIO11_SEC_OFFSET 21
|
|
#define GPIO11_SEC_MASK 0x00200000
|
|
#define GPIO11_DRV_OFFSET 19
|
|
#define GPIO11_DRV_MASK 0x00180000
|
|
#define GPIO11_SLP_SEL_OFFSET 18
|
|
#define GPIO11_SLP_SEL_MASK 0x00040000
|
|
#define GPIO11_ODRV_OFFSET 17
|
|
#define GPIO11_ODRV_MASK 0x00020000
|
|
#define GPIO11_IINV_OFFSET 16
|
|
#define GPIO11_IINV_MASK 0x00010000
|
|
#define GPIO11_OINV_OFFSET 15
|
|
#define GPIO11_OINV_MASK 0x00008000
|
|
#define GPIO11_OPOS_OFFSET 14
|
|
#define GPIO11_OPOS_MASK 0x00004000
|
|
#define GPIO11_ONEG_OFFSET 13
|
|
#define GPIO11_ONEG_MASK 0x00002000
|
|
#define GPIO11_IPOS_OFFSET 12
|
|
#define GPIO11_IPOS_MASK 0x00001000
|
|
#define GPIO11_INEG_OFFSET 11
|
|
#define GPIO11_INEG_MASK 0x00000800
|
|
#define GPIO11_ORE_OFFSET 10
|
|
#define GPIO11_ORE_MASK 0x00000400
|
|
#define GPIO11_IRE_OFFSET 9
|
|
#define GPIO11_IRE_MASK 0x00000200
|
|
#define GPIO11_FUNC_WPU_OFFSET 8
|
|
#define GPIO11_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO11_FUNC_WPD_OFFSET 7
|
|
#define GPIO11_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO11_FUNC_SEL_OFFSET 4
|
|
#define GPIO11_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO11_SLP_WPU_OFFSET 3
|
|
#define GPIO11_SLP_WPU_MASK 0x00000008
|
|
#define GPIO11_SLP_WPD_OFFSET 2
|
|
#define GPIO11_SLP_WPD_MASK 0x00000004
|
|
#define GPIO11_SLP_IE_OFFSET 1
|
|
#define GPIO11_SLP_IE_MASK 0x00000002
|
|
#define GPIO11_SLP_OE_OFFSET 0
|
|
#define GPIO11_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO12_PIN_CFG_ADDR 0x34
|
|
#define GPIO12_SEC_OFFSET 21
|
|
#define GPIO12_SEC_MASK 0x00200000
|
|
#define GPIO12_DRV_OFFSET 19
|
|
#define GPIO12_DRV_MASK 0x00180000
|
|
#define GPIO12_SLP_SEL_OFFSET 18
|
|
#define GPIO12_SLP_SEL_MASK 0x00040000
|
|
#define GPIO12_ODRV_OFFSET 17
|
|
#define GPIO12_ODRV_MASK 0x00020000
|
|
#define GPIO12_IINV_OFFSET 16
|
|
#define GPIO12_IINV_MASK 0x00010000
|
|
#define GPIO12_OINV_OFFSET 15
|
|
#define GPIO12_OINV_MASK 0x00008000
|
|
#define GPIO12_OPOS_OFFSET 14
|
|
#define GPIO12_OPOS_MASK 0x00004000
|
|
#define GPIO12_ONEG_OFFSET 13
|
|
#define GPIO12_ONEG_MASK 0x00002000
|
|
#define GPIO12_IPOS_OFFSET 12
|
|
#define GPIO12_IPOS_MASK 0x00001000
|
|
#define GPIO12_INEG_OFFSET 11
|
|
#define GPIO12_INEG_MASK 0x00000800
|
|
#define GPIO12_ORE_OFFSET 10
|
|
#define GPIO12_ORE_MASK 0x00000400
|
|
#define GPIO12_IRE_OFFSET 9
|
|
#define GPIO12_IRE_MASK 0x00000200
|
|
#define GPIO12_FUNC_WPU_OFFSET 8
|
|
#define GPIO12_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO12_FUNC_WPD_OFFSET 7
|
|
#define GPIO12_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO12_FUNC_SEL_OFFSET 4
|
|
#define GPIO12_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO12_SLP_WPU_OFFSET 3
|
|
#define GPIO12_SLP_WPU_MASK 0x00000008
|
|
#define GPIO12_SLP_WPD_OFFSET 2
|
|
#define GPIO12_SLP_WPD_MASK 0x00000004
|
|
#define GPIO12_SLP_IE_OFFSET 1
|
|
#define GPIO12_SLP_IE_MASK 0x00000002
|
|
#define GPIO12_SLP_OE_OFFSET 0
|
|
#define GPIO12_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO13_PIN_CFG_ADDR 0x38
|
|
#define GPIO13_SEC_OFFSET 21
|
|
#define GPIO13_SEC_MASK 0x00200000
|
|
#define GPIO13_DRV_OFFSET 19
|
|
#define GPIO13_DRV_MASK 0x00180000
|
|
#define GPIO13_SLP_SEL_OFFSET 18
|
|
#define GPIO13_SLP_SEL_MASK 0x00040000
|
|
#define GPIO13_ODRV_OFFSET 17
|
|
#define GPIO13_ODRV_MASK 0x00020000
|
|
#define GPIO13_IINV_OFFSET 16
|
|
#define GPIO13_IINV_MASK 0x00010000
|
|
#define GPIO13_OINV_OFFSET 15
|
|
#define GPIO13_OINV_MASK 0x00008000
|
|
#define GPIO13_OPOS_OFFSET 14
|
|
#define GPIO13_OPOS_MASK 0x00004000
|
|
#define GPIO13_ONEG_OFFSET 13
|
|
#define GPIO13_ONEG_MASK 0x00002000
|
|
#define GPIO13_IPOS_OFFSET 12
|
|
#define GPIO13_IPOS_MASK 0x00001000
|
|
#define GPIO13_INEG_OFFSET 11
|
|
#define GPIO13_INEG_MASK 0x00000800
|
|
#define GPIO13_ORE_OFFSET 10
|
|
#define GPIO13_ORE_MASK 0x00000400
|
|
#define GPIO13_IRE_OFFSET 9
|
|
#define GPIO13_IRE_MASK 0x00000200
|
|
#define GPIO13_FUNC_WPU_OFFSET 8
|
|
#define GPIO13_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO13_FUNC_WPD_OFFSET 7
|
|
#define GPIO13_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO13_FUNC_SEL_OFFSET 4
|
|
#define GPIO13_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO13_SLP_WPU_OFFSET 3
|
|
#define GPIO13_SLP_WPU_MASK 0x00000008
|
|
#define GPIO13_SLP_WPD_OFFSET 2
|
|
#define GPIO13_SLP_WPD_MASK 0x00000004
|
|
#define GPIO13_SLP_IE_OFFSET 1
|
|
#define GPIO13_SLP_IE_MASK 0x00000002
|
|
#define GPIO13_SLP_OE_OFFSET 0
|
|
#define GPIO13_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO14_PIN_CFG_ADDR 0x3c
|
|
#define GPIO14_SEC_OFFSET 21
|
|
#define GPIO14_SEC_MASK 0x00200000
|
|
#define GPIO14_DRV_OFFSET 19
|
|
#define GPIO14_DRV_MASK 0x00180000
|
|
#define GPIO14_SLP_SEL_OFFSET 18
|
|
#define GPIO14_SLP_SEL_MASK 0x00040000
|
|
#define GPIO14_ODRV_OFFSET 17
|
|
#define GPIO14_ODRV_MASK 0x00020000
|
|
#define GPIO14_IINV_OFFSET 16
|
|
#define GPIO14_IINV_MASK 0x00010000
|
|
#define GPIO14_OINV_OFFSET 15
|
|
#define GPIO14_OINV_MASK 0x00008000
|
|
#define GPIO14_OPOS_OFFSET 14
|
|
#define GPIO14_OPOS_MASK 0x00004000
|
|
#define GPIO14_ONEG_OFFSET 13
|
|
#define GPIO14_ONEG_MASK 0x00002000
|
|
#define GPIO14_IPOS_OFFSET 12
|
|
#define GPIO14_IPOS_MASK 0x00001000
|
|
#define GPIO14_INEG_OFFSET 11
|
|
#define GPIO14_INEG_MASK 0x00000800
|
|
#define GPIO14_ORE_OFFSET 10
|
|
#define GPIO14_ORE_MASK 0x00000400
|
|
#define GPIO14_IRE_OFFSET 9
|
|
#define GPIO14_IRE_MASK 0x00000200
|
|
#define GPIO14_FUNC_WPU_OFFSET 8
|
|
#define GPIO14_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO14_FUNC_WPD_OFFSET 7
|
|
#define GPIO14_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO14_FUNC_SEL_OFFSET 4
|
|
#define GPIO14_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO14_SLP_WPU_OFFSET 3
|
|
#define GPIO14_SLP_WPU_MASK 0x00000008
|
|
#define GPIO14_SLP_WPD_OFFSET 2
|
|
#define GPIO14_SLP_WPD_MASK 0x00000004
|
|
#define GPIO14_SLP_IE_OFFSET 1
|
|
#define GPIO14_SLP_IE_MASK 0x00000002
|
|
#define GPIO14_SLP_OE_OFFSET 0
|
|
#define GPIO14_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO15_PIN_CFG_ADDR 0x40
|
|
#define GPIO15_SEC_OFFSET 21
|
|
#define GPIO15_SEC_MASK 0x00200000
|
|
#define GPIO15_DRV_OFFSET 19
|
|
#define GPIO15_DRV_MASK 0x00180000
|
|
#define GPIO15_SLP_SEL_OFFSET 18
|
|
#define GPIO15_SLP_SEL_MASK 0x00040000
|
|
#define GPIO15_ODRV_OFFSET 17
|
|
#define GPIO15_ODRV_MASK 0x00020000
|
|
#define GPIO15_IINV_OFFSET 16
|
|
#define GPIO15_IINV_MASK 0x00010000
|
|
#define GPIO15_OINV_OFFSET 15
|
|
#define GPIO15_OINV_MASK 0x00008000
|
|
#define GPIO15_OPOS_OFFSET 14
|
|
#define GPIO15_OPOS_MASK 0x00004000
|
|
#define GPIO15_ONEG_OFFSET 13
|
|
#define GPIO15_ONEG_MASK 0x00002000
|
|
#define GPIO15_IPOS_OFFSET 12
|
|
#define GPIO15_IPOS_MASK 0x00001000
|
|
#define GPIO15_INEG_OFFSET 11
|
|
#define GPIO15_INEG_MASK 0x00000800
|
|
#define GPIO15_ORE_OFFSET 10
|
|
#define GPIO15_ORE_MASK 0x00000400
|
|
#define GPIO15_IRE_OFFSET 9
|
|
#define GPIO15_IRE_MASK 0x00000200
|
|
#define GPIO15_FUNC_WPU_OFFSET 8
|
|
#define GPIO15_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO15_FUNC_WPD_OFFSET 7
|
|
#define GPIO15_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO15_FUNC_SEL_OFFSET 4
|
|
#define GPIO15_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO15_SLP_WPU_OFFSET 3
|
|
#define GPIO15_SLP_WPU_MASK 0x00000008
|
|
#define GPIO15_SLP_WPD_OFFSET 2
|
|
#define GPIO15_SLP_WPD_MASK 0x00000004
|
|
#define GPIO15_SLP_IE_OFFSET 1
|
|
#define GPIO15_SLP_IE_MASK 0x00000002
|
|
#define GPIO15_SLP_OE_OFFSET 0
|
|
#define GPIO15_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO16_PIN_CFG_ADDR 0x44
|
|
#define GPIO16_SEC_OFFSET 21
|
|
#define GPIO16_SEC_MASK 0x00200000
|
|
#define GPIO16_DRV_OFFSET 19
|
|
#define GPIO16_DRV_MASK 0x00180000
|
|
#define GPIO16_SLP_SEL_OFFSET 18
|
|
#define GPIO16_SLP_SEL_MASK 0x00040000
|
|
#define GPIO16_ODRV_OFFSET 17
|
|
#define GPIO16_ODRV_MASK 0x00020000
|
|
#define GPIO16_IINV_OFFSET 16
|
|
#define GPIO16_IINV_MASK 0x00010000
|
|
#define GPIO16_OINV_OFFSET 15
|
|
#define GPIO16_OINV_MASK 0x00008000
|
|
#define GPIO16_OPOS_OFFSET 14
|
|
#define GPIO16_OPOS_MASK 0x00004000
|
|
#define GPIO16_ONEG_OFFSET 13
|
|
#define GPIO16_ONEG_MASK 0x00002000
|
|
#define GPIO16_IPOS_OFFSET 12
|
|
#define GPIO16_IPOS_MASK 0x00001000
|
|
#define GPIO16_INEG_OFFSET 11
|
|
#define GPIO16_INEG_MASK 0x00000800
|
|
#define GPIO16_ORE_OFFSET 10
|
|
#define GPIO16_ORE_MASK 0x00000400
|
|
#define GPIO16_IRE_OFFSET 9
|
|
#define GPIO16_IRE_MASK 0x00000200
|
|
#define GPIO16_FUNC_WPU_OFFSET 8
|
|
#define GPIO16_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO16_FUNC_WPD_OFFSET 7
|
|
#define GPIO16_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO16_FUNC_SEL_OFFSET 4
|
|
#define GPIO16_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO16_SLP_WPU_OFFSET 3
|
|
#define GPIO16_SLP_WPU_MASK 0x00000008
|
|
#define GPIO16_SLP_WPD_OFFSET 2
|
|
#define GPIO16_SLP_WPD_MASK 0x00000004
|
|
#define GPIO16_SLP_IE_OFFSET 1
|
|
#define GPIO16_SLP_IE_MASK 0x00000002
|
|
#define GPIO16_SLP_OE_OFFSET 0
|
|
#define GPIO16_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO17_PIN_CFG_ADDR 0x48
|
|
#define GPIO17_SEC_OFFSET 21
|
|
#define GPIO17_SEC_MASK 0x00200000
|
|
#define GPIO17_DRV_OFFSET 19
|
|
#define GPIO17_DRV_MASK 0x00180000
|
|
#define GPIO17_SLP_SEL_OFFSET 18
|
|
#define GPIO17_SLP_SEL_MASK 0x00040000
|
|
#define GPIO17_ODRV_OFFSET 17
|
|
#define GPIO17_ODRV_MASK 0x00020000
|
|
#define GPIO17_IINV_OFFSET 16
|
|
#define GPIO17_IINV_MASK 0x00010000
|
|
#define GPIO17_OINV_OFFSET 15
|
|
#define GPIO17_OINV_MASK 0x00008000
|
|
#define GPIO17_OPOS_OFFSET 14
|
|
#define GPIO17_OPOS_MASK 0x00004000
|
|
#define GPIO17_ONEG_OFFSET 13
|
|
#define GPIO17_ONEG_MASK 0x00002000
|
|
#define GPIO17_IPOS_OFFSET 12
|
|
#define GPIO17_IPOS_MASK 0x00001000
|
|
#define GPIO17_INEG_OFFSET 11
|
|
#define GPIO17_INEG_MASK 0x00000800
|
|
#define GPIO17_ORE_OFFSET 10
|
|
#define GPIO17_ORE_MASK 0x00000400
|
|
#define GPIO17_IRE_OFFSET 9
|
|
#define GPIO17_IRE_MASK 0x00000200
|
|
#define GPIO17_FUNC_WPU_OFFSET 8
|
|
#define GPIO17_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO17_FUNC_WPD_OFFSET 7
|
|
#define GPIO17_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO17_FUNC_SEL_OFFSET 4
|
|
#define GPIO17_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO17_SLP_WPU_OFFSET 3
|
|
#define GPIO17_SLP_WPU_MASK 0x00000008
|
|
#define GPIO17_SLP_WPD_OFFSET 2
|
|
#define GPIO17_SLP_WPD_MASK 0x00000004
|
|
#define GPIO17_SLP_IE_OFFSET 1
|
|
#define GPIO17_SLP_IE_MASK 0x00000002
|
|
#define GPIO17_SLP_OE_OFFSET 0
|
|
#define GPIO17_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO18_PIN_CFG_ADDR 0x4c
|
|
#define GPIO18_SEC_OFFSET 21
|
|
#define GPIO18_SEC_MASK 0x00200000
|
|
#define GPIO18_DRV_OFFSET 19
|
|
#define GPIO18_DRV_MASK 0x00180000
|
|
#define GPIO18_SLP_SEL_OFFSET 18
|
|
#define GPIO18_SLP_SEL_MASK 0x00040000
|
|
#define GPIO18_ODRV_OFFSET 17
|
|
#define GPIO18_ODRV_MASK 0x00020000
|
|
#define GPIO18_IINV_OFFSET 16
|
|
#define GPIO18_IINV_MASK 0x00010000
|
|
#define GPIO18_OINV_OFFSET 15
|
|
#define GPIO18_OINV_MASK 0x00008000
|
|
#define GPIO18_OPOS_OFFSET 14
|
|
#define GPIO18_OPOS_MASK 0x00004000
|
|
#define GPIO18_ONEG_OFFSET 13
|
|
#define GPIO18_ONEG_MASK 0x00002000
|
|
#define GPIO18_IPOS_OFFSET 12
|
|
#define GPIO18_IPOS_MASK 0x00001000
|
|
#define GPIO18_INEG_OFFSET 11
|
|
#define GPIO18_INEG_MASK 0x00000800
|
|
#define GPIO18_ORE_OFFSET 10
|
|
#define GPIO18_ORE_MASK 0x00000400
|
|
#define GPIO18_IRE_OFFSET 9
|
|
#define GPIO18_IRE_MASK 0x00000200
|
|
#define GPIO18_FUNC_WPU_OFFSET 8
|
|
#define GPIO18_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO18_FUNC_WPD_OFFSET 7
|
|
#define GPIO18_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO18_FUNC_SEL_OFFSET 4
|
|
#define GPIO18_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO18_SLP_WPU_OFFSET 3
|
|
#define GPIO18_SLP_WPU_MASK 0x00000008
|
|
#define GPIO18_SLP_WPD_OFFSET 2
|
|
#define GPIO18_SLP_WPD_MASK 0x00000004
|
|
#define GPIO18_SLP_IE_OFFSET 1
|
|
#define GPIO18_SLP_IE_MASK 0x00000002
|
|
#define GPIO18_SLP_OE_OFFSET 0
|
|
#define GPIO18_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO19_PIN_CFG_ADDR 0x50
|
|
#define GPIO19_SEC_OFFSET 21
|
|
#define GPIO19_SEC_MASK 0x00200000
|
|
#define GPIO19_DRV_OFFSET 19
|
|
#define GPIO19_DRV_MASK 0x00180000
|
|
#define GPIO19_SLP_SEL_OFFSET 18
|
|
#define GPIO19_SLP_SEL_MASK 0x00040000
|
|
#define GPIO19_ODRV_OFFSET 17
|
|
#define GPIO19_ODRV_MASK 0x00020000
|
|
#define GPIO19_IINV_OFFSET 16
|
|
#define GPIO19_IINV_MASK 0x00010000
|
|
#define GPIO19_OINV_OFFSET 15
|
|
#define GPIO19_OINV_MASK 0x00008000
|
|
#define GPIO19_OPOS_OFFSET 14
|
|
#define GPIO19_OPOS_MASK 0x00004000
|
|
#define GPIO19_ONEG_OFFSET 13
|
|
#define GPIO19_ONEG_MASK 0x00002000
|
|
#define GPIO19_IPOS_OFFSET 12
|
|
#define GPIO19_IPOS_MASK 0x00001000
|
|
#define GPIO19_INEG_OFFSET 11
|
|
#define GPIO19_INEG_MASK 0x00000800
|
|
#define GPIO19_ORE_OFFSET 10
|
|
#define GPIO19_ORE_MASK 0x00000400
|
|
#define GPIO19_IRE_OFFSET 9
|
|
#define GPIO19_IRE_MASK 0x00000200
|
|
#define GPIO19_FUNC_WPU_OFFSET 8
|
|
#define GPIO19_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO19_FUNC_WPD_OFFSET 7
|
|
#define GPIO19_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO19_FUNC_SEL_OFFSET 4
|
|
#define GPIO19_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO19_SLP_WPU_OFFSET 3
|
|
#define GPIO19_SLP_WPU_MASK 0x00000008
|
|
#define GPIO19_SLP_WPD_OFFSET 2
|
|
#define GPIO19_SLP_WPD_MASK 0x00000004
|
|
#define GPIO19_SLP_IE_OFFSET 1
|
|
#define GPIO19_SLP_IE_MASK 0x00000002
|
|
#define GPIO19_SLP_OE_OFFSET 0
|
|
#define GPIO19_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO20_PIN_CFG_ADDR 0x54
|
|
#define GPIO20_SEC_OFFSET 21
|
|
#define GPIO20_SEC_MASK 0x00200000
|
|
#define GPIO20_DRV_OFFSET 19
|
|
#define GPIO20_DRV_MASK 0x00180000
|
|
#define GPIO20_SLP_SEL_OFFSET 18
|
|
#define GPIO20_SLP_SEL_MASK 0x00040000
|
|
#define GPIO20_ODRV_OFFSET 17
|
|
#define GPIO20_ODRV_MASK 0x00020000
|
|
#define GPIO20_IINV_OFFSET 16
|
|
#define GPIO20_IINV_MASK 0x00010000
|
|
#define GPIO20_OINV_OFFSET 15
|
|
#define GPIO20_OINV_MASK 0x00008000
|
|
#define GPIO20_OPOS_OFFSET 14
|
|
#define GPIO20_OPOS_MASK 0x00004000
|
|
#define GPIO20_ONEG_OFFSET 13
|
|
#define GPIO20_ONEG_MASK 0x00002000
|
|
#define GPIO20_IPOS_OFFSET 12
|
|
#define GPIO20_IPOS_MASK 0x00001000
|
|
#define GPIO20_INEG_OFFSET 11
|
|
#define GPIO20_INEG_MASK 0x00000800
|
|
#define GPIO20_ORE_OFFSET 10
|
|
#define GPIO20_ORE_MASK 0x00000400
|
|
#define GPIO20_IRE_OFFSET 9
|
|
#define GPIO20_IRE_MASK 0x00000200
|
|
#define GPIO20_FUNC_WPU_OFFSET 8
|
|
#define GPIO20_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO20_FUNC_WPD_OFFSET 7
|
|
#define GPIO20_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO20_FUNC_SEL_OFFSET 4
|
|
#define GPIO20_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO20_SLP_WPU_OFFSET 3
|
|
#define GPIO20_SLP_WPU_MASK 0x00000008
|
|
#define GPIO20_SLP_WPD_OFFSET 2
|
|
#define GPIO20_SLP_WPD_MASK 0x00000004
|
|
#define GPIO20_SLP_IE_OFFSET 1
|
|
#define GPIO20_SLP_IE_MASK 0x00000002
|
|
#define GPIO20_SLP_OE_OFFSET 0
|
|
#define GPIO20_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO21_PIN_CFG_ADDR 0x58
|
|
#define GPIO21_SEC_OFFSET 21
|
|
#define GPIO21_SEC_MASK 0x00200000
|
|
#define GPIO21_DRV_OFFSET 19
|
|
#define GPIO21_DRV_MASK 0x00180000
|
|
#define GPIO21_SLP_SEL_OFFSET 18
|
|
#define GPIO21_SLP_SEL_MASK 0x00040000
|
|
#define GPIO21_ODRV_OFFSET 17
|
|
#define GPIO21_ODRV_MASK 0x00020000
|
|
#define GPIO21_IINV_OFFSET 16
|
|
#define GPIO21_IINV_MASK 0x00010000
|
|
#define GPIO21_OINV_OFFSET 15
|
|
#define GPIO21_OINV_MASK 0x00008000
|
|
#define GPIO21_OPOS_OFFSET 14
|
|
#define GPIO21_OPOS_MASK 0x00004000
|
|
#define GPIO21_ONEG_OFFSET 13
|
|
#define GPIO21_ONEG_MASK 0x00002000
|
|
#define GPIO21_IPOS_OFFSET 12
|
|
#define GPIO21_IPOS_MASK 0x00001000
|
|
#define GPIO21_INEG_OFFSET 11
|
|
#define GPIO21_INEG_MASK 0x00000800
|
|
#define GPIO21_ORE_OFFSET 10
|
|
#define GPIO21_ORE_MASK 0x00000400
|
|
#define GPIO21_IRE_OFFSET 9
|
|
#define GPIO21_IRE_MASK 0x00000200
|
|
#define GPIO21_FUNC_WPU_OFFSET 8
|
|
#define GPIO21_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO21_FUNC_WPD_OFFSET 7
|
|
#define GPIO21_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO21_FUNC_SEL_OFFSET 4
|
|
#define GPIO21_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO21_SLP_WPU_OFFSET 3
|
|
#define GPIO21_SLP_WPU_MASK 0x00000008
|
|
#define GPIO21_SLP_WPD_OFFSET 2
|
|
#define GPIO21_SLP_WPD_MASK 0x00000004
|
|
#define GPIO21_SLP_IE_OFFSET 1
|
|
#define GPIO21_SLP_IE_MASK 0x00000002
|
|
#define GPIO21_SLP_OE_OFFSET 0
|
|
#define GPIO21_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO22_PIN_CFG_ADDR 0x5c
|
|
#define GPIO22_SEC_OFFSET 21
|
|
#define GPIO22_SEC_MASK 0x00200000
|
|
#define GPIO22_DRV_OFFSET 19
|
|
#define GPIO22_DRV_MASK 0x00180000
|
|
#define GPIO22_SLP_SEL_OFFSET 18
|
|
#define GPIO22_SLP_SEL_MASK 0x00040000
|
|
#define GPIO22_ODRV_OFFSET 17
|
|
#define GPIO22_ODRV_MASK 0x00020000
|
|
#define GPIO22_IINV_OFFSET 16
|
|
#define GPIO22_IINV_MASK 0x00010000
|
|
#define GPIO22_OINV_OFFSET 15
|
|
#define GPIO22_OINV_MASK 0x00008000
|
|
#define GPIO22_OPOS_OFFSET 14
|
|
#define GPIO22_OPOS_MASK 0x00004000
|
|
#define GPIO22_ONEG_OFFSET 13
|
|
#define GPIO22_ONEG_MASK 0x00002000
|
|
#define GPIO22_IPOS_OFFSET 12
|
|
#define GPIO22_IPOS_MASK 0x00001000
|
|
#define GPIO22_INEG_OFFSET 11
|
|
#define GPIO22_INEG_MASK 0x00000800
|
|
#define GPIO22_ORE_OFFSET 10
|
|
#define GPIO22_ORE_MASK 0x00000400
|
|
#define GPIO22_IRE_OFFSET 9
|
|
#define GPIO22_IRE_MASK 0x00000200
|
|
#define GPIO22_FUNC_WPU_OFFSET 8
|
|
#define GPIO22_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO22_FUNC_WPD_OFFSET 7
|
|
#define GPIO22_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO22_FUNC_SEL_OFFSET 4
|
|
#define GPIO22_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO22_SLP_WPU_OFFSET 3
|
|
#define GPIO22_SLP_WPU_MASK 0x00000008
|
|
#define GPIO22_SLP_WPD_OFFSET 2
|
|
#define GPIO22_SLP_WPD_MASK 0x00000004
|
|
#define GPIO22_SLP_IE_OFFSET 1
|
|
#define GPIO22_SLP_IE_MASK 0x00000002
|
|
#define GPIO22_SLP_OE_OFFSET 0
|
|
#define GPIO22_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO23_PIN_CFG_ADDR 0x60
|
|
#define GPIO23_SEC_OFFSET 21
|
|
#define GPIO23_SEC_MASK 0x00200000
|
|
#define GPIO23_DRV_OFFSET 19
|
|
#define GPIO23_DRV_MASK 0x00180000
|
|
#define GPIO23_SLP_SEL_OFFSET 18
|
|
#define GPIO23_SLP_SEL_MASK 0x00040000
|
|
#define GPIO23_ODRV_OFFSET 17
|
|
#define GPIO23_ODRV_MASK 0x00020000
|
|
#define GPIO23_IINV_OFFSET 16
|
|
#define GPIO23_IINV_MASK 0x00010000
|
|
#define GPIO23_OINV_OFFSET 15
|
|
#define GPIO23_OINV_MASK 0x00008000
|
|
#define GPIO23_OPOS_OFFSET 14
|
|
#define GPIO23_OPOS_MASK 0x00004000
|
|
#define GPIO23_ONEG_OFFSET 13
|
|
#define GPIO23_ONEG_MASK 0x00002000
|
|
#define GPIO23_IPOS_OFFSET 12
|
|
#define GPIO23_IPOS_MASK 0x00001000
|
|
#define GPIO23_INEG_OFFSET 11
|
|
#define GPIO23_INEG_MASK 0x00000800
|
|
#define GPIO23_ORE_OFFSET 10
|
|
#define GPIO23_ORE_MASK 0x00000400
|
|
#define GPIO23_IRE_OFFSET 9
|
|
#define GPIO23_IRE_MASK 0x00000200
|
|
#define GPIO23_FUNC_WPU_OFFSET 8
|
|
#define GPIO23_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO23_FUNC_WPD_OFFSET 7
|
|
#define GPIO23_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO23_FUNC_SEL_OFFSET 4
|
|
#define GPIO23_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO23_SLP_WPU_OFFSET 3
|
|
#define GPIO23_SLP_WPU_MASK 0x00000008
|
|
#define GPIO23_SLP_WPD_OFFSET 2
|
|
#define GPIO23_SLP_WPD_MASK 0x00000004
|
|
#define GPIO23_SLP_IE_OFFSET 1
|
|
#define GPIO23_SLP_IE_MASK 0x00000002
|
|
#define GPIO23_SLP_OE_OFFSET 0
|
|
#define GPIO23_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO24_PIN_CFG_ADDR 0x64
|
|
#define GPIO24_SEC_OFFSET 21
|
|
#define GPIO24_SEC_MASK 0x00200000
|
|
#define GPIO24_DRV_OFFSET 19
|
|
#define GPIO24_DRV_MASK 0x00180000
|
|
#define GPIO24_SLP_SEL_OFFSET 18
|
|
#define GPIO24_SLP_SEL_MASK 0x00040000
|
|
#define GPIO24_ODRV_OFFSET 17
|
|
#define GPIO24_ODRV_MASK 0x00020000
|
|
#define GPIO24_IINV_OFFSET 16
|
|
#define GPIO24_IINV_MASK 0x00010000
|
|
#define GPIO24_OINV_OFFSET 15
|
|
#define GPIO24_OINV_MASK 0x00008000
|
|
#define GPIO24_OPOS_OFFSET 14
|
|
#define GPIO24_OPOS_MASK 0x00004000
|
|
#define GPIO24_ONEG_OFFSET 13
|
|
#define GPIO24_ONEG_MASK 0x00002000
|
|
#define GPIO24_IPOS_OFFSET 12
|
|
#define GPIO24_IPOS_MASK 0x00001000
|
|
#define GPIO24_INEG_OFFSET 11
|
|
#define GPIO24_INEG_MASK 0x00000800
|
|
#define GPIO24_ORE_OFFSET 10
|
|
#define GPIO24_ORE_MASK 0x00000400
|
|
#define GPIO24_IRE_OFFSET 9
|
|
#define GPIO24_IRE_MASK 0x00000200
|
|
#define GPIO24_FUNC_WPU_OFFSET 8
|
|
#define GPIO24_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO24_FUNC_WPD_OFFSET 7
|
|
#define GPIO24_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO24_FUNC_SEL_OFFSET 4
|
|
#define GPIO24_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO24_SLP_WPU_OFFSET 3
|
|
#define GPIO24_SLP_WPU_MASK 0x00000008
|
|
#define GPIO24_SLP_WPD_OFFSET 2
|
|
#define GPIO24_SLP_WPD_MASK 0x00000004
|
|
#define GPIO24_SLP_IE_OFFSET 1
|
|
#define GPIO24_SLP_IE_MASK 0x00000002
|
|
#define GPIO24_SLP_OE_OFFSET 0
|
|
#define GPIO24_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO25_PIN_CFG_ADDR 0x68
|
|
#define GPIO25_SEC_OFFSET 21
|
|
#define GPIO25_SEC_MASK 0x00200000
|
|
#define GPIO25_DRV_OFFSET 19
|
|
#define GPIO25_DRV_MASK 0x00180000
|
|
#define GPIO25_SLP_SEL_OFFSET 18
|
|
#define GPIO25_SLP_SEL_MASK 0x00040000
|
|
#define GPIO25_ODRV_OFFSET 17
|
|
#define GPIO25_ODRV_MASK 0x00020000
|
|
#define GPIO25_IINV_OFFSET 16
|
|
#define GPIO25_IINV_MASK 0x00010000
|
|
#define GPIO25_OINV_OFFSET 15
|
|
#define GPIO25_OINV_MASK 0x00008000
|
|
#define GPIO25_OPOS_OFFSET 14
|
|
#define GPIO25_OPOS_MASK 0x00004000
|
|
#define GPIO25_ONEG_OFFSET 13
|
|
#define GPIO25_ONEG_MASK 0x00002000
|
|
#define GPIO25_IPOS_OFFSET 12
|
|
#define GPIO25_IPOS_MASK 0x00001000
|
|
#define GPIO25_INEG_OFFSET 11
|
|
#define GPIO25_INEG_MASK 0x00000800
|
|
#define GPIO25_ORE_OFFSET 10
|
|
#define GPIO25_ORE_MASK 0x00000400
|
|
#define GPIO25_IRE_OFFSET 9
|
|
#define GPIO25_IRE_MASK 0x00000200
|
|
#define GPIO25_FUNC_WPU_OFFSET 8
|
|
#define GPIO25_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO25_FUNC_WPD_OFFSET 7
|
|
#define GPIO25_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO25_FUNC_SEL_OFFSET 4
|
|
#define GPIO25_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO25_SLP_WPU_OFFSET 3
|
|
#define GPIO25_SLP_WPU_MASK 0x00000008
|
|
#define GPIO25_SLP_WPD_OFFSET 2
|
|
#define GPIO25_SLP_WPD_MASK 0x00000004
|
|
#define GPIO25_SLP_IE_OFFSET 1
|
|
#define GPIO25_SLP_IE_MASK 0x00000002
|
|
#define GPIO25_SLP_OE_OFFSET 0
|
|
#define GPIO25_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO26_PIN_CFG_ADDR 0x6c
|
|
#define GPIO26_SEC_OFFSET 21
|
|
#define GPIO26_SEC_MASK 0x00200000
|
|
#define GPIO26_DRV_OFFSET 19
|
|
#define GPIO26_DRV_MASK 0x00180000
|
|
#define GPIO26_SLP_SEL_OFFSET 18
|
|
#define GPIO26_SLP_SEL_MASK 0x00040000
|
|
#define GPIO26_ODRV_OFFSET 17
|
|
#define GPIO26_ODRV_MASK 0x00020000
|
|
#define GPIO26_IINV_OFFSET 16
|
|
#define GPIO26_IINV_MASK 0x00010000
|
|
#define GPIO26_OINV_OFFSET 15
|
|
#define GPIO26_OINV_MASK 0x00008000
|
|
#define GPIO26_OPOS_OFFSET 14
|
|
#define GPIO26_OPOS_MASK 0x00004000
|
|
#define GPIO26_ONEG_OFFSET 13
|
|
#define GPIO26_ONEG_MASK 0x00002000
|
|
#define GPIO26_IPOS_OFFSET 12
|
|
#define GPIO26_IPOS_MASK 0x00001000
|
|
#define GPIO26_INEG_OFFSET 11
|
|
#define GPIO26_INEG_MASK 0x00000800
|
|
#define GPIO26_ORE_OFFSET 10
|
|
#define GPIO26_ORE_MASK 0x00000400
|
|
#define GPIO26_IRE_OFFSET 9
|
|
#define GPIO26_IRE_MASK 0x00000200
|
|
#define GPIO26_FUNC_WPU_OFFSET 8
|
|
#define GPIO26_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO26_FUNC_WPD_OFFSET 7
|
|
#define GPIO26_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO26_FUNC_SEL_OFFSET 4
|
|
#define GPIO26_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO26_SLP_WPU_OFFSET 3
|
|
#define GPIO26_SLP_WPU_MASK 0x00000008
|
|
#define GPIO26_SLP_WPD_OFFSET 2
|
|
#define GPIO26_SLP_WPD_MASK 0x00000004
|
|
#define GPIO26_SLP_IE_OFFSET 1
|
|
#define GPIO26_SLP_IE_MASK 0x00000002
|
|
#define GPIO26_SLP_OE_OFFSET 0
|
|
#define GPIO26_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO27_PIN_CFG_ADDR 0x70
|
|
#define GPIO27_SEC_OFFSET 21
|
|
#define GPIO27_SEC_MASK 0x00200000
|
|
#define GPIO27_DRV_OFFSET 19
|
|
#define GPIO27_DRV_MASK 0x00180000
|
|
#define GPIO27_SLP_SEL_OFFSET 18
|
|
#define GPIO27_SLP_SEL_MASK 0x00040000
|
|
#define GPIO27_ODRV_OFFSET 17
|
|
#define GPIO27_ODRV_MASK 0x00020000
|
|
#define GPIO27_IINV_OFFSET 16
|
|
#define GPIO27_IINV_MASK 0x00010000
|
|
#define GPIO27_OINV_OFFSET 15
|
|
#define GPIO27_OINV_MASK 0x00008000
|
|
#define GPIO27_OPOS_OFFSET 14
|
|
#define GPIO27_OPOS_MASK 0x00004000
|
|
#define GPIO27_ONEG_OFFSET 13
|
|
#define GPIO27_ONEG_MASK 0x00002000
|
|
#define GPIO27_IPOS_OFFSET 12
|
|
#define GPIO27_IPOS_MASK 0x00001000
|
|
#define GPIO27_INEG_OFFSET 11
|
|
#define GPIO27_INEG_MASK 0x00000800
|
|
#define GPIO27_ORE_OFFSET 10
|
|
#define GPIO27_ORE_MASK 0x00000400
|
|
#define GPIO27_IRE_OFFSET 9
|
|
#define GPIO27_IRE_MASK 0x00000200
|
|
#define GPIO27_FUNC_WPU_OFFSET 8
|
|
#define GPIO27_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO27_FUNC_WPD_OFFSET 7
|
|
#define GPIO27_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO27_FUNC_SEL_OFFSET 4
|
|
#define GPIO27_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO27_SLP_WPU_OFFSET 3
|
|
#define GPIO27_SLP_WPU_MASK 0x00000008
|
|
#define GPIO27_SLP_WPD_OFFSET 2
|
|
#define GPIO27_SLP_WPD_MASK 0x00000004
|
|
#define GPIO27_SLP_IE_OFFSET 1
|
|
#define GPIO27_SLP_IE_MASK 0x00000002
|
|
#define GPIO27_SLP_OE_OFFSET 0
|
|
#define GPIO27_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO28_PIN_CFG_ADDR 0x74
|
|
#define GPIO28_SEC_OFFSET 21
|
|
#define GPIO28_SEC_MASK 0x00200000
|
|
#define GPIO28_DRV_OFFSET 19
|
|
#define GPIO28_DRV_MASK 0x00180000
|
|
#define GPIO28_SLP_SEL_OFFSET 18
|
|
#define GPIO28_SLP_SEL_MASK 0x00040000
|
|
#define GPIO28_ODRV_OFFSET 17
|
|
#define GPIO28_ODRV_MASK 0x00020000
|
|
#define GPIO28_IINV_OFFSET 16
|
|
#define GPIO28_IINV_MASK 0x00010000
|
|
#define GPIO28_OINV_OFFSET 15
|
|
#define GPIO28_OINV_MASK 0x00008000
|
|
#define GPIO28_OPOS_OFFSET 14
|
|
#define GPIO28_OPOS_MASK 0x00004000
|
|
#define GPIO28_ONEG_OFFSET 13
|
|
#define GPIO28_ONEG_MASK 0x00002000
|
|
#define GPIO28_IPOS_OFFSET 12
|
|
#define GPIO28_IPOS_MASK 0x00001000
|
|
#define GPIO28_INEG_OFFSET 11
|
|
#define GPIO28_INEG_MASK 0x00000800
|
|
#define GPIO28_ORE_OFFSET 10
|
|
#define GPIO28_ORE_MASK 0x00000400
|
|
#define GPIO28_IRE_OFFSET 9
|
|
#define GPIO28_IRE_MASK 0x00000200
|
|
#define GPIO28_FUNC_WPU_OFFSET 8
|
|
#define GPIO28_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO28_FUNC_WPD_OFFSET 7
|
|
#define GPIO28_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO28_FUNC_SEL_OFFSET 4
|
|
#define GPIO28_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO28_SLP_WPU_OFFSET 3
|
|
#define GPIO28_SLP_WPU_MASK 0x00000008
|
|
#define GPIO28_SLP_WPD_OFFSET 2
|
|
#define GPIO28_SLP_WPD_MASK 0x00000004
|
|
#define GPIO28_SLP_IE_OFFSET 1
|
|
#define GPIO28_SLP_IE_MASK 0x00000002
|
|
#define GPIO28_SLP_OE_OFFSET 0
|
|
#define GPIO28_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO29_PIN_CFG_ADDR 0x78
|
|
#define GPIO29_SEC_OFFSET 21
|
|
#define GPIO29_SEC_MASK 0x00200000
|
|
#define GPIO29_DRV_OFFSET 19
|
|
#define GPIO29_DRV_MASK 0x00180000
|
|
#define GPIO29_SLP_SEL_OFFSET 18
|
|
#define GPIO29_SLP_SEL_MASK 0x00040000
|
|
#define GPIO29_ODRV_OFFSET 17
|
|
#define GPIO29_ODRV_MASK 0x00020000
|
|
#define GPIO29_IINV_OFFSET 16
|
|
#define GPIO29_IINV_MASK 0x00010000
|
|
#define GPIO29_OINV_OFFSET 15
|
|
#define GPIO29_OINV_MASK 0x00008000
|
|
#define GPIO29_OPOS_OFFSET 14
|
|
#define GPIO29_OPOS_MASK 0x00004000
|
|
#define GPIO29_ONEG_OFFSET 13
|
|
#define GPIO29_ONEG_MASK 0x00002000
|
|
#define GPIO29_IPOS_OFFSET 12
|
|
#define GPIO29_IPOS_MASK 0x00001000
|
|
#define GPIO29_INEG_OFFSET 11
|
|
#define GPIO29_INEG_MASK 0x00000800
|
|
#define GPIO29_ORE_OFFSET 10
|
|
#define GPIO29_ORE_MASK 0x00000400
|
|
#define GPIO29_IRE_OFFSET 9
|
|
#define GPIO29_IRE_MASK 0x00000200
|
|
#define GPIO29_FUNC_WPU_OFFSET 8
|
|
#define GPIO29_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO29_FUNC_WPD_OFFSET 7
|
|
#define GPIO29_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO29_FUNC_SEL_OFFSET 4
|
|
#define GPIO29_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO29_SLP_WPU_OFFSET 3
|
|
#define GPIO29_SLP_WPU_MASK 0x00000008
|
|
#define GPIO29_SLP_WPD_OFFSET 2
|
|
#define GPIO29_SLP_WPD_MASK 0x00000004
|
|
#define GPIO29_SLP_IE_OFFSET 1
|
|
#define GPIO29_SLP_IE_MASK 0x00000002
|
|
#define GPIO29_SLP_OE_OFFSET 0
|
|
#define GPIO29_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO30_PIN_CFG_ADDR 0x7c
|
|
#define GPIO30_SEC_OFFSET 21
|
|
#define GPIO30_SEC_MASK 0x00200000
|
|
#define GPIO30_DRV_OFFSET 19
|
|
#define GPIO30_DRV_MASK 0x00180000
|
|
#define GPIO30_SLP_SEL_OFFSET 18
|
|
#define GPIO30_SLP_SEL_MASK 0x00040000
|
|
#define GPIO30_ODRV_OFFSET 17
|
|
#define GPIO30_ODRV_MASK 0x00020000
|
|
#define GPIO30_IINV_OFFSET 16
|
|
#define GPIO30_IINV_MASK 0x00010000
|
|
#define GPIO30_OINV_OFFSET 15
|
|
#define GPIO30_OINV_MASK 0x00008000
|
|
#define GPIO30_OPOS_OFFSET 14
|
|
#define GPIO30_OPOS_MASK 0x00004000
|
|
#define GPIO30_ONEG_OFFSET 13
|
|
#define GPIO30_ONEG_MASK 0x00002000
|
|
#define GPIO30_IPOS_OFFSET 12
|
|
#define GPIO30_IPOS_MASK 0x00001000
|
|
#define GPIO30_INEG_OFFSET 11
|
|
#define GPIO30_INEG_MASK 0x00000800
|
|
#define GPIO30_ORE_OFFSET 10
|
|
#define GPIO30_ORE_MASK 0x00000400
|
|
#define GPIO30_IRE_OFFSET 9
|
|
#define GPIO30_IRE_MASK 0x00000200
|
|
#define GPIO30_FUNC_WPU_OFFSET 8
|
|
#define GPIO30_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO30_FUNC_WPD_OFFSET 7
|
|
#define GPIO30_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO30_FUNC_SEL_OFFSET 4
|
|
#define GPIO30_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO30_SLP_WPU_OFFSET 3
|
|
#define GPIO30_SLP_WPU_MASK 0x00000008
|
|
#define GPIO30_SLP_WPD_OFFSET 2
|
|
#define GPIO30_SLP_WPD_MASK 0x00000004
|
|
#define GPIO30_SLP_IE_OFFSET 1
|
|
#define GPIO30_SLP_IE_MASK 0x00000002
|
|
#define GPIO30_SLP_OE_OFFSET 0
|
|
#define GPIO30_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO31_PIN_CFG_ADDR 0x80
|
|
#define GPIO31_SEC_OFFSET 21
|
|
#define GPIO31_SEC_MASK 0x00200000
|
|
#define GPIO31_DRV_OFFSET 19
|
|
#define GPIO31_DRV_MASK 0x00180000
|
|
#define GPIO31_SLP_SEL_OFFSET 18
|
|
#define GPIO31_SLP_SEL_MASK 0x00040000
|
|
#define GPIO31_ODRV_OFFSET 17
|
|
#define GPIO31_ODRV_MASK 0x00020000
|
|
#define GPIO31_IINV_OFFSET 16
|
|
#define GPIO31_IINV_MASK 0x00010000
|
|
#define GPIO31_OINV_OFFSET 15
|
|
#define GPIO31_OINV_MASK 0x00008000
|
|
#define GPIO31_OPOS_OFFSET 14
|
|
#define GPIO31_OPOS_MASK 0x00004000
|
|
#define GPIO31_ONEG_OFFSET 13
|
|
#define GPIO31_ONEG_MASK 0x00002000
|
|
#define GPIO31_IPOS_OFFSET 12
|
|
#define GPIO31_IPOS_MASK 0x00001000
|
|
#define GPIO31_INEG_OFFSET 11
|
|
#define GPIO31_INEG_MASK 0x00000800
|
|
#define GPIO31_ORE_OFFSET 10
|
|
#define GPIO31_ORE_MASK 0x00000400
|
|
#define GPIO31_IRE_OFFSET 9
|
|
#define GPIO31_IRE_MASK 0x00000200
|
|
#define GPIO31_FUNC_WPU_OFFSET 8
|
|
#define GPIO31_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO31_FUNC_WPD_OFFSET 7
|
|
#define GPIO31_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO31_FUNC_SEL_OFFSET 4
|
|
#define GPIO31_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO31_SLP_WPU_OFFSET 3
|
|
#define GPIO31_SLP_WPU_MASK 0x00000008
|
|
#define GPIO31_SLP_WPD_OFFSET 2
|
|
#define GPIO31_SLP_WPD_MASK 0x00000004
|
|
#define GPIO31_SLP_IE_OFFSET 1
|
|
#define GPIO31_SLP_IE_MASK 0x00000002
|
|
#define GPIO31_SLP_OE_OFFSET 0
|
|
#define GPIO31_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO32_PIN_CFG_ADDR 0x84
|
|
#define GPIO32_SEC_OFFSET 21
|
|
#define GPIO32_SEC_MASK 0x00200000
|
|
#define GPIO32_DRV_OFFSET 19
|
|
#define GPIO32_DRV_MASK 0x00180000
|
|
#define GPIO32_SLP_SEL_OFFSET 18
|
|
#define GPIO32_SLP_SEL_MASK 0x00040000
|
|
#define GPIO32_ODRV_OFFSET 17
|
|
#define GPIO32_ODRV_MASK 0x00020000
|
|
#define GPIO32_IINV_OFFSET 16
|
|
#define GPIO32_IINV_MASK 0x00010000
|
|
#define GPIO32_OINV_OFFSET 15
|
|
#define GPIO32_OINV_MASK 0x00008000
|
|
#define GPIO32_OPOS_OFFSET 14
|
|
#define GPIO32_OPOS_MASK 0x00004000
|
|
#define GPIO32_ONEG_OFFSET 13
|
|
#define GPIO32_ONEG_MASK 0x00002000
|
|
#define GPIO32_IPOS_OFFSET 12
|
|
#define GPIO32_IPOS_MASK 0x00001000
|
|
#define GPIO32_INEG_OFFSET 11
|
|
#define GPIO32_INEG_MASK 0x00000800
|
|
#define GPIO32_ORE_OFFSET 10
|
|
#define GPIO32_ORE_MASK 0x00000400
|
|
#define GPIO32_IRE_OFFSET 9
|
|
#define GPIO32_IRE_MASK 0x00000200
|
|
#define GPIO32_FUNC_WPU_OFFSET 8
|
|
#define GPIO32_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO32_FUNC_WPD_OFFSET 7
|
|
#define GPIO32_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO32_FUNC_SEL_OFFSET 4
|
|
#define GPIO32_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO32_SLP_WPU_OFFSET 3
|
|
#define GPIO32_SLP_WPU_MASK 0x00000008
|
|
#define GPIO32_SLP_WPD_OFFSET 2
|
|
#define GPIO32_SLP_WPD_MASK 0x00000004
|
|
#define GPIO32_SLP_IE_OFFSET 1
|
|
#define GPIO32_SLP_IE_MASK 0x00000002
|
|
#define GPIO32_SLP_OE_OFFSET 0
|
|
#define GPIO32_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO33_PIN_CFG_ADDR 0x88
|
|
#define GPIO33_SEC_OFFSET 21
|
|
#define GPIO33_SEC_MASK 0x00200000
|
|
#define GPIO33_DRV_OFFSET 19
|
|
#define GPIO33_DRV_MASK 0x00180000
|
|
#define GPIO33_SLP_SEL_OFFSET 18
|
|
#define GPIO33_SLP_SEL_MASK 0x00040000
|
|
#define GPIO33_ODRV_OFFSET 17
|
|
#define GPIO33_ODRV_MASK 0x00020000
|
|
#define GPIO33_IINV_OFFSET 16
|
|
#define GPIO33_IINV_MASK 0x00010000
|
|
#define GPIO33_OINV_OFFSET 15
|
|
#define GPIO33_OINV_MASK 0x00008000
|
|
#define GPIO33_OPOS_OFFSET 14
|
|
#define GPIO33_OPOS_MASK 0x00004000
|
|
#define GPIO33_ONEG_OFFSET 13
|
|
#define GPIO33_ONEG_MASK 0x00002000
|
|
#define GPIO33_IPOS_OFFSET 12
|
|
#define GPIO33_IPOS_MASK 0x00001000
|
|
#define GPIO33_INEG_OFFSET 11
|
|
#define GPIO33_INEG_MASK 0x00000800
|
|
#define GPIO33_ORE_OFFSET 10
|
|
#define GPIO33_ORE_MASK 0x00000400
|
|
#define GPIO33_IRE_OFFSET 9
|
|
#define GPIO33_IRE_MASK 0x00000200
|
|
#define GPIO33_FUNC_WPU_OFFSET 8
|
|
#define GPIO33_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO33_FUNC_WPD_OFFSET 7
|
|
#define GPIO33_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO33_FUNC_SEL_OFFSET 4
|
|
#define GPIO33_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO33_SLP_WPU_OFFSET 3
|
|
#define GPIO33_SLP_WPU_MASK 0x00000008
|
|
#define GPIO33_SLP_WPD_OFFSET 2
|
|
#define GPIO33_SLP_WPD_MASK 0x00000004
|
|
#define GPIO33_SLP_IE_OFFSET 1
|
|
#define GPIO33_SLP_IE_MASK 0x00000002
|
|
#define GPIO33_SLP_OE_OFFSET 0
|
|
#define GPIO33_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO34_PIN_CFG_ADDR 0x8c
|
|
#define GPIO34_SEC_OFFSET 21
|
|
#define GPIO34_SEC_MASK 0x00200000
|
|
#define GPIO34_DRV_OFFSET 19
|
|
#define GPIO34_DRV_MASK 0x00180000
|
|
#define GPIO34_SLP_SEL_OFFSET 18
|
|
#define GPIO34_SLP_SEL_MASK 0x00040000
|
|
#define GPIO34_ODRV_OFFSET 17
|
|
#define GPIO34_ODRV_MASK 0x00020000
|
|
#define GPIO34_IINV_OFFSET 16
|
|
#define GPIO34_IINV_MASK 0x00010000
|
|
#define GPIO34_OINV_OFFSET 15
|
|
#define GPIO34_OINV_MASK 0x00008000
|
|
#define GPIO34_OPOS_OFFSET 14
|
|
#define GPIO34_OPOS_MASK 0x00004000
|
|
#define GPIO34_ONEG_OFFSET 13
|
|
#define GPIO34_ONEG_MASK 0x00002000
|
|
#define GPIO34_IPOS_OFFSET 12
|
|
#define GPIO34_IPOS_MASK 0x00001000
|
|
#define GPIO34_INEG_OFFSET 11
|
|
#define GPIO34_INEG_MASK 0x00000800
|
|
#define GPIO34_ORE_OFFSET 10
|
|
#define GPIO34_ORE_MASK 0x00000400
|
|
#define GPIO34_IRE_OFFSET 9
|
|
#define GPIO34_IRE_MASK 0x00000200
|
|
#define GPIO34_FUNC_WPU_OFFSET 8
|
|
#define GPIO34_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO34_FUNC_WPD_OFFSET 7
|
|
#define GPIO34_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO34_FUNC_SEL_OFFSET 4
|
|
#define GPIO34_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO34_SLP_WPU_OFFSET 3
|
|
#define GPIO34_SLP_WPU_MASK 0x00000008
|
|
#define GPIO34_SLP_WPD_OFFSET 2
|
|
#define GPIO34_SLP_WPD_MASK 0x00000004
|
|
#define GPIO34_SLP_IE_OFFSET 1
|
|
#define GPIO34_SLP_IE_MASK 0x00000002
|
|
#define GPIO34_SLP_OE_OFFSET 0
|
|
#define GPIO34_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO35_PIN_CFG_ADDR 0x90
|
|
#define GPIO35_SEC_OFFSET 21
|
|
#define GPIO35_SEC_MASK 0x00200000
|
|
#define GPIO35_DRV_OFFSET 19
|
|
#define GPIO35_DRV_MASK 0x00180000
|
|
#define GPIO35_SLP_SEL_OFFSET 18
|
|
#define GPIO35_SLP_SEL_MASK 0x00040000
|
|
#define GPIO35_ODRV_OFFSET 17
|
|
#define GPIO35_ODRV_MASK 0x00020000
|
|
#define GPIO35_IINV_OFFSET 16
|
|
#define GPIO35_IINV_MASK 0x00010000
|
|
#define GPIO35_OINV_OFFSET 15
|
|
#define GPIO35_OINV_MASK 0x00008000
|
|
#define GPIO35_OPOS_OFFSET 14
|
|
#define GPIO35_OPOS_MASK 0x00004000
|
|
#define GPIO35_ONEG_OFFSET 13
|
|
#define GPIO35_ONEG_MASK 0x00002000
|
|
#define GPIO35_IPOS_OFFSET 12
|
|
#define GPIO35_IPOS_MASK 0x00001000
|
|
#define GPIO35_INEG_OFFSET 11
|
|
#define GPIO35_INEG_MASK 0x00000800
|
|
#define GPIO35_ORE_OFFSET 10
|
|
#define GPIO35_ORE_MASK 0x00000400
|
|
#define GPIO35_IRE_OFFSET 9
|
|
#define GPIO35_IRE_MASK 0x00000200
|
|
#define GPIO35_FUNC_WPU_OFFSET 8
|
|
#define GPIO35_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO35_FUNC_WPD_OFFSET 7
|
|
#define GPIO35_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO35_FUNC_SEL_OFFSET 4
|
|
#define GPIO35_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO35_SLP_WPU_OFFSET 3
|
|
#define GPIO35_SLP_WPU_MASK 0x00000008
|
|
#define GPIO35_SLP_WPD_OFFSET 2
|
|
#define GPIO35_SLP_WPD_MASK 0x00000004
|
|
#define GPIO35_SLP_IE_OFFSET 1
|
|
#define GPIO35_SLP_IE_MASK 0x00000002
|
|
#define GPIO35_SLP_OE_OFFSET 0
|
|
#define GPIO35_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO36_PIN_CFG_ADDR 0x94
|
|
#define GPIO36_SEC_OFFSET 21
|
|
#define GPIO36_SEC_MASK 0x00200000
|
|
#define GPIO36_DRV_OFFSET 19
|
|
#define GPIO36_DRV_MASK 0x00180000
|
|
#define GPIO36_SLP_SEL_OFFSET 18
|
|
#define GPIO36_SLP_SEL_MASK 0x00040000
|
|
#define GPIO36_ODRV_OFFSET 17
|
|
#define GPIO36_ODRV_MASK 0x00020000
|
|
#define GPIO36_IINV_OFFSET 16
|
|
#define GPIO36_IINV_MASK 0x00010000
|
|
#define GPIO36_OINV_OFFSET 15
|
|
#define GPIO36_OINV_MASK 0x00008000
|
|
#define GPIO36_OPOS_OFFSET 14
|
|
#define GPIO36_OPOS_MASK 0x00004000
|
|
#define GPIO36_ONEG_OFFSET 13
|
|
#define GPIO36_ONEG_MASK 0x00002000
|
|
#define GPIO36_IPOS_OFFSET 12
|
|
#define GPIO36_IPOS_MASK 0x00001000
|
|
#define GPIO36_INEG_OFFSET 11
|
|
#define GPIO36_INEG_MASK 0x00000800
|
|
#define GPIO36_ORE_OFFSET 10
|
|
#define GPIO36_ORE_MASK 0x00000400
|
|
#define GPIO36_IRE_OFFSET 9
|
|
#define GPIO36_IRE_MASK 0x00000200
|
|
#define GPIO36_FUNC_WPU_OFFSET 8
|
|
#define GPIO36_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO36_FUNC_WPD_OFFSET 7
|
|
#define GPIO36_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO36_FUNC_SEL_OFFSET 4
|
|
#define GPIO36_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO36_SLP_WPU_OFFSET 3
|
|
#define GPIO36_SLP_WPU_MASK 0x00000008
|
|
#define GPIO36_SLP_WPD_OFFSET 2
|
|
#define GPIO36_SLP_WPD_MASK 0x00000004
|
|
#define GPIO36_SLP_IE_OFFSET 1
|
|
#define GPIO36_SLP_IE_MASK 0x00000002
|
|
#define GPIO36_SLP_OE_OFFSET 0
|
|
#define GPIO36_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO37_PIN_CFG_ADDR 0x98
|
|
#define GPIO37_SEC_OFFSET 21
|
|
#define GPIO37_SEC_MASK 0x00200000
|
|
#define GPIO37_DRV_OFFSET 19
|
|
#define GPIO37_DRV_MASK 0x00180000
|
|
#define GPIO37_SLP_SEL_OFFSET 18
|
|
#define GPIO37_SLP_SEL_MASK 0x00040000
|
|
#define GPIO37_ODRV_OFFSET 17
|
|
#define GPIO37_ODRV_MASK 0x00020000
|
|
#define GPIO37_IINV_OFFSET 16
|
|
#define GPIO37_IINV_MASK 0x00010000
|
|
#define GPIO37_OINV_OFFSET 15
|
|
#define GPIO37_OINV_MASK 0x00008000
|
|
#define GPIO37_OPOS_OFFSET 14
|
|
#define GPIO37_OPOS_MASK 0x00004000
|
|
#define GPIO37_ONEG_OFFSET 13
|
|
#define GPIO37_ONEG_MASK 0x00002000
|
|
#define GPIO37_IPOS_OFFSET 12
|
|
#define GPIO37_IPOS_MASK 0x00001000
|
|
#define GPIO37_INEG_OFFSET 11
|
|
#define GPIO37_INEG_MASK 0x00000800
|
|
#define GPIO37_ORE_OFFSET 10
|
|
#define GPIO37_ORE_MASK 0x00000400
|
|
#define GPIO37_IRE_OFFSET 9
|
|
#define GPIO37_IRE_MASK 0x00000200
|
|
#define GPIO37_FUNC_WPU_OFFSET 8
|
|
#define GPIO37_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO37_FUNC_WPD_OFFSET 7
|
|
#define GPIO37_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO37_FUNC_SEL_OFFSET 4
|
|
#define GPIO37_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO37_SLP_WPU_OFFSET 3
|
|
#define GPIO37_SLP_WPU_MASK 0x00000008
|
|
#define GPIO37_SLP_WPD_OFFSET 2
|
|
#define GPIO37_SLP_WPD_MASK 0x00000004
|
|
#define GPIO37_SLP_IE_OFFSET 1
|
|
#define GPIO37_SLP_IE_MASK 0x00000002
|
|
#define GPIO37_SLP_OE_OFFSET 0
|
|
#define GPIO37_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO38_PIN_CFG_ADDR 0x9c
|
|
#define GPIO38_SEC_OFFSET 21
|
|
#define GPIO38_SEC_MASK 0x00200000
|
|
#define GPIO38_DRV_OFFSET 19
|
|
#define GPIO38_DRV_MASK 0x00180000
|
|
#define GPIO38_SLP_SEL_OFFSET 18
|
|
#define GPIO38_SLP_SEL_MASK 0x00040000
|
|
#define GPIO38_ODRV_OFFSET 17
|
|
#define GPIO38_ODRV_MASK 0x00020000
|
|
#define GPIO38_IINV_OFFSET 16
|
|
#define GPIO38_IINV_MASK 0x00010000
|
|
#define GPIO38_OINV_OFFSET 15
|
|
#define GPIO38_OINV_MASK 0x00008000
|
|
#define GPIO38_OPOS_OFFSET 14
|
|
#define GPIO38_OPOS_MASK 0x00004000
|
|
#define GPIO38_ONEG_OFFSET 13
|
|
#define GPIO38_ONEG_MASK 0x00002000
|
|
#define GPIO38_IPOS_OFFSET 12
|
|
#define GPIO38_IPOS_MASK 0x00001000
|
|
#define GPIO38_INEG_OFFSET 11
|
|
#define GPIO38_INEG_MASK 0x00000800
|
|
#define GPIO38_ORE_OFFSET 10
|
|
#define GPIO38_ORE_MASK 0x00000400
|
|
#define GPIO38_IRE_OFFSET 9
|
|
#define GPIO38_IRE_MASK 0x00000200
|
|
#define GPIO38_FUNC_WPU_OFFSET 8
|
|
#define GPIO38_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO38_FUNC_WPD_OFFSET 7
|
|
#define GPIO38_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO38_FUNC_SEL_OFFSET 4
|
|
#define GPIO38_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO38_SLP_WPU_OFFSET 3
|
|
#define GPIO38_SLP_WPU_MASK 0x00000008
|
|
#define GPIO38_SLP_WPD_OFFSET 2
|
|
#define GPIO38_SLP_WPD_MASK 0x00000004
|
|
#define GPIO38_SLP_IE_OFFSET 1
|
|
#define GPIO38_SLP_IE_MASK 0x00000002
|
|
#define GPIO38_SLP_OE_OFFSET 0
|
|
#define GPIO38_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO39_PIN_CFG_ADDR 0xa0
|
|
#define GPIO39_SEC_OFFSET 21
|
|
#define GPIO39_SEC_MASK 0x00200000
|
|
#define GPIO39_DRV_OFFSET 19
|
|
#define GPIO39_DRV_MASK 0x00180000
|
|
#define GPIO39_SLP_SEL_OFFSET 18
|
|
#define GPIO39_SLP_SEL_MASK 0x00040000
|
|
#define GPIO39_ODRV_OFFSET 17
|
|
#define GPIO39_ODRV_MASK 0x00020000
|
|
#define GPIO39_IINV_OFFSET 16
|
|
#define GPIO39_IINV_MASK 0x00010000
|
|
#define GPIO39_OINV_OFFSET 15
|
|
#define GPIO39_OINV_MASK 0x00008000
|
|
#define GPIO39_OPOS_OFFSET 14
|
|
#define GPIO39_OPOS_MASK 0x00004000
|
|
#define GPIO39_ONEG_OFFSET 13
|
|
#define GPIO39_ONEG_MASK 0x00002000
|
|
#define GPIO39_IPOS_OFFSET 12
|
|
#define GPIO39_IPOS_MASK 0x00001000
|
|
#define GPIO39_INEG_OFFSET 11
|
|
#define GPIO39_INEG_MASK 0x00000800
|
|
#define GPIO39_ORE_OFFSET 10
|
|
#define GPIO39_ORE_MASK 0x00000400
|
|
#define GPIO39_IRE_OFFSET 9
|
|
#define GPIO39_IRE_MASK 0x00000200
|
|
#define GPIO39_FUNC_WPU_OFFSET 8
|
|
#define GPIO39_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO39_FUNC_WPD_OFFSET 7
|
|
#define GPIO39_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO39_FUNC_SEL_OFFSET 4
|
|
#define GPIO39_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO39_SLP_WPU_OFFSET 3
|
|
#define GPIO39_SLP_WPU_MASK 0x00000008
|
|
#define GPIO39_SLP_WPD_OFFSET 2
|
|
#define GPIO39_SLP_WPD_MASK 0x00000004
|
|
#define GPIO39_SLP_IE_OFFSET 1
|
|
#define GPIO39_SLP_IE_MASK 0x00000002
|
|
#define GPIO39_SLP_OE_OFFSET 0
|
|
#define GPIO39_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO40_PIN_CFG_ADDR 0xa4
|
|
#define GPIO40_SEC_OFFSET 21
|
|
#define GPIO40_SEC_MASK 0x00200000
|
|
#define GPIO40_DRV_OFFSET 19
|
|
#define GPIO40_DRV_MASK 0x00180000
|
|
#define GPIO40_SLP_SEL_OFFSET 18
|
|
#define GPIO40_SLP_SEL_MASK 0x00040000
|
|
#define GPIO40_ODRV_OFFSET 17
|
|
#define GPIO40_ODRV_MASK 0x00020000
|
|
#define GPIO40_IINV_OFFSET 16
|
|
#define GPIO40_IINV_MASK 0x00010000
|
|
#define GPIO40_OINV_OFFSET 15
|
|
#define GPIO40_OINV_MASK 0x00008000
|
|
#define GPIO40_OPOS_OFFSET 14
|
|
#define GPIO40_OPOS_MASK 0x00004000
|
|
#define GPIO40_ONEG_OFFSET 13
|
|
#define GPIO40_ONEG_MASK 0x00002000
|
|
#define GPIO40_IPOS_OFFSET 12
|
|
#define GPIO40_IPOS_MASK 0x00001000
|
|
#define GPIO40_INEG_OFFSET 11
|
|
#define GPIO40_INEG_MASK 0x00000800
|
|
#define GPIO40_ORE_OFFSET 10
|
|
#define GPIO40_ORE_MASK 0x00000400
|
|
#define GPIO40_IRE_OFFSET 9
|
|
#define GPIO40_IRE_MASK 0x00000200
|
|
#define GPIO40_FUNC_WPU_OFFSET 8
|
|
#define GPIO40_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO40_FUNC_WPD_OFFSET 7
|
|
#define GPIO40_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO40_FUNC_SEL_OFFSET 4
|
|
#define GPIO40_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO40_SLP_WPU_OFFSET 3
|
|
#define GPIO40_SLP_WPU_MASK 0x00000008
|
|
#define GPIO40_SLP_WPD_OFFSET 2
|
|
#define GPIO40_SLP_WPD_MASK 0x00000004
|
|
#define GPIO40_SLP_IE_OFFSET 1
|
|
#define GPIO40_SLP_IE_MASK 0x00000002
|
|
#define GPIO40_SLP_OE_OFFSET 0
|
|
#define GPIO40_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO41_PIN_CFG_ADDR 0xa8
|
|
#define GPIO41_SEC_OFFSET 21
|
|
#define GPIO41_SEC_MASK 0x00200000
|
|
#define GPIO41_DRV_OFFSET 19
|
|
#define GPIO41_DRV_MASK 0x00180000
|
|
#define GPIO41_SLP_SEL_OFFSET 18
|
|
#define GPIO41_SLP_SEL_MASK 0x00040000
|
|
#define GPIO41_ODRV_OFFSET 17
|
|
#define GPIO41_ODRV_MASK 0x00020000
|
|
#define GPIO41_IINV_OFFSET 16
|
|
#define GPIO41_IINV_MASK 0x00010000
|
|
#define GPIO41_OINV_OFFSET 15
|
|
#define GPIO41_OINV_MASK 0x00008000
|
|
#define GPIO41_OPOS_OFFSET 14
|
|
#define GPIO41_OPOS_MASK 0x00004000
|
|
#define GPIO41_ONEG_OFFSET 13
|
|
#define GPIO41_ONEG_MASK 0x00002000
|
|
#define GPIO41_IPOS_OFFSET 12
|
|
#define GPIO41_IPOS_MASK 0x00001000
|
|
#define GPIO41_INEG_OFFSET 11
|
|
#define GPIO41_INEG_MASK 0x00000800
|
|
#define GPIO41_ORE_OFFSET 10
|
|
#define GPIO41_ORE_MASK 0x00000400
|
|
#define GPIO41_IRE_OFFSET 9
|
|
#define GPIO41_IRE_MASK 0x00000200
|
|
#define GPIO41_FUNC_WPU_OFFSET 8
|
|
#define GPIO41_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO41_FUNC_WPD_OFFSET 7
|
|
#define GPIO41_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO41_FUNC_SEL_OFFSET 4
|
|
#define GPIO41_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO41_SLP_WPU_OFFSET 3
|
|
#define GPIO41_SLP_WPU_MASK 0x00000008
|
|
#define GPIO41_SLP_WPD_OFFSET 2
|
|
#define GPIO41_SLP_WPD_MASK 0x00000004
|
|
#define GPIO41_SLP_IE_OFFSET 1
|
|
#define GPIO41_SLP_IE_MASK 0x00000002
|
|
#define GPIO41_SLP_OE_OFFSET 0
|
|
#define GPIO41_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO42_PIN_CFG_ADDR 0xac
|
|
#define GPIO42_SEC_OFFSET 21
|
|
#define GPIO42_SEC_MASK 0x00200000
|
|
#define GPIO42_DRV_OFFSET 19
|
|
#define GPIO42_DRV_MASK 0x00180000
|
|
#define GPIO42_SLP_SEL_OFFSET 18
|
|
#define GPIO42_SLP_SEL_MASK 0x00040000
|
|
#define GPIO42_ODRV_OFFSET 17
|
|
#define GPIO42_ODRV_MASK 0x00020000
|
|
#define GPIO42_IINV_OFFSET 16
|
|
#define GPIO42_IINV_MASK 0x00010000
|
|
#define GPIO42_OINV_OFFSET 15
|
|
#define GPIO42_OINV_MASK 0x00008000
|
|
#define GPIO42_OPOS_OFFSET 14
|
|
#define GPIO42_OPOS_MASK 0x00004000
|
|
#define GPIO42_ONEG_OFFSET 13
|
|
#define GPIO42_ONEG_MASK 0x00002000
|
|
#define GPIO42_IPOS_OFFSET 12
|
|
#define GPIO42_IPOS_MASK 0x00001000
|
|
#define GPIO42_INEG_OFFSET 11
|
|
#define GPIO42_INEG_MASK 0x00000800
|
|
#define GPIO42_ORE_OFFSET 10
|
|
#define GPIO42_ORE_MASK 0x00000400
|
|
#define GPIO42_IRE_OFFSET 9
|
|
#define GPIO42_IRE_MASK 0x00000200
|
|
#define GPIO42_FUNC_WPU_OFFSET 8
|
|
#define GPIO42_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO42_FUNC_WPD_OFFSET 7
|
|
#define GPIO42_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO42_FUNC_SEL_OFFSET 4
|
|
#define GPIO42_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO42_SLP_WPU_OFFSET 3
|
|
#define GPIO42_SLP_WPU_MASK 0x00000008
|
|
#define GPIO42_SLP_WPD_OFFSET 2
|
|
#define GPIO42_SLP_WPD_MASK 0x00000004
|
|
#define GPIO42_SLP_IE_OFFSET 1
|
|
#define GPIO42_SLP_IE_MASK 0x00000002
|
|
#define GPIO42_SLP_OE_OFFSET 0
|
|
#define GPIO42_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO43_PIN_CFG_ADDR 0xb0
|
|
#define GPIO43_SEC_OFFSET 21
|
|
#define GPIO43_SEC_MASK 0x00200000
|
|
#define GPIO43_DRV_OFFSET 19
|
|
#define GPIO43_DRV_MASK 0x00180000
|
|
#define GPIO43_SLP_SEL_OFFSET 18
|
|
#define GPIO43_SLP_SEL_MASK 0x00040000
|
|
#define GPIO43_ODRV_OFFSET 17
|
|
#define GPIO43_ODRV_MASK 0x00020000
|
|
#define GPIO43_IINV_OFFSET 16
|
|
#define GPIO43_IINV_MASK 0x00010000
|
|
#define GPIO43_OINV_OFFSET 15
|
|
#define GPIO43_OINV_MASK 0x00008000
|
|
#define GPIO43_OPOS_OFFSET 14
|
|
#define GPIO43_OPOS_MASK 0x00004000
|
|
#define GPIO43_ONEG_OFFSET 13
|
|
#define GPIO43_ONEG_MASK 0x00002000
|
|
#define GPIO43_IPOS_OFFSET 12
|
|
#define GPIO43_IPOS_MASK 0x00001000
|
|
#define GPIO43_INEG_OFFSET 11
|
|
#define GPIO43_INEG_MASK 0x00000800
|
|
#define GPIO43_ORE_OFFSET 10
|
|
#define GPIO43_ORE_MASK 0x00000400
|
|
#define GPIO43_IRE_OFFSET 9
|
|
#define GPIO43_IRE_MASK 0x00000200
|
|
#define GPIO43_FUNC_WPU_OFFSET 8
|
|
#define GPIO43_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO43_FUNC_WPD_OFFSET 7
|
|
#define GPIO43_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO43_FUNC_SEL_OFFSET 4
|
|
#define GPIO43_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO43_SLP_WPU_OFFSET 3
|
|
#define GPIO43_SLP_WPU_MASK 0x00000008
|
|
#define GPIO43_SLP_WPD_OFFSET 2
|
|
#define GPIO43_SLP_WPD_MASK 0x00000004
|
|
#define GPIO43_SLP_IE_OFFSET 1
|
|
#define GPIO43_SLP_IE_MASK 0x00000002
|
|
#define GPIO43_SLP_OE_OFFSET 0
|
|
#define GPIO43_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO44_PIN_CFG_ADDR 0xb4
|
|
#define GPIO44_SEC_OFFSET 21
|
|
#define GPIO44_SEC_MASK 0x00200000
|
|
#define GPIO44_DRV_OFFSET 19
|
|
#define GPIO44_DRV_MASK 0x00180000
|
|
#define GPIO44_SLP_SEL_OFFSET 18
|
|
#define GPIO44_SLP_SEL_MASK 0x00040000
|
|
#define GPIO44_ODRV_OFFSET 17
|
|
#define GPIO44_ODRV_MASK 0x00020000
|
|
#define GPIO44_IINV_OFFSET 16
|
|
#define GPIO44_IINV_MASK 0x00010000
|
|
#define GPIO44_OINV_OFFSET 15
|
|
#define GPIO44_OINV_MASK 0x00008000
|
|
#define GPIO44_OPOS_OFFSET 14
|
|
#define GPIO44_OPOS_MASK 0x00004000
|
|
#define GPIO44_ONEG_OFFSET 13
|
|
#define GPIO44_ONEG_MASK 0x00002000
|
|
#define GPIO44_IPOS_OFFSET 12
|
|
#define GPIO44_IPOS_MASK 0x00001000
|
|
#define GPIO44_INEG_OFFSET 11
|
|
#define GPIO44_INEG_MASK 0x00000800
|
|
#define GPIO44_ORE_OFFSET 10
|
|
#define GPIO44_ORE_MASK 0x00000400
|
|
#define GPIO44_IRE_OFFSET 9
|
|
#define GPIO44_IRE_MASK 0x00000200
|
|
#define GPIO44_FUNC_WPU_OFFSET 8
|
|
#define GPIO44_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO44_FUNC_WPD_OFFSET 7
|
|
#define GPIO44_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO44_FUNC_SEL_OFFSET 4
|
|
#define GPIO44_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO44_SLP_WPU_OFFSET 3
|
|
#define GPIO44_SLP_WPU_MASK 0x00000008
|
|
#define GPIO44_SLP_WPD_OFFSET 2
|
|
#define GPIO44_SLP_WPD_MASK 0x00000004
|
|
#define GPIO44_SLP_IE_OFFSET 1
|
|
#define GPIO44_SLP_IE_MASK 0x00000002
|
|
#define GPIO44_SLP_OE_OFFSET 0
|
|
#define GPIO44_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO45_PIN_CFG_ADDR 0xb8
|
|
#define GPIO45_SEC_OFFSET 21
|
|
#define GPIO45_SEC_MASK 0x00200000
|
|
#define GPIO45_DRV_OFFSET 19
|
|
#define GPIO45_DRV_MASK 0x00180000
|
|
#define GPIO45_SLP_SEL_OFFSET 18
|
|
#define GPIO45_SLP_SEL_MASK 0x00040000
|
|
#define GPIO45_ODRV_OFFSET 17
|
|
#define GPIO45_ODRV_MASK 0x00020000
|
|
#define GPIO45_IINV_OFFSET 16
|
|
#define GPIO45_IINV_MASK 0x00010000
|
|
#define GPIO45_OINV_OFFSET 15
|
|
#define GPIO45_OINV_MASK 0x00008000
|
|
#define GPIO45_OPOS_OFFSET 14
|
|
#define GPIO45_OPOS_MASK 0x00004000
|
|
#define GPIO45_ONEG_OFFSET 13
|
|
#define GPIO45_ONEG_MASK 0x00002000
|
|
#define GPIO45_IPOS_OFFSET 12
|
|
#define GPIO45_IPOS_MASK 0x00001000
|
|
#define GPIO45_INEG_OFFSET 11
|
|
#define GPIO45_INEG_MASK 0x00000800
|
|
#define GPIO45_ORE_OFFSET 10
|
|
#define GPIO45_ORE_MASK 0x00000400
|
|
#define GPIO45_IRE_OFFSET 9
|
|
#define GPIO45_IRE_MASK 0x00000200
|
|
#define GPIO45_FUNC_WPU_OFFSET 8
|
|
#define GPIO45_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO45_FUNC_WPD_OFFSET 7
|
|
#define GPIO45_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO45_FUNC_SEL_OFFSET 4
|
|
#define GPIO45_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO45_SLP_WPU_OFFSET 3
|
|
#define GPIO45_SLP_WPU_MASK 0x00000008
|
|
#define GPIO45_SLP_WPD_OFFSET 2
|
|
#define GPIO45_SLP_WPD_MASK 0x00000004
|
|
#define GPIO45_SLP_IE_OFFSET 1
|
|
#define GPIO45_SLP_IE_MASK 0x00000002
|
|
#define GPIO45_SLP_OE_OFFSET 0
|
|
#define GPIO45_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO46_PIN_CFG_ADDR 0xbc
|
|
#define GPIO46_SEC_OFFSET 21
|
|
#define GPIO46_SEC_MASK 0x00200000
|
|
#define GPIO46_DRV_OFFSET 19
|
|
#define GPIO46_DRV_MASK 0x00180000
|
|
#define GPIO46_SLP_SEL_OFFSET 18
|
|
#define GPIO46_SLP_SEL_MASK 0x00040000
|
|
#define GPIO46_ODRV_OFFSET 17
|
|
#define GPIO46_ODRV_MASK 0x00020000
|
|
#define GPIO46_IINV_OFFSET 16
|
|
#define GPIO46_IINV_MASK 0x00010000
|
|
#define GPIO46_OINV_OFFSET 15
|
|
#define GPIO46_OINV_MASK 0x00008000
|
|
#define GPIO46_OPOS_OFFSET 14
|
|
#define GPIO46_OPOS_MASK 0x00004000
|
|
#define GPIO46_ONEG_OFFSET 13
|
|
#define GPIO46_ONEG_MASK 0x00002000
|
|
#define GPIO46_IPOS_OFFSET 12
|
|
#define GPIO46_IPOS_MASK 0x00001000
|
|
#define GPIO46_INEG_OFFSET 11
|
|
#define GPIO46_INEG_MASK 0x00000800
|
|
#define GPIO46_ORE_OFFSET 10
|
|
#define GPIO46_ORE_MASK 0x00000400
|
|
#define GPIO46_IRE_OFFSET 9
|
|
#define GPIO46_IRE_MASK 0x00000200
|
|
#define GPIO46_FUNC_WPU_OFFSET 8
|
|
#define GPIO46_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO46_FUNC_WPD_OFFSET 7
|
|
#define GPIO46_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO46_FUNC_SEL_OFFSET 4
|
|
#define GPIO46_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO46_SLP_WPU_OFFSET 3
|
|
#define GPIO46_SLP_WPU_MASK 0x00000008
|
|
#define GPIO46_SLP_WPD_OFFSET 2
|
|
#define GPIO46_SLP_WPD_MASK 0x00000004
|
|
#define GPIO46_SLP_IE_OFFSET 1
|
|
#define GPIO46_SLP_IE_MASK 0x00000002
|
|
#define GPIO46_SLP_OE_OFFSET 0
|
|
#define GPIO46_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO47_PIN_CFG_ADDR 0xc0
|
|
#define GPIO47_SEC_OFFSET 21
|
|
#define GPIO47_SEC_MASK 0x00200000
|
|
#define GPIO47_DRV_OFFSET 19
|
|
#define GPIO47_DRV_MASK 0x00180000
|
|
#define GPIO47_SLP_SEL_OFFSET 18
|
|
#define GPIO47_SLP_SEL_MASK 0x00040000
|
|
#define GPIO47_ODRV_OFFSET 17
|
|
#define GPIO47_ODRV_MASK 0x00020000
|
|
#define GPIO47_IINV_OFFSET 16
|
|
#define GPIO47_IINV_MASK 0x00010000
|
|
#define GPIO47_OINV_OFFSET 15
|
|
#define GPIO47_OINV_MASK 0x00008000
|
|
#define GPIO47_OPOS_OFFSET 14
|
|
#define GPIO47_OPOS_MASK 0x00004000
|
|
#define GPIO47_ONEG_OFFSET 13
|
|
#define GPIO47_ONEG_MASK 0x00002000
|
|
#define GPIO47_IPOS_OFFSET 12
|
|
#define GPIO47_IPOS_MASK 0x00001000
|
|
#define GPIO47_INEG_OFFSET 11
|
|
#define GPIO47_INEG_MASK 0x00000800
|
|
#define GPIO47_ORE_OFFSET 10
|
|
#define GPIO47_ORE_MASK 0x00000400
|
|
#define GPIO47_IRE_OFFSET 9
|
|
#define GPIO47_IRE_MASK 0x00000200
|
|
#define GPIO47_FUNC_WPU_OFFSET 8
|
|
#define GPIO47_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO47_FUNC_WPD_OFFSET 7
|
|
#define GPIO47_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO47_FUNC_SEL_OFFSET 4
|
|
#define GPIO47_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO47_SLP_WPU_OFFSET 3
|
|
#define GPIO47_SLP_WPU_MASK 0x00000008
|
|
#define GPIO47_SLP_WPD_OFFSET 2
|
|
#define GPIO47_SLP_WPD_MASK 0x00000004
|
|
#define GPIO47_SLP_IE_OFFSET 1
|
|
#define GPIO47_SLP_IE_MASK 0x00000002
|
|
#define GPIO47_SLP_OE_OFFSET 0
|
|
#define GPIO47_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO48_PIN_CFG_ADDR 0xc4
|
|
#define GPIO48_SEC_OFFSET 21
|
|
#define GPIO48_SEC_MASK 0x00200000
|
|
#define GPIO48_DRV_OFFSET 19
|
|
#define GPIO48_DRV_MASK 0x00180000
|
|
#define GPIO48_SLP_SEL_OFFSET 18
|
|
#define GPIO48_SLP_SEL_MASK 0x00040000
|
|
#define GPIO48_ODRV_OFFSET 17
|
|
#define GPIO48_ODRV_MASK 0x00020000
|
|
#define GPIO48_IINV_OFFSET 16
|
|
#define GPIO48_IINV_MASK 0x00010000
|
|
#define GPIO48_OINV_OFFSET 15
|
|
#define GPIO48_OINV_MASK 0x00008000
|
|
#define GPIO48_OPOS_OFFSET 14
|
|
#define GPIO48_OPOS_MASK 0x00004000
|
|
#define GPIO48_ONEG_OFFSET 13
|
|
#define GPIO48_ONEG_MASK 0x00002000
|
|
#define GPIO48_IPOS_OFFSET 12
|
|
#define GPIO48_IPOS_MASK 0x00001000
|
|
#define GPIO48_INEG_OFFSET 11
|
|
#define GPIO48_INEG_MASK 0x00000800
|
|
#define GPIO48_ORE_OFFSET 10
|
|
#define GPIO48_ORE_MASK 0x00000400
|
|
#define GPIO48_IRE_OFFSET 9
|
|
#define GPIO48_IRE_MASK 0x00000200
|
|
#define GPIO48_FUNC_WPU_OFFSET 8
|
|
#define GPIO48_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO48_FUNC_WPD_OFFSET 7
|
|
#define GPIO48_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO48_FUNC_SEL_OFFSET 4
|
|
#define GPIO48_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO48_SLP_WPU_OFFSET 3
|
|
#define GPIO48_SLP_WPU_MASK 0x00000008
|
|
#define GPIO48_SLP_WPD_OFFSET 2
|
|
#define GPIO48_SLP_WPD_MASK 0x00000004
|
|
#define GPIO48_SLP_IE_OFFSET 1
|
|
#define GPIO48_SLP_IE_MASK 0x00000002
|
|
#define GPIO48_SLP_OE_OFFSET 0
|
|
#define GPIO48_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO49_PIN_CFG_ADDR 0xc8
|
|
#define GPIO49_SEC_OFFSET 21
|
|
#define GPIO49_SEC_MASK 0x00200000
|
|
#define GPIO49_DRV_OFFSET 19
|
|
#define GPIO49_DRV_MASK 0x00180000
|
|
#define GPIO49_SLP_SEL_OFFSET 18
|
|
#define GPIO49_SLP_SEL_MASK 0x00040000
|
|
#define GPIO49_ODRV_OFFSET 17
|
|
#define GPIO49_ODRV_MASK 0x00020000
|
|
#define GPIO49_IINV_OFFSET 16
|
|
#define GPIO49_IINV_MASK 0x00010000
|
|
#define GPIO49_OINV_OFFSET 15
|
|
#define GPIO49_OINV_MASK 0x00008000
|
|
#define GPIO49_OPOS_OFFSET 14
|
|
#define GPIO49_OPOS_MASK 0x00004000
|
|
#define GPIO49_ONEG_OFFSET 13
|
|
#define GPIO49_ONEG_MASK 0x00002000
|
|
#define GPIO49_IPOS_OFFSET 12
|
|
#define GPIO49_IPOS_MASK 0x00001000
|
|
#define GPIO49_INEG_OFFSET 11
|
|
#define GPIO49_INEG_MASK 0x00000800
|
|
#define GPIO49_ORE_OFFSET 10
|
|
#define GPIO49_ORE_MASK 0x00000400
|
|
#define GPIO49_IRE_OFFSET 9
|
|
#define GPIO49_IRE_MASK 0x00000200
|
|
#define GPIO49_FUNC_WPU_OFFSET 8
|
|
#define GPIO49_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO49_FUNC_WPD_OFFSET 7
|
|
#define GPIO49_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO49_FUNC_SEL_OFFSET 4
|
|
#define GPIO49_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO49_SLP_WPU_OFFSET 3
|
|
#define GPIO49_SLP_WPU_MASK 0x00000008
|
|
#define GPIO49_SLP_WPD_OFFSET 2
|
|
#define GPIO49_SLP_WPD_MASK 0x00000004
|
|
#define GPIO49_SLP_IE_OFFSET 1
|
|
#define GPIO49_SLP_IE_MASK 0x00000002
|
|
#define GPIO49_SLP_OE_OFFSET 0
|
|
#define GPIO49_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO50_PIN_CFG_ADDR 0xcc
|
|
#define GPIO50_SEC_OFFSET 21
|
|
#define GPIO50_SEC_MASK 0x00200000
|
|
#define GPIO50_DRV_OFFSET 19
|
|
#define GPIO50_DRV_MASK 0x00180000
|
|
#define GPIO50_SLP_SEL_OFFSET 18
|
|
#define GPIO50_SLP_SEL_MASK 0x00040000
|
|
#define GPIO50_ODRV_OFFSET 17
|
|
#define GPIO50_ODRV_MASK 0x00020000
|
|
#define GPIO50_IINV_OFFSET 16
|
|
#define GPIO50_IINV_MASK 0x00010000
|
|
#define GPIO50_OINV_OFFSET 15
|
|
#define GPIO50_OINV_MASK 0x00008000
|
|
#define GPIO50_OPOS_OFFSET 14
|
|
#define GPIO50_OPOS_MASK 0x00004000
|
|
#define GPIO50_ONEG_OFFSET 13
|
|
#define GPIO50_ONEG_MASK 0x00002000
|
|
#define GPIO50_IPOS_OFFSET 12
|
|
#define GPIO50_IPOS_MASK 0x00001000
|
|
#define GPIO50_INEG_OFFSET 11
|
|
#define GPIO50_INEG_MASK 0x00000800
|
|
#define GPIO50_ORE_OFFSET 10
|
|
#define GPIO50_ORE_MASK 0x00000400
|
|
#define GPIO50_IRE_OFFSET 9
|
|
#define GPIO50_IRE_MASK 0x00000200
|
|
#define GPIO50_FUNC_WPU_OFFSET 8
|
|
#define GPIO50_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO50_FUNC_WPD_OFFSET 7
|
|
#define GPIO50_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO50_FUNC_SEL_OFFSET 4
|
|
#define GPIO50_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO50_SLP_WPU_OFFSET 3
|
|
#define GPIO50_SLP_WPU_MASK 0x00000008
|
|
#define GPIO50_SLP_WPD_OFFSET 2
|
|
#define GPIO50_SLP_WPD_MASK 0x00000004
|
|
#define GPIO50_SLP_IE_OFFSET 1
|
|
#define GPIO50_SLP_IE_MASK 0x00000002
|
|
#define GPIO50_SLP_OE_OFFSET 0
|
|
#define GPIO50_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO51_PIN_CFG_ADDR 0xd0
|
|
#define GPIO51_SEC_OFFSET 21
|
|
#define GPIO51_SEC_MASK 0x00200000
|
|
#define GPIO51_DRV_OFFSET 19
|
|
#define GPIO51_DRV_MASK 0x00180000
|
|
#define GPIO51_SLP_SEL_OFFSET 18
|
|
#define GPIO51_SLP_SEL_MASK 0x00040000
|
|
#define GPIO51_ODRV_OFFSET 17
|
|
#define GPIO51_ODRV_MASK 0x00020000
|
|
#define GPIO51_IINV_OFFSET 16
|
|
#define GPIO51_IINV_MASK 0x00010000
|
|
#define GPIO51_OINV_OFFSET 15
|
|
#define GPIO51_OINV_MASK 0x00008000
|
|
#define GPIO51_OPOS_OFFSET 14
|
|
#define GPIO51_OPOS_MASK 0x00004000
|
|
#define GPIO51_ONEG_OFFSET 13
|
|
#define GPIO51_ONEG_MASK 0x00002000
|
|
#define GPIO51_IPOS_OFFSET 12
|
|
#define GPIO51_IPOS_MASK 0x00001000
|
|
#define GPIO51_INEG_OFFSET 11
|
|
#define GPIO51_INEG_MASK 0x00000800
|
|
#define GPIO51_ORE_OFFSET 10
|
|
#define GPIO51_ORE_MASK 0x00000400
|
|
#define GPIO51_IRE_OFFSET 9
|
|
#define GPIO51_IRE_MASK 0x00000200
|
|
#define GPIO51_FUNC_WPU_OFFSET 8
|
|
#define GPIO51_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO51_FUNC_WPD_OFFSET 7
|
|
#define GPIO51_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO51_FUNC_SEL_OFFSET 4
|
|
#define GPIO51_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO51_SLP_WPU_OFFSET 3
|
|
#define GPIO51_SLP_WPU_MASK 0x00000008
|
|
#define GPIO51_SLP_WPD_OFFSET 2
|
|
#define GPIO51_SLP_WPD_MASK 0x00000004
|
|
#define GPIO51_SLP_IE_OFFSET 1
|
|
#define GPIO51_SLP_IE_MASK 0x00000002
|
|
#define GPIO51_SLP_OE_OFFSET 0
|
|
#define GPIO51_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO52_PIN_CFG_ADDR 0xd4
|
|
#define GPIO52_SEC_OFFSET 21
|
|
#define GPIO52_SEC_MASK 0x00200000
|
|
#define GPIO52_DRV_OFFSET 19
|
|
#define GPIO52_DRV_MASK 0x00180000
|
|
#define GPIO52_SLP_SEL_OFFSET 18
|
|
#define GPIO52_SLP_SEL_MASK 0x00040000
|
|
#define GPIO52_ODRV_OFFSET 17
|
|
#define GPIO52_ODRV_MASK 0x00020000
|
|
#define GPIO52_IINV_OFFSET 16
|
|
#define GPIO52_IINV_MASK 0x00010000
|
|
#define GPIO52_OINV_OFFSET 15
|
|
#define GPIO52_OINV_MASK 0x00008000
|
|
#define GPIO52_OPOS_OFFSET 14
|
|
#define GPIO52_OPOS_MASK 0x00004000
|
|
#define GPIO52_ONEG_OFFSET 13
|
|
#define GPIO52_ONEG_MASK 0x00002000
|
|
#define GPIO52_IPOS_OFFSET 12
|
|
#define GPIO52_IPOS_MASK 0x00001000
|
|
#define GPIO52_INEG_OFFSET 11
|
|
#define GPIO52_INEG_MASK 0x00000800
|
|
#define GPIO52_ORE_OFFSET 10
|
|
#define GPIO52_ORE_MASK 0x00000400
|
|
#define GPIO52_IRE_OFFSET 9
|
|
#define GPIO52_IRE_MASK 0x00000200
|
|
#define GPIO52_FUNC_WPU_OFFSET 8
|
|
#define GPIO52_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO52_FUNC_WPD_OFFSET 7
|
|
#define GPIO52_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO52_FUNC_SEL_OFFSET 4
|
|
#define GPIO52_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO52_SLP_WPU_OFFSET 3
|
|
#define GPIO52_SLP_WPU_MASK 0x00000008
|
|
#define GPIO52_SLP_WPD_OFFSET 2
|
|
#define GPIO52_SLP_WPD_MASK 0x00000004
|
|
#define GPIO52_SLP_IE_OFFSET 1
|
|
#define GPIO52_SLP_IE_MASK 0x00000002
|
|
#define GPIO52_SLP_OE_OFFSET 0
|
|
#define GPIO52_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO53_PIN_CFG_ADDR 0xd8
|
|
#define GPIO53_SEC_OFFSET 21
|
|
#define GPIO53_SEC_MASK 0x00200000
|
|
#define GPIO53_DRV_OFFSET 19
|
|
#define GPIO53_DRV_MASK 0x00180000
|
|
#define GPIO53_SLP_SEL_OFFSET 18
|
|
#define GPIO53_SLP_SEL_MASK 0x00040000
|
|
#define GPIO53_ODRV_OFFSET 17
|
|
#define GPIO53_ODRV_MASK 0x00020000
|
|
#define GPIO53_IINV_OFFSET 16
|
|
#define GPIO53_IINV_MASK 0x00010000
|
|
#define GPIO53_OINV_OFFSET 15
|
|
#define GPIO53_OINV_MASK 0x00008000
|
|
#define GPIO53_OPOS_OFFSET 14
|
|
#define GPIO53_OPOS_MASK 0x00004000
|
|
#define GPIO53_ONEG_OFFSET 13
|
|
#define GPIO53_ONEG_MASK 0x00002000
|
|
#define GPIO53_IPOS_OFFSET 12
|
|
#define GPIO53_IPOS_MASK 0x00001000
|
|
#define GPIO53_INEG_OFFSET 11
|
|
#define GPIO53_INEG_MASK 0x00000800
|
|
#define GPIO53_ORE_OFFSET 10
|
|
#define GPIO53_ORE_MASK 0x00000400
|
|
#define GPIO53_IRE_OFFSET 9
|
|
#define GPIO53_IRE_MASK 0x00000200
|
|
#define GPIO53_FUNC_WPU_OFFSET 8
|
|
#define GPIO53_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO53_FUNC_WPD_OFFSET 7
|
|
#define GPIO53_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO53_FUNC_SEL_OFFSET 4
|
|
#define GPIO53_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO53_SLP_WPU_OFFSET 3
|
|
#define GPIO53_SLP_WPU_MASK 0x00000008
|
|
#define GPIO53_SLP_WPD_OFFSET 2
|
|
#define GPIO53_SLP_WPD_MASK 0x00000004
|
|
#define GPIO53_SLP_IE_OFFSET 1
|
|
#define GPIO53_SLP_IE_MASK 0x00000002
|
|
#define GPIO53_SLP_OE_OFFSET 0
|
|
#define GPIO53_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO54_PIN_CFG_ADDR 0xdc
|
|
#define GPIO54_SEC_OFFSET 21
|
|
#define GPIO54_SEC_MASK 0x00200000
|
|
#define GPIO54_DRV_OFFSET 19
|
|
#define GPIO54_DRV_MASK 0x00180000
|
|
#define GPIO54_SLP_SEL_OFFSET 18
|
|
#define GPIO54_SLP_SEL_MASK 0x00040000
|
|
#define GPIO54_ODRV_OFFSET 17
|
|
#define GPIO54_ODRV_MASK 0x00020000
|
|
#define GPIO54_IINV_OFFSET 16
|
|
#define GPIO54_IINV_MASK 0x00010000
|
|
#define GPIO54_OINV_OFFSET 15
|
|
#define GPIO54_OINV_MASK 0x00008000
|
|
#define GPIO54_OPOS_OFFSET 14
|
|
#define GPIO54_OPOS_MASK 0x00004000
|
|
#define GPIO54_ONEG_OFFSET 13
|
|
#define GPIO54_ONEG_MASK 0x00002000
|
|
#define GPIO54_IPOS_OFFSET 12
|
|
#define GPIO54_IPOS_MASK 0x00001000
|
|
#define GPIO54_INEG_OFFSET 11
|
|
#define GPIO54_INEG_MASK 0x00000800
|
|
#define GPIO54_ORE_OFFSET 10
|
|
#define GPIO54_ORE_MASK 0x00000400
|
|
#define GPIO54_IRE_OFFSET 9
|
|
#define GPIO54_IRE_MASK 0x00000200
|
|
#define GPIO54_FUNC_WPU_OFFSET 8
|
|
#define GPIO54_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO54_FUNC_WPD_OFFSET 7
|
|
#define GPIO54_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO54_FUNC_SEL_OFFSET 4
|
|
#define GPIO54_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO54_SLP_WPU_OFFSET 3
|
|
#define GPIO54_SLP_WPU_MASK 0x00000008
|
|
#define GPIO54_SLP_WPD_OFFSET 2
|
|
#define GPIO54_SLP_WPD_MASK 0x00000004
|
|
#define GPIO54_SLP_IE_OFFSET 1
|
|
#define GPIO54_SLP_IE_MASK 0x00000002
|
|
#define GPIO54_SLP_OE_OFFSET 0
|
|
#define GPIO54_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO55_PIN_CFG_ADDR 0xe0
|
|
#define GPIO55_SEC_OFFSET 21
|
|
#define GPIO55_SEC_MASK 0x00200000
|
|
#define GPIO55_DRV_OFFSET 19
|
|
#define GPIO55_DRV_MASK 0x00180000
|
|
#define GPIO55_SLP_SEL_OFFSET 18
|
|
#define GPIO55_SLP_SEL_MASK 0x00040000
|
|
#define GPIO55_ODRV_OFFSET 17
|
|
#define GPIO55_ODRV_MASK 0x00020000
|
|
#define GPIO55_IINV_OFFSET 16
|
|
#define GPIO55_IINV_MASK 0x00010000
|
|
#define GPIO55_OINV_OFFSET 15
|
|
#define GPIO55_OINV_MASK 0x00008000
|
|
#define GPIO55_OPOS_OFFSET 14
|
|
#define GPIO55_OPOS_MASK 0x00004000
|
|
#define GPIO55_ONEG_OFFSET 13
|
|
#define GPIO55_ONEG_MASK 0x00002000
|
|
#define GPIO55_IPOS_OFFSET 12
|
|
#define GPIO55_IPOS_MASK 0x00001000
|
|
#define GPIO55_INEG_OFFSET 11
|
|
#define GPIO55_INEG_MASK 0x00000800
|
|
#define GPIO55_ORE_OFFSET 10
|
|
#define GPIO55_ORE_MASK 0x00000400
|
|
#define GPIO55_IRE_OFFSET 9
|
|
#define GPIO55_IRE_MASK 0x00000200
|
|
#define GPIO55_FUNC_WPU_OFFSET 8
|
|
#define GPIO55_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO55_FUNC_WPD_OFFSET 7
|
|
#define GPIO55_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO55_FUNC_SEL_OFFSET 4
|
|
#define GPIO55_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO55_SLP_WPU_OFFSET 3
|
|
#define GPIO55_SLP_WPU_MASK 0x00000008
|
|
#define GPIO55_SLP_WPD_OFFSET 2
|
|
#define GPIO55_SLP_WPD_MASK 0x00000004
|
|
#define GPIO55_SLP_IE_OFFSET 1
|
|
#define GPIO55_SLP_IE_MASK 0x00000002
|
|
#define GPIO55_SLP_OE_OFFSET 0
|
|
#define GPIO55_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO56_PIN_CFG_ADDR 0xe4
|
|
#define GPIO56_SEC_OFFSET 21
|
|
#define GPIO56_SEC_MASK 0x00200000
|
|
#define GPIO56_DRV_OFFSET 19
|
|
#define GPIO56_DRV_MASK 0x00180000
|
|
#define GPIO56_SLP_SEL_OFFSET 18
|
|
#define GPIO56_SLP_SEL_MASK 0x00040000
|
|
#define GPIO56_ODRV_OFFSET 17
|
|
#define GPIO56_ODRV_MASK 0x00020000
|
|
#define GPIO56_IINV_OFFSET 16
|
|
#define GPIO56_IINV_MASK 0x00010000
|
|
#define GPIO56_OINV_OFFSET 15
|
|
#define GPIO56_OINV_MASK 0x00008000
|
|
#define GPIO56_OPOS_OFFSET 14
|
|
#define GPIO56_OPOS_MASK 0x00004000
|
|
#define GPIO56_ONEG_OFFSET 13
|
|
#define GPIO56_ONEG_MASK 0x00002000
|
|
#define GPIO56_IPOS_OFFSET 12
|
|
#define GPIO56_IPOS_MASK 0x00001000
|
|
#define GPIO56_INEG_OFFSET 11
|
|
#define GPIO56_INEG_MASK 0x00000800
|
|
#define GPIO56_ORE_OFFSET 10
|
|
#define GPIO56_ORE_MASK 0x00000400
|
|
#define GPIO56_IRE_OFFSET 9
|
|
#define GPIO56_IRE_MASK 0x00000200
|
|
#define GPIO56_FUNC_WPU_OFFSET 8
|
|
#define GPIO56_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO56_FUNC_WPD_OFFSET 7
|
|
#define GPIO56_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO56_FUNC_SEL_OFFSET 4
|
|
#define GPIO56_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO56_SLP_WPU_OFFSET 3
|
|
#define GPIO56_SLP_WPU_MASK 0x00000008
|
|
#define GPIO56_SLP_WPD_OFFSET 2
|
|
#define GPIO56_SLP_WPD_MASK 0x00000004
|
|
#define GPIO56_SLP_IE_OFFSET 1
|
|
#define GPIO56_SLP_IE_MASK 0x00000002
|
|
#define GPIO56_SLP_OE_OFFSET 0
|
|
#define GPIO56_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO57_PIN_CFG_ADDR 0xe8
|
|
#define GPIO57_SEC_OFFSET 21
|
|
#define GPIO57_SEC_MASK 0x00200000
|
|
#define GPIO57_DRV_OFFSET 19
|
|
#define GPIO57_DRV_MASK 0x00180000
|
|
#define GPIO57_SLP_SEL_OFFSET 18
|
|
#define GPIO57_SLP_SEL_MASK 0x00040000
|
|
#define GPIO57_ODRV_OFFSET 17
|
|
#define GPIO57_ODRV_MASK 0x00020000
|
|
#define GPIO57_IINV_OFFSET 16
|
|
#define GPIO57_IINV_MASK 0x00010000
|
|
#define GPIO57_OINV_OFFSET 15
|
|
#define GPIO57_OINV_MASK 0x00008000
|
|
#define GPIO57_OPOS_OFFSET 14
|
|
#define GPIO57_OPOS_MASK 0x00004000
|
|
#define GPIO57_ONEG_OFFSET 13
|
|
#define GPIO57_ONEG_MASK 0x00002000
|
|
#define GPIO57_IPOS_OFFSET 12
|
|
#define GPIO57_IPOS_MASK 0x00001000
|
|
#define GPIO57_INEG_OFFSET 11
|
|
#define GPIO57_INEG_MASK 0x00000800
|
|
#define GPIO57_ORE_OFFSET 10
|
|
#define GPIO57_ORE_MASK 0x00000400
|
|
#define GPIO57_IRE_OFFSET 9
|
|
#define GPIO57_IRE_MASK 0x00000200
|
|
#define GPIO57_FUNC_WPU_OFFSET 8
|
|
#define GPIO57_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO57_FUNC_WPD_OFFSET 7
|
|
#define GPIO57_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO57_FUNC_SEL_OFFSET 4
|
|
#define GPIO57_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO57_SLP_WPU_OFFSET 3
|
|
#define GPIO57_SLP_WPU_MASK 0x00000008
|
|
#define GPIO57_SLP_WPD_OFFSET 2
|
|
#define GPIO57_SLP_WPD_MASK 0x00000004
|
|
#define GPIO57_SLP_IE_OFFSET 1
|
|
#define GPIO57_SLP_IE_MASK 0x00000002
|
|
#define GPIO57_SLP_OE_OFFSET 0
|
|
#define GPIO57_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO58_PIN_CFG_ADDR 0xec
|
|
#define GPIO58_SEC_OFFSET 21
|
|
#define GPIO58_SEC_MASK 0x00200000
|
|
#define GPIO58_DRV_OFFSET 19
|
|
#define GPIO58_DRV_MASK 0x00180000
|
|
#define GPIO58_SLP_SEL_OFFSET 18
|
|
#define GPIO58_SLP_SEL_MASK 0x00040000
|
|
#define GPIO58_ODRV_OFFSET 17
|
|
#define GPIO58_ODRV_MASK 0x00020000
|
|
#define GPIO58_IINV_OFFSET 16
|
|
#define GPIO58_IINV_MASK 0x00010000
|
|
#define GPIO58_OINV_OFFSET 15
|
|
#define GPIO58_OINV_MASK 0x00008000
|
|
#define GPIO58_OPOS_OFFSET 14
|
|
#define GPIO58_OPOS_MASK 0x00004000
|
|
#define GPIO58_ONEG_OFFSET 13
|
|
#define GPIO58_ONEG_MASK 0x00002000
|
|
#define GPIO58_IPOS_OFFSET 12
|
|
#define GPIO58_IPOS_MASK 0x00001000
|
|
#define GPIO58_INEG_OFFSET 11
|
|
#define GPIO58_INEG_MASK 0x00000800
|
|
#define GPIO58_ORE_OFFSET 10
|
|
#define GPIO58_ORE_MASK 0x00000400
|
|
#define GPIO58_IRE_OFFSET 9
|
|
#define GPIO58_IRE_MASK 0x00000200
|
|
#define GPIO58_FUNC_WPU_OFFSET 8
|
|
#define GPIO58_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO58_FUNC_WPD_OFFSET 7
|
|
#define GPIO58_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO58_FUNC_SEL_OFFSET 4
|
|
#define GPIO58_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO58_SLP_WPU_OFFSET 3
|
|
#define GPIO58_SLP_WPU_MASK 0x00000008
|
|
#define GPIO58_SLP_WPD_OFFSET 2
|
|
#define GPIO58_SLP_WPD_MASK 0x00000004
|
|
#define GPIO58_SLP_IE_OFFSET 1
|
|
#define GPIO58_SLP_IE_MASK 0x00000002
|
|
#define GPIO58_SLP_OE_OFFSET 0
|
|
#define GPIO58_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO59_PIN_CFG_ADDR 0xf0
|
|
#define GPIO59_SEC_OFFSET 21
|
|
#define GPIO59_SEC_MASK 0x00200000
|
|
#define GPIO59_DRV_OFFSET 19
|
|
#define GPIO59_DRV_MASK 0x00180000
|
|
#define GPIO59_SLP_SEL_OFFSET 18
|
|
#define GPIO59_SLP_SEL_MASK 0x00040000
|
|
#define GPIO59_ODRV_OFFSET 17
|
|
#define GPIO59_ODRV_MASK 0x00020000
|
|
#define GPIO59_IINV_OFFSET 16
|
|
#define GPIO59_IINV_MASK 0x00010000
|
|
#define GPIO59_OINV_OFFSET 15
|
|
#define GPIO59_OINV_MASK 0x00008000
|
|
#define GPIO59_OPOS_OFFSET 14
|
|
#define GPIO59_OPOS_MASK 0x00004000
|
|
#define GPIO59_ONEG_OFFSET 13
|
|
#define GPIO59_ONEG_MASK 0x00002000
|
|
#define GPIO59_IPOS_OFFSET 12
|
|
#define GPIO59_IPOS_MASK 0x00001000
|
|
#define GPIO59_INEG_OFFSET 11
|
|
#define GPIO59_INEG_MASK 0x00000800
|
|
#define GPIO59_ORE_OFFSET 10
|
|
#define GPIO59_ORE_MASK 0x00000400
|
|
#define GPIO59_IRE_OFFSET 9
|
|
#define GPIO59_IRE_MASK 0x00000200
|
|
#define GPIO59_FUNC_WPU_OFFSET 8
|
|
#define GPIO59_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO59_FUNC_WPD_OFFSET 7
|
|
#define GPIO59_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO59_FUNC_SEL_OFFSET 4
|
|
#define GPIO59_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO59_SLP_WPU_OFFSET 3
|
|
#define GPIO59_SLP_WPU_MASK 0x00000008
|
|
#define GPIO59_SLP_WPD_OFFSET 2
|
|
#define GPIO59_SLP_WPD_MASK 0x00000004
|
|
#define GPIO59_SLP_IE_OFFSET 1
|
|
#define GPIO59_SLP_IE_MASK 0x00000002
|
|
#define GPIO59_SLP_OE_OFFSET 0
|
|
#define GPIO59_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO60_PIN_CFG_ADDR 0xf4
|
|
#define GPIO60_SEC_OFFSET 21
|
|
#define GPIO60_SEC_MASK 0x00200000
|
|
#define GPIO60_DRV_OFFSET 19
|
|
#define GPIO60_DRV_MASK 0x00180000
|
|
#define GPIO60_SLP_SEL_OFFSET 18
|
|
#define GPIO60_SLP_SEL_MASK 0x00040000
|
|
#define GPIO60_ODRV_OFFSET 17
|
|
#define GPIO60_ODRV_MASK 0x00020000
|
|
#define GPIO60_IINV_OFFSET 16
|
|
#define GPIO60_IINV_MASK 0x00010000
|
|
#define GPIO60_OINV_OFFSET 15
|
|
#define GPIO60_OINV_MASK 0x00008000
|
|
#define GPIO60_OPOS_OFFSET 14
|
|
#define GPIO60_OPOS_MASK 0x00004000
|
|
#define GPIO60_ONEG_OFFSET 13
|
|
#define GPIO60_ONEG_MASK 0x00002000
|
|
#define GPIO60_IPOS_OFFSET 12
|
|
#define GPIO60_IPOS_MASK 0x00001000
|
|
#define GPIO60_INEG_OFFSET 11
|
|
#define GPIO60_INEG_MASK 0x00000800
|
|
#define GPIO60_ORE_OFFSET 10
|
|
#define GPIO60_ORE_MASK 0x00000400
|
|
#define GPIO60_IRE_OFFSET 9
|
|
#define GPIO60_IRE_MASK 0x00000200
|
|
#define GPIO60_FUNC_WPU_OFFSET 8
|
|
#define GPIO60_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO60_FUNC_WPD_OFFSET 7
|
|
#define GPIO60_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO60_FUNC_SEL_OFFSET 4
|
|
#define GPIO60_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO60_SLP_WPU_OFFSET 3
|
|
#define GPIO60_SLP_WPU_MASK 0x00000008
|
|
#define GPIO60_SLP_WPD_OFFSET 2
|
|
#define GPIO60_SLP_WPD_MASK 0x00000004
|
|
#define GPIO60_SLP_IE_OFFSET 1
|
|
#define GPIO60_SLP_IE_MASK 0x00000002
|
|
#define GPIO60_SLP_OE_OFFSET 0
|
|
#define GPIO60_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO61_PIN_CFG_ADDR 0xf8
|
|
#define GPIO61_SEC_OFFSET 21
|
|
#define GPIO61_SEC_MASK 0x00200000
|
|
#define GPIO61_DRV_OFFSET 19
|
|
#define GPIO61_DRV_MASK 0x00180000
|
|
#define GPIO61_SLP_SEL_OFFSET 18
|
|
#define GPIO61_SLP_SEL_MASK 0x00040000
|
|
#define GPIO61_ODRV_OFFSET 17
|
|
#define GPIO61_ODRV_MASK 0x00020000
|
|
#define GPIO61_IINV_OFFSET 16
|
|
#define GPIO61_IINV_MASK 0x00010000
|
|
#define GPIO61_OINV_OFFSET 15
|
|
#define GPIO61_OINV_MASK 0x00008000
|
|
#define GPIO61_OPOS_OFFSET 14
|
|
#define GPIO61_OPOS_MASK 0x00004000
|
|
#define GPIO61_ONEG_OFFSET 13
|
|
#define GPIO61_ONEG_MASK 0x00002000
|
|
#define GPIO61_IPOS_OFFSET 12
|
|
#define GPIO61_IPOS_MASK 0x00001000
|
|
#define GPIO61_INEG_OFFSET 11
|
|
#define GPIO61_INEG_MASK 0x00000800
|
|
#define GPIO61_ORE_OFFSET 10
|
|
#define GPIO61_ORE_MASK 0x00000400
|
|
#define GPIO61_IRE_OFFSET 9
|
|
#define GPIO61_IRE_MASK 0x00000200
|
|
#define GPIO61_FUNC_WPU_OFFSET 8
|
|
#define GPIO61_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO61_FUNC_WPD_OFFSET 7
|
|
#define GPIO61_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO61_FUNC_SEL_OFFSET 4
|
|
#define GPIO61_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO61_SLP_WPU_OFFSET 3
|
|
#define GPIO61_SLP_WPU_MASK 0x00000008
|
|
#define GPIO61_SLP_WPD_OFFSET 2
|
|
#define GPIO61_SLP_WPD_MASK 0x00000004
|
|
#define GPIO61_SLP_IE_OFFSET 1
|
|
#define GPIO61_SLP_IE_MASK 0x00000002
|
|
#define GPIO61_SLP_OE_OFFSET 0
|
|
#define GPIO61_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO62_PIN_CFG_ADDR 0xfc
|
|
#define GPIO62_SEC_OFFSET 21
|
|
#define GPIO62_SEC_MASK 0x00200000
|
|
#define GPIO62_DRV_OFFSET 19
|
|
#define GPIO62_DRV_MASK 0x00180000
|
|
#define GPIO62_SLP_SEL_OFFSET 18
|
|
#define GPIO62_SLP_SEL_MASK 0x00040000
|
|
#define GPIO62_ODRV_OFFSET 17
|
|
#define GPIO62_ODRV_MASK 0x00020000
|
|
#define GPIO62_IINV_OFFSET 16
|
|
#define GPIO62_IINV_MASK 0x00010000
|
|
#define GPIO62_OINV_OFFSET 15
|
|
#define GPIO62_OINV_MASK 0x00008000
|
|
#define GPIO62_OPOS_OFFSET 14
|
|
#define GPIO62_OPOS_MASK 0x00004000
|
|
#define GPIO62_ONEG_OFFSET 13
|
|
#define GPIO62_ONEG_MASK 0x00002000
|
|
#define GPIO62_IPOS_OFFSET 12
|
|
#define GPIO62_IPOS_MASK 0x00001000
|
|
#define GPIO62_INEG_OFFSET 11
|
|
#define GPIO62_INEG_MASK 0x00000800
|
|
#define GPIO62_ORE_OFFSET 10
|
|
#define GPIO62_ORE_MASK 0x00000400
|
|
#define GPIO62_IRE_OFFSET 9
|
|
#define GPIO62_IRE_MASK 0x00000200
|
|
#define GPIO62_FUNC_WPU_OFFSET 8
|
|
#define GPIO62_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO62_FUNC_WPD_OFFSET 7
|
|
#define GPIO62_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO62_FUNC_SEL_OFFSET 4
|
|
#define GPIO62_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO62_SLP_WPU_OFFSET 3
|
|
#define GPIO62_SLP_WPU_MASK 0x00000008
|
|
#define GPIO62_SLP_WPD_OFFSET 2
|
|
#define GPIO62_SLP_WPD_MASK 0x00000004
|
|
#define GPIO62_SLP_IE_OFFSET 1
|
|
#define GPIO62_SLP_IE_MASK 0x00000002
|
|
#define GPIO62_SLP_OE_OFFSET 0
|
|
#define GPIO62_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO63_PIN_CFG_ADDR 0x100
|
|
#define GPIO63_SEC_OFFSET 21
|
|
#define GPIO63_SEC_MASK 0x00200000
|
|
#define GPIO63_DRV_OFFSET 19
|
|
#define GPIO63_DRV_MASK 0x00180000
|
|
#define GPIO63_SLP_SEL_OFFSET 18
|
|
#define GPIO63_SLP_SEL_MASK 0x00040000
|
|
#define GPIO63_ODRV_OFFSET 17
|
|
#define GPIO63_ODRV_MASK 0x00020000
|
|
#define GPIO63_IINV_OFFSET 16
|
|
#define GPIO63_IINV_MASK 0x00010000
|
|
#define GPIO63_OINV_OFFSET 15
|
|
#define GPIO63_OINV_MASK 0x00008000
|
|
#define GPIO63_OPOS_OFFSET 14
|
|
#define GPIO63_OPOS_MASK 0x00004000
|
|
#define GPIO63_ONEG_OFFSET 13
|
|
#define GPIO63_ONEG_MASK 0x00002000
|
|
#define GPIO63_IPOS_OFFSET 12
|
|
#define GPIO63_IPOS_MASK 0x00001000
|
|
#define GPIO63_INEG_OFFSET 11
|
|
#define GPIO63_INEG_MASK 0x00000800
|
|
#define GPIO63_ORE_OFFSET 10
|
|
#define GPIO63_ORE_MASK 0x00000400
|
|
#define GPIO63_IRE_OFFSET 9
|
|
#define GPIO63_IRE_MASK 0x00000200
|
|
#define GPIO63_FUNC_WPU_OFFSET 8
|
|
#define GPIO63_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO63_FUNC_WPD_OFFSET 7
|
|
#define GPIO63_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO63_FUNC_SEL_OFFSET 4
|
|
#define GPIO63_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO63_SLP_WPU_OFFSET 3
|
|
#define GPIO63_SLP_WPU_MASK 0x00000008
|
|
#define GPIO63_SLP_WPD_OFFSET 2
|
|
#define GPIO63_SLP_WPD_MASK 0x00000004
|
|
#define GPIO63_SLP_IE_OFFSET 1
|
|
#define GPIO63_SLP_IE_MASK 0x00000002
|
|
#define GPIO63_SLP_OE_OFFSET 0
|
|
#define GPIO63_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO64_PIN_CFG_ADDR 0x104
|
|
#define GPIO64_SEC_OFFSET 21
|
|
#define GPIO64_SEC_MASK 0x00200000
|
|
#define GPIO64_DRV_OFFSET 19
|
|
#define GPIO64_DRV_MASK 0x00180000
|
|
#define GPIO64_SLP_SEL_OFFSET 18
|
|
#define GPIO64_SLP_SEL_MASK 0x00040000
|
|
#define GPIO64_ODRV_OFFSET 17
|
|
#define GPIO64_ODRV_MASK 0x00020000
|
|
#define GPIO64_IINV_OFFSET 16
|
|
#define GPIO64_IINV_MASK 0x00010000
|
|
#define GPIO64_OINV_OFFSET 15
|
|
#define GPIO64_OINV_MASK 0x00008000
|
|
#define GPIO64_OPOS_OFFSET 14
|
|
#define GPIO64_OPOS_MASK 0x00004000
|
|
#define GPIO64_ONEG_OFFSET 13
|
|
#define GPIO64_ONEG_MASK 0x00002000
|
|
#define GPIO64_IPOS_OFFSET 12
|
|
#define GPIO64_IPOS_MASK 0x00001000
|
|
#define GPIO64_INEG_OFFSET 11
|
|
#define GPIO64_INEG_MASK 0x00000800
|
|
#define GPIO64_ORE_OFFSET 10
|
|
#define GPIO64_ORE_MASK 0x00000400
|
|
#define GPIO64_IRE_OFFSET 9
|
|
#define GPIO64_IRE_MASK 0x00000200
|
|
#define GPIO64_FUNC_WPU_OFFSET 8
|
|
#define GPIO64_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO64_FUNC_WPD_OFFSET 7
|
|
#define GPIO64_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO64_FUNC_SEL_OFFSET 4
|
|
#define GPIO64_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO64_SLP_WPU_OFFSET 3
|
|
#define GPIO64_SLP_WPU_MASK 0x00000008
|
|
#define GPIO64_SLP_WPD_OFFSET 2
|
|
#define GPIO64_SLP_WPD_MASK 0x00000004
|
|
#define GPIO64_SLP_IE_OFFSET 1
|
|
#define GPIO64_SLP_IE_MASK 0x00000002
|
|
#define GPIO64_SLP_OE_OFFSET 0
|
|
#define GPIO64_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO65_PIN_CFG_ADDR 0x108
|
|
#define GPIO65_SEC_OFFSET 21
|
|
#define GPIO65_SEC_MASK 0x00200000
|
|
#define GPIO65_DRV_OFFSET 19
|
|
#define GPIO65_DRV_MASK 0x00180000
|
|
#define GPIO65_SLP_SEL_OFFSET 18
|
|
#define GPIO65_SLP_SEL_MASK 0x00040000
|
|
#define GPIO65_ODRV_OFFSET 17
|
|
#define GPIO65_ODRV_MASK 0x00020000
|
|
#define GPIO65_IINV_OFFSET 16
|
|
#define GPIO65_IINV_MASK 0x00010000
|
|
#define GPIO65_OINV_OFFSET 15
|
|
#define GPIO65_OINV_MASK 0x00008000
|
|
#define GPIO65_OPOS_OFFSET 14
|
|
#define GPIO65_OPOS_MASK 0x00004000
|
|
#define GPIO65_ONEG_OFFSET 13
|
|
#define GPIO65_ONEG_MASK 0x00002000
|
|
#define GPIO65_IPOS_OFFSET 12
|
|
#define GPIO65_IPOS_MASK 0x00001000
|
|
#define GPIO65_INEG_OFFSET 11
|
|
#define GPIO65_INEG_MASK 0x00000800
|
|
#define GPIO65_ORE_OFFSET 10
|
|
#define GPIO65_ORE_MASK 0x00000400
|
|
#define GPIO65_IRE_OFFSET 9
|
|
#define GPIO65_IRE_MASK 0x00000200
|
|
#define GPIO65_FUNC_WPU_OFFSET 8
|
|
#define GPIO65_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO65_FUNC_WPD_OFFSET 7
|
|
#define GPIO65_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO65_FUNC_SEL_OFFSET 4
|
|
#define GPIO65_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO65_SLP_WPU_OFFSET 3
|
|
#define GPIO65_SLP_WPU_MASK 0x00000008
|
|
#define GPIO65_SLP_WPD_OFFSET 2
|
|
#define GPIO65_SLP_WPD_MASK 0x00000004
|
|
#define GPIO65_SLP_IE_OFFSET 1
|
|
#define GPIO65_SLP_IE_MASK 0x00000002
|
|
#define GPIO65_SLP_OE_OFFSET 0
|
|
#define GPIO65_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO66_PIN_CFG_ADDR 0x10c
|
|
#define GPIO66_SEC_OFFSET 21
|
|
#define GPIO66_SEC_MASK 0x00200000
|
|
#define GPIO66_DRV_OFFSET 19
|
|
#define GPIO66_DRV_MASK 0x00180000
|
|
#define GPIO66_SLP_SEL_OFFSET 18
|
|
#define GPIO66_SLP_SEL_MASK 0x00040000
|
|
#define GPIO66_ODRV_OFFSET 17
|
|
#define GPIO66_ODRV_MASK 0x00020000
|
|
#define GPIO66_IINV_OFFSET 16
|
|
#define GPIO66_IINV_MASK 0x00010000
|
|
#define GPIO66_OINV_OFFSET 15
|
|
#define GPIO66_OINV_MASK 0x00008000
|
|
#define GPIO66_OPOS_OFFSET 14
|
|
#define GPIO66_OPOS_MASK 0x00004000
|
|
#define GPIO66_ONEG_OFFSET 13
|
|
#define GPIO66_ONEG_MASK 0x00002000
|
|
#define GPIO66_IPOS_OFFSET 12
|
|
#define GPIO66_IPOS_MASK 0x00001000
|
|
#define GPIO66_INEG_OFFSET 11
|
|
#define GPIO66_INEG_MASK 0x00000800
|
|
#define GPIO66_ORE_OFFSET 10
|
|
#define GPIO66_ORE_MASK 0x00000400
|
|
#define GPIO66_IRE_OFFSET 9
|
|
#define GPIO66_IRE_MASK 0x00000200
|
|
#define GPIO66_FUNC_WPU_OFFSET 8
|
|
#define GPIO66_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO66_FUNC_WPD_OFFSET 7
|
|
#define GPIO66_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO66_FUNC_SEL_OFFSET 4
|
|
#define GPIO66_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO66_SLP_WPU_OFFSET 3
|
|
#define GPIO66_SLP_WPU_MASK 0x00000008
|
|
#define GPIO66_SLP_WPD_OFFSET 2
|
|
#define GPIO66_SLP_WPD_MASK 0x00000004
|
|
#define GPIO66_SLP_IE_OFFSET 1
|
|
#define GPIO66_SLP_IE_MASK 0x00000002
|
|
#define GPIO66_SLP_OE_OFFSET 0
|
|
#define GPIO66_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO67_PIN_CFG_ADDR 0x110
|
|
#define GPIO67_SEC_OFFSET 21
|
|
#define GPIO67_SEC_MASK 0x00200000
|
|
#define GPIO67_DRV_OFFSET 19
|
|
#define GPIO67_DRV_MASK 0x00180000
|
|
#define GPIO67_SLP_SEL_OFFSET 18
|
|
#define GPIO67_SLP_SEL_MASK 0x00040000
|
|
#define GPIO67_ODRV_OFFSET 17
|
|
#define GPIO67_ODRV_MASK 0x00020000
|
|
#define GPIO67_IINV_OFFSET 16
|
|
#define GPIO67_IINV_MASK 0x00010000
|
|
#define GPIO67_OINV_OFFSET 15
|
|
#define GPIO67_OINV_MASK 0x00008000
|
|
#define GPIO67_OPOS_OFFSET 14
|
|
#define GPIO67_OPOS_MASK 0x00004000
|
|
#define GPIO67_ONEG_OFFSET 13
|
|
#define GPIO67_ONEG_MASK 0x00002000
|
|
#define GPIO67_IPOS_OFFSET 12
|
|
#define GPIO67_IPOS_MASK 0x00001000
|
|
#define GPIO67_INEG_OFFSET 11
|
|
#define GPIO67_INEG_MASK 0x00000800
|
|
#define GPIO67_ORE_OFFSET 10
|
|
#define GPIO67_ORE_MASK 0x00000400
|
|
#define GPIO67_IRE_OFFSET 9
|
|
#define GPIO67_IRE_MASK 0x00000200
|
|
#define GPIO67_FUNC_WPU_OFFSET 8
|
|
#define GPIO67_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO67_FUNC_WPD_OFFSET 7
|
|
#define GPIO67_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO67_FUNC_SEL_OFFSET 4
|
|
#define GPIO67_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO67_SLP_WPU_OFFSET 3
|
|
#define GPIO67_SLP_WPU_MASK 0x00000008
|
|
#define GPIO67_SLP_WPD_OFFSET 2
|
|
#define GPIO67_SLP_WPD_MASK 0x00000004
|
|
#define GPIO67_SLP_IE_OFFSET 1
|
|
#define GPIO67_SLP_IE_MASK 0x00000002
|
|
#define GPIO67_SLP_OE_OFFSET 0
|
|
#define GPIO67_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO68_PIN_CFG_ADDR 0x114
|
|
#define GPIO68_SEC_OFFSET 21
|
|
#define GPIO68_SEC_MASK 0x00200000
|
|
#define GPIO68_DRV_OFFSET 19
|
|
#define GPIO68_DRV_MASK 0x00180000
|
|
#define GPIO68_SLP_SEL_OFFSET 18
|
|
#define GPIO68_SLP_SEL_MASK 0x00040000
|
|
#define GPIO68_ODRV_OFFSET 17
|
|
#define GPIO68_ODRV_MASK 0x00020000
|
|
#define GPIO68_IINV_OFFSET 16
|
|
#define GPIO68_IINV_MASK 0x00010000
|
|
#define GPIO68_OINV_OFFSET 15
|
|
#define GPIO68_OINV_MASK 0x00008000
|
|
#define GPIO68_OPOS_OFFSET 14
|
|
#define GPIO68_OPOS_MASK 0x00004000
|
|
#define GPIO68_ONEG_OFFSET 13
|
|
#define GPIO68_ONEG_MASK 0x00002000
|
|
#define GPIO68_IPOS_OFFSET 12
|
|
#define GPIO68_IPOS_MASK 0x00001000
|
|
#define GPIO68_INEG_OFFSET 11
|
|
#define GPIO68_INEG_MASK 0x00000800
|
|
#define GPIO68_ORE_OFFSET 10
|
|
#define GPIO68_ORE_MASK 0x00000400
|
|
#define GPIO68_IRE_OFFSET 9
|
|
#define GPIO68_IRE_MASK 0x00000200
|
|
#define GPIO68_FUNC_WPU_OFFSET 8
|
|
#define GPIO68_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO68_FUNC_WPD_OFFSET 7
|
|
#define GPIO68_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO68_FUNC_SEL_OFFSET 4
|
|
#define GPIO68_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO68_SLP_WPU_OFFSET 3
|
|
#define GPIO68_SLP_WPU_MASK 0x00000008
|
|
#define GPIO68_SLP_WPD_OFFSET 2
|
|
#define GPIO68_SLP_WPD_MASK 0x00000004
|
|
#define GPIO68_SLP_IE_OFFSET 1
|
|
#define GPIO68_SLP_IE_MASK 0x00000002
|
|
#define GPIO68_SLP_OE_OFFSET 0
|
|
#define GPIO68_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO69_PIN_CFG_ADDR 0x118
|
|
#define GPIO69_SEC_OFFSET 21
|
|
#define GPIO69_SEC_MASK 0x00200000
|
|
#define GPIO69_DRV_OFFSET 19
|
|
#define GPIO69_DRV_MASK 0x00180000
|
|
#define GPIO69_SLP_SEL_OFFSET 18
|
|
#define GPIO69_SLP_SEL_MASK 0x00040000
|
|
#define GPIO69_ODRV_OFFSET 17
|
|
#define GPIO69_ODRV_MASK 0x00020000
|
|
#define GPIO69_IINV_OFFSET 16
|
|
#define GPIO69_IINV_MASK 0x00010000
|
|
#define GPIO69_OINV_OFFSET 15
|
|
#define GPIO69_OINV_MASK 0x00008000
|
|
#define GPIO69_OPOS_OFFSET 14
|
|
#define GPIO69_OPOS_MASK 0x00004000
|
|
#define GPIO69_ONEG_OFFSET 13
|
|
#define GPIO69_ONEG_MASK 0x00002000
|
|
#define GPIO69_IPOS_OFFSET 12
|
|
#define GPIO69_IPOS_MASK 0x00001000
|
|
#define GPIO69_INEG_OFFSET 11
|
|
#define GPIO69_INEG_MASK 0x00000800
|
|
#define GPIO69_ORE_OFFSET 10
|
|
#define GPIO69_ORE_MASK 0x00000400
|
|
#define GPIO69_IRE_OFFSET 9
|
|
#define GPIO69_IRE_MASK 0x00000200
|
|
#define GPIO69_FUNC_WPU_OFFSET 8
|
|
#define GPIO69_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO69_FUNC_WPD_OFFSET 7
|
|
#define GPIO69_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO69_FUNC_SEL_OFFSET 4
|
|
#define GPIO69_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO69_SLP_WPU_OFFSET 3
|
|
#define GPIO69_SLP_WPU_MASK 0x00000008
|
|
#define GPIO69_SLP_WPD_OFFSET 2
|
|
#define GPIO69_SLP_WPD_MASK 0x00000004
|
|
#define GPIO69_SLP_IE_OFFSET 1
|
|
#define GPIO69_SLP_IE_MASK 0x00000002
|
|
#define GPIO69_SLP_OE_OFFSET 0
|
|
#define GPIO69_SLP_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO70_PIN_CFG_ADDR 0x11c
|
|
#define GPIO70_SEC_OFFSET 21
|
|
#define GPIO70_SEC_MASK 0x00200000
|
|
#define GPIO70_DRV_OFFSET 19
|
|
#define GPIO70_DRV_MASK 0x00180000
|
|
#define GPIO70_SLP_SEL_OFFSET 18
|
|
#define GPIO70_SLP_SEL_MASK 0x00040000
|
|
#define GPIO70_ODRV_OFFSET 17
|
|
#define GPIO70_ODRV_MASK 0x00020000
|
|
#define GPIO70_IINV_OFFSET 16
|
|
#define GPIO70_IINV_MASK 0x00010000
|
|
#define GPIO70_OINV_OFFSET 15
|
|
#define GPIO70_OINV_MASK 0x00008000
|
|
#define GPIO70_OPOS_OFFSET 14
|
|
#define GPIO70_OPOS_MASK 0x00004000
|
|
#define GPIO70_ONEG_OFFSET 13
|
|
#define GPIO70_ONEG_MASK 0x00002000
|
|
#define GPIO70_IPOS_OFFSET 12
|
|
#define GPIO70_IPOS_MASK 0x00001000
|
|
#define GPIO70_INEG_OFFSET 11
|
|
#define GPIO70_INEG_MASK 0x00000800
|
|
#define GPIO70_ORE_OFFSET 10
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#define GPIO70_ORE_MASK 0x00000400
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#define GPIO70_IRE_OFFSET 9
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#define GPIO70_IRE_MASK 0x00000200
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#define GPIO70_FUNC_WPU_OFFSET 8
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#define GPIO70_FUNC_WPU_MASK 0x00000100
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#define GPIO70_FUNC_WPD_OFFSET 7
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#define GPIO70_FUNC_WPD_MASK 0x00000080
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#define GPIO70_FUNC_SEL_OFFSET 4
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#define GPIO70_FUNC_SEL_MASK 0x00000070
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#define GPIO70_SLP_WPU_OFFSET 3
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#define GPIO70_SLP_WPU_MASK 0x00000008
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#define GPIO70_SLP_WPD_OFFSET 2
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#define GPIO70_SLP_WPD_MASK 0x00000004
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#define GPIO70_SLP_IE_OFFSET 1
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#define GPIO70_SLP_IE_MASK 0x00000002
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#define GPIO70_SLP_OE_OFFSET 0
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#define GPIO70_SLP_OE_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO71_PIN_CFG_ADDR 0x120
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#define GPIO71_SEC_OFFSET 21
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#define GPIO71_SEC_MASK 0x00200000
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#define GPIO71_DRV_OFFSET 19
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#define GPIO71_DRV_MASK 0x00180000
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#define GPIO71_SLP_SEL_OFFSET 18
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#define GPIO71_SLP_SEL_MASK 0x00040000
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#define GPIO71_ODRV_OFFSET 17
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#define GPIO71_ODRV_MASK 0x00020000
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#define GPIO71_IINV_OFFSET 16
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#define GPIO71_IINV_MASK 0x00010000
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#define GPIO71_OINV_OFFSET 15
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#define GPIO71_OINV_MASK 0x00008000
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#define GPIO71_OPOS_OFFSET 14
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#define GPIO71_OPOS_MASK 0x00004000
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#define GPIO71_ONEG_OFFSET 13
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#define GPIO71_ONEG_MASK 0x00002000
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#define GPIO71_IPOS_OFFSET 12
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#define GPIO71_IPOS_MASK 0x00001000
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#define GPIO71_INEG_OFFSET 11
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#define GPIO71_INEG_MASK 0x00000800
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#define GPIO71_ORE_OFFSET 10
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#define GPIO71_ORE_MASK 0x00000400
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#define GPIO71_IRE_OFFSET 9
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#define GPIO71_IRE_MASK 0x00000200
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#define GPIO71_FUNC_WPU_OFFSET 8
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#define GPIO71_FUNC_WPU_MASK 0x00000100
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#define GPIO71_FUNC_WPD_OFFSET 7
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#define GPIO71_FUNC_WPD_MASK 0x00000080
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#define GPIO71_FUNC_SEL_OFFSET 4
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#define GPIO71_FUNC_SEL_MASK 0x00000070
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#define GPIO71_SLP_WPU_OFFSET 3
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#define GPIO71_SLP_WPU_MASK 0x00000008
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#define GPIO71_SLP_WPD_OFFSET 2
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#define GPIO71_SLP_WPD_MASK 0x00000004
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#define GPIO71_SLP_IE_OFFSET 1
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#define GPIO71_SLP_IE_MASK 0x00000002
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#define GPIO71_SLP_OE_OFFSET 0
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#define GPIO71_SLP_OE_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO72_PIN_CFG_ADDR 0x124
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#define GPIO72_SEC_OFFSET 21
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#define GPIO72_SEC_MASK 0x00200000
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#define GPIO72_DRV_OFFSET 19
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#define GPIO72_DRV_MASK 0x00180000
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#define GPIO72_SLP_SEL_OFFSET 18
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#define GPIO72_SLP_SEL_MASK 0x00040000
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#define GPIO72_ODRV_OFFSET 17
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#define GPIO72_ODRV_MASK 0x00020000
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#define GPIO72_IINV_OFFSET 16
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#define GPIO72_IINV_MASK 0x00010000
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#define GPIO72_OINV_OFFSET 15
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#define GPIO72_OINV_MASK 0x00008000
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#define GPIO72_OPOS_OFFSET 14
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#define GPIO72_OPOS_MASK 0x00004000
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#define GPIO72_ONEG_OFFSET 13
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#define GPIO72_ONEG_MASK 0x00002000
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#define GPIO72_IPOS_OFFSET 12
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#define GPIO72_IPOS_MASK 0x00001000
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#define GPIO72_INEG_OFFSET 11
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#define GPIO72_INEG_MASK 0x00000800
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#define GPIO72_ORE_OFFSET 10
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#define GPIO72_ORE_MASK 0x00000400
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#define GPIO72_IRE_OFFSET 9
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#define GPIO72_IRE_MASK 0x00000200
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#define GPIO72_FUNC_WPU_OFFSET 8
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#define GPIO72_FUNC_WPU_MASK 0x00000100
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#define GPIO72_FUNC_WPD_OFFSET 7
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#define GPIO72_FUNC_WPD_MASK 0x00000080
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#define GPIO72_FUNC_SEL_OFFSET 4
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#define GPIO72_FUNC_SEL_MASK 0x00000070
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#define GPIO72_SLP_WPU_OFFSET 3
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#define GPIO72_SLP_WPU_MASK 0x00000008
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#define GPIO72_SLP_WPD_OFFSET 2
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#define GPIO72_SLP_WPD_MASK 0x00000004
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#define GPIO72_SLP_IE_OFFSET 1
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#define GPIO72_SLP_IE_MASK 0x00000002
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#define GPIO72_SLP_OE_OFFSET 0
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#define GPIO72_SLP_OE_MASK 0x00000001
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|
//-----------------------------------
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#define CFG_GPIO73_PIN_CFG_ADDR 0x128
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#define GPIO73_SEC_OFFSET 21
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|
#define GPIO73_SEC_MASK 0x00200000
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#define GPIO73_DRV_OFFSET 19
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|
#define GPIO73_DRV_MASK 0x00180000
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|
#define GPIO73_SLP_SEL_OFFSET 18
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|
#define GPIO73_SLP_SEL_MASK 0x00040000
|
|
#define GPIO73_ODRV_OFFSET 17
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|
#define GPIO73_ODRV_MASK 0x00020000
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|
#define GPIO73_IINV_OFFSET 16
|
|
#define GPIO73_IINV_MASK 0x00010000
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|
#define GPIO73_OINV_OFFSET 15
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|
#define GPIO73_OINV_MASK 0x00008000
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#define GPIO73_OPOS_OFFSET 14
|
|
#define GPIO73_OPOS_MASK 0x00004000
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#define GPIO73_ONEG_OFFSET 13
|
|
#define GPIO73_ONEG_MASK 0x00002000
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#define GPIO73_IPOS_OFFSET 12
|
|
#define GPIO73_IPOS_MASK 0x00001000
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|
#define GPIO73_INEG_OFFSET 11
|
|
#define GPIO73_INEG_MASK 0x00000800
|
|
#define GPIO73_ORE_OFFSET 10
|
|
#define GPIO73_ORE_MASK 0x00000400
|
|
#define GPIO73_IRE_OFFSET 9
|
|
#define GPIO73_IRE_MASK 0x00000200
|
|
#define GPIO73_FUNC_WPU_OFFSET 8
|
|
#define GPIO73_FUNC_WPU_MASK 0x00000100
|
|
#define GPIO73_FUNC_WPD_OFFSET 7
|
|
#define GPIO73_FUNC_WPD_MASK 0x00000080
|
|
#define GPIO73_FUNC_SEL_OFFSET 4
|
|
#define GPIO73_FUNC_SEL_MASK 0x00000070
|
|
#define GPIO73_SLP_WPU_OFFSET 3
|
|
#define GPIO73_SLP_WPU_MASK 0x00000008
|
|
#define GPIO73_SLP_WPD_OFFSET 2
|
|
#define GPIO73_SLP_WPD_MASK 0x00000004
|
|
#define GPIO73_SLP_IE_OFFSET 1
|
|
#define GPIO73_SLP_IE_MASK 0x00000002
|
|
#define GPIO73_SLP_OE_OFFSET 0
|
|
#define GPIO73_SLP_OE_MASK 0x00000001
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|
|
|
//HW module read/write macro
|
|
#define PIN_RF_READ_REG(addr) SOC_READ_REG(PIN_RF_BASEADDR + addr)
|
|
#define PIN_RF_WRITE_REG(addr,value) SOC_WRITE_REG(PIN_RF_BASEADDR + addr,value)
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