125 lines
3.8 KiB
C
125 lines
3.8 KiB
C
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "mac_key_hw.h"
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#include "mac_avln.h"
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#include "mac_sys_reg.h"
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#include "mac_rx_reg.h"
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#include "hw_reg_api.h"
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/* HW key related function placed here */
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/* set avln's nid to HW */
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uint32_t mac_key_hw_set_avln_nid(uint8_t avln_idx, nid_t nid)
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{
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(void)nid;
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IOT_ASSERT(avln_idx < MAX_AVLN_NUM);
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switch(avln_idx){
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case AES_VLAN0:
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RGF_RX_WRITE_REG(CFG_VLAN0_NID_ADDR, nid);
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break;
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case AES_VLAN1:
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RGF_RX_WRITE_REG(CFG_VLAN1_NID_ADDR, nid);
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break;
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case AES_VLAN2:
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RGF_RX_WRITE_REG(CFG_VLAN2_NID_ADDR, nid);
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break;
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case AES_VLAN3:
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RGF_RX_WRITE_REG(CFG_VLAN3_NID_ADDR, nid);
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break;
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case AES_VLAN4:
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RGF_RX_WRITE_REG(CFG_VLAN4_NID_ADDR, nid);
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break;
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case AES_VLAN5:
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RGF_RX_WRITE_REG(CFG_VLAN5_NID_ADDR, nid);
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break;
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case AES_VLAN6:
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RGF_RX_WRITE_REG(CFG_VLAN6_NID_ADDR, nid);
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break;
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case AES_VLAN7:
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RGF_RX_WRITE_REG(CFG_VLAN7_NID_ADDR, nid);
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break;
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default:
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IOT_ASSERT(0);
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break;
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}
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return 0;
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}
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/* get avln's nid to HW
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* return nid if successful, else return INV NID
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*/
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uint32_t mac_key_hw_get_avln_nid(uint8_t avln_idx)
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{
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IOT_ASSERT(avln_idx < MAX_AVLN_NUM);
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switch(avln_idx){
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case AES_VLAN0:
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return RGF_RX_READ_REG(CFG_VLAN0_NID_ADDR);
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case AES_VLAN1:
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return RGF_RX_READ_REG(CFG_VLAN1_NID_ADDR);
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case AES_VLAN2:
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return RGF_RX_READ_REG(CFG_VLAN2_NID_ADDR);
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case AES_VLAN3:
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return RGF_RX_READ_REG(CFG_VLAN3_NID_ADDR);
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case AES_VLAN4:
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return RGF_RX_READ_REG(CFG_VLAN4_NID_ADDR);
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case AES_VLAN5:
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return RGF_RX_READ_REG(CFG_VLAN5_NID_ADDR);
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case AES_VLAN6:
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return RGF_RX_READ_REG(CFG_VLAN6_NID_ADDR);
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case AES_VLAN7:
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return RGF_RX_READ_REG(CFG_VLAN7_NID_ADDR);
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default:
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IOT_ASSERT(0);
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}
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return 0;
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}
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/* set key table for avln to hw */
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uint32_t mac_key_hw_set_avln_key_tlb(uint8_t avln_idx, void *key_tbl_ptr)
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{
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(void)key_tbl_ptr;
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IOT_ASSERT(avln_idx < MAX_AVLN_NUM);
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switch(avln_idx){
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case AES_VLAN0:
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RGF_MAC_WRITE_REG(CFG_VLAN0_AES_TBL_ADDR, (uint32_t)key_tbl_ptr);
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break;
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case AES_VLAN1:
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RGF_MAC_WRITE_REG(CFG_VLAN1_AES_TBL_ADDR, (uint32_t)key_tbl_ptr);
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break;
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case AES_VLAN2:
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RGF_MAC_WRITE_REG(CFG_VLAN2_AES_TBL_ADDR, (uint32_t)key_tbl_ptr);
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break;
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case AES_VLAN3:
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RGF_MAC_WRITE_REG(CFG_VLAN3_AES_TBL_ADDR, (uint32_t)key_tbl_ptr);
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break;
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case AES_VLAN4:
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RGF_MAC_WRITE_REG(CFG_VLAN4_AES_TBL_ADDR, (uint32_t)key_tbl_ptr);
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break;
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case AES_VLAN5:
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RGF_MAC_WRITE_REG(CFG_VLAN5_AES_TBL_ADDR, (uint32_t)key_tbl_ptr);
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break;
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case AES_VLAN6:
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RGF_MAC_WRITE_REG(CFG_VLAN6_AES_TBL_ADDR, (uint32_t)key_tbl_ptr);
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break;
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case AES_VLAN7:
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RGF_MAC_WRITE_REG(CFG_VLAN7_AES_TBL_ADDR, (uint32_t)key_tbl_ptr);
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break;
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default:
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IOT_ASSERT(0);
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break;
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}
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return 0;
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} |