239 lines
7.7 KiB
C
239 lines
7.7 KiB
C
/****************************************************************************
|
|
|
|
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
|
|
|
|
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
|
|
be copied by any method or incorporated into another program without
|
|
the express written consent of Aerospace C.Power. This Information or any portion
|
|
thereof remains the property of Aerospace C.Power. The Information contained herein
|
|
is believed to be accurate and Aerospace C.Power assumes no responsibility or
|
|
liability for its use in any way and conveys no license or title under
|
|
any patent or copyright and makes no representation or warranty that this
|
|
Information is free from patent or copyright infringement.
|
|
|
|
****************************************************************************/
|
|
|
|
#ifndef _BB_CPU_FSM_H_
|
|
#define _BB_CPU_FSM_H_
|
|
|
|
/* os shim includes */
|
|
#include "os_types.h"
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
#define BB_MAX_TIME 0xffffffffUL
|
|
|
|
/* enter idle state reason is normal fllow */
|
|
#define BB_CPU_ENTER_IDLE_NOR 0
|
|
/* enter idle state reason is reset */
|
|
#define BB_CPU_ENTER_IDLE_RST 1
|
|
|
|
/* bb cpu global finite state machine */
|
|
typedef enum{
|
|
/* bb cpu is idle state */
|
|
BB_CPU_STATE_IDLE = 0,
|
|
/* bb cpu is tx state */
|
|
BB_CPU_STATE_TX = 1,
|
|
/* bb cpu is rx state */
|
|
BB_CPU_STATE_RX = 2,
|
|
/* bb cpu is reset state */
|
|
BB_CPU_STATE_RST = 3,
|
|
} BB_CPU_GLB_STATE;
|
|
|
|
/* bb cpu tx state finite state machine */
|
|
typedef enum{
|
|
/* bb cpu tx idle state */
|
|
BB_CPU_TX_STATE_IDLE = 0,
|
|
/* bb cpu tx is wait tx complete state */
|
|
BB_CPU_TX_STATE_WAIT_COMPLETE = 1,
|
|
} BB_CPU_TX_STATE;
|
|
|
|
/* bb cpu rx state finite state machine */
|
|
typedef enum{
|
|
/* bb cpu rx is wait rx idle state */
|
|
BB_CPU_RX_STATE_IDLE = 0,
|
|
/* bb cpu rx is rx listening state */
|
|
BB_CPU_RX_STATE_LISTENING = 1,
|
|
/* bb cpu rx is wait phy header interrupt state */
|
|
BB_CPU_RX_STATE_WAIT_PHR = 2,
|
|
/* bb cpu rx is wait payload interrupt state */
|
|
BB_CPU_RX_STATE_WAIT_PLD = 3,
|
|
/* bb cpu rx is rx complete state */
|
|
BB_CPU_RX_STATE_RX_COMPLETE = 4,
|
|
/* bb cpu rx is wait sack tx complete state */
|
|
BB_CPU_RX_STATE_WAIT_SACK_TX_COMPLETE = 5,
|
|
} BB_CPU_RX_STATE;
|
|
|
|
/* bb cpu reset state finite state machine */
|
|
typedef enum{
|
|
/* bb cpu reset is idle state */
|
|
BB_CPU_RST_STATE_IDLE = 0,
|
|
/* bb cpu reset is wait tx complete state */
|
|
BB_CPU_RST_STATE_WAIT_TX_COMPLETE = 1,
|
|
/* bb cpu reset is wait rx pld start state */
|
|
BB_CPU_RST_STATE_WAIT_RX_PLD_START = 2,
|
|
} BB_CPU_RST_STATE;
|
|
|
|
/* bb cpu event id
|
|
* NOTE: the lower the number, the higher the priority.
|
|
*/
|
|
typedef enum{
|
|
/* bb cpu power save idle event id */
|
|
BB_CPU_EVENT_PS_IDLE_ID = 1,
|
|
/* bb cpu bb csma tx check event id */
|
|
BB_CPU_EVENT_CSMA_TX_CHECK_ID = 2,
|
|
/* bb cpu bb set channel event id */
|
|
BB_CPU_EVENT_SET_CHANNEL_ID = 3,
|
|
/* bb cpu cmdlist done event id */
|
|
BB_CPU_EVENT_CMDLIST_DONE_ID = 4,
|
|
/* bb cpu enter reset state event id */
|
|
BB_CPU_EVENT_RST_ID = 5,
|
|
/* bb cpu enter wait rx complete event id */
|
|
BB_CPU_EVENT_RST_WAIT_RX_COMPLETE_ID = 6,
|
|
/* bb cpu enter wait tx done event id */
|
|
BB_CPU_EVENT_RST_WAIT_TX_DONE_ID = 7,
|
|
/* bb cpu enter reset timeout state event id */
|
|
BB_CPU_EVENT_RST_TIMEOUT_ID = 8,
|
|
/* bb cpu mac rx start event id */
|
|
BB_CPU_EVENT_MAC_RX_START_ID = 9,
|
|
/* bb cpu enter rx abort event id */
|
|
BB_CPU_EVENT_RX_ABORT_ID = 10,
|
|
/* bb cpu enter backoff timeout event id */
|
|
BB_CPU_EVENT_BACKOFF_TIMEOUT_ID = 11,
|
|
/* bb cpu rx sig event id */
|
|
BB_CPU_EVENT_RX_SIG_ID = 12,
|
|
/* bb cpu rx phy header event id */
|
|
BB_CPU_EVENT_RX_PHR_ID = 13,
|
|
/* bb cpu rx pld start event id */
|
|
BB_CPU_EVENT_RX_PLD_START_ID = 14,
|
|
/* bb cpu rx backfill desc event id */
|
|
BB_CPU_EVENT_RX_BACKFILL_DESC_ID = 15,
|
|
/* bb cpu rx timeout event id */
|
|
BB_CPU_EVENT_RX_TIMEOUT_ID = 16,
|
|
/* bb cpu wait sack timeout event id */
|
|
BB_CPU_EVENT_WAIT_SACK_TIMEOUT_ID = 17,
|
|
/* bb cpu mac tx start event id */
|
|
BB_CPU_EVENT_MAC_TX_START_ID = 18,
|
|
/* bb cpu tx abort event id */
|
|
BB_CPU_EVENT_TX_ABORT_ID = 19,
|
|
/* bb cpu mac fill tx info event id */
|
|
BB_CPU_EVENT_MAC_TX_FILL_INFO_ID = 20,
|
|
/* bb cpu tx complete event id */
|
|
BB_CPU_EVENT_TX_COMP_ID = 21,
|
|
/* bb cpu tx timeout event id */
|
|
BB_CPU_EVENT_TX_TIMEOUT_ID = 22,
|
|
/* bb cpu bb init event id */
|
|
BB_CPU_EVENT_BB_INIT_ID = 23,
|
|
/* bb cpu sync spi event id */
|
|
BB_CPU_EVENT_SYNC_SPI_ID = 24,
|
|
/* bb cpu tx tone event id */
|
|
BB_CPU_EVENT_TX_TONE_ID = 25,
|
|
/* bb cpu tx cal update event id */
|
|
BB_CPU_EVENT_TX_CAL_UPDATE_ID = 26,
|
|
BB_CPU_EVENT_MAX,
|
|
} BB_CPU_EVENT_ID;
|
|
|
|
/* the macros indicate the reason bb cpu enter reset state.
|
|
* just enter reset state have this reason.
|
|
*/
|
|
/* enter reset mode reason is invaild */
|
|
#define BB_CPU_TO_RST_IS_INVALID 0
|
|
/* enter reset mode reason is stop schedule */
|
|
#define BB_CPU_TO_RST_IS_STOP_SCHE 1
|
|
/* enter reset mode reason is rx abort */
|
|
#define BB_CPU_TO_RST_IS_RX_ABORT 2
|
|
/* enter reset mode reason is cmdlist done */
|
|
#define BB_CPU_TO_RST_IS_CMDLIST_DONE 3
|
|
/* enter reset mode reason is tx abort */
|
|
#define BB_CPU_TO_RST_IS_TX_ABORT 4
|
|
|
|
/* the macros indicate the reason bb cpu trigger bb.*/
|
|
/* define bb cpu trigger bb event bit 0/1 to tx */
|
|
#define BB_CPU_TRIGGER_BB_TX 1
|
|
/* define bb cpu trigger bb event bit 2/3 to rx */
|
|
#define BB_CPU_TRIGGER_BB_RX 2
|
|
|
|
/* define the margin of tx timeout, uint us */
|
|
#define BB_CPU_TX_TIMEOUT_MARGIN 1000
|
|
|
|
/* define the margin of vcs by phr calculate, uint us 20ms */
|
|
#define BB_CPU_VCS_MARGIN (20000)
|
|
|
|
/* define bbcpu after rx done interval to tx, uint us 400us */
|
|
#define BB_CPU_VCS_INTERVAL (400)
|
|
|
|
/*
|
|
* bb_cpu_fsm_main() - bb cpu fsm main.
|
|
* return: void.
|
|
*/
|
|
void bb_cpu_fsm_main();
|
|
|
|
/*
|
|
* bb_cpu_set_event() - bb set event.
|
|
* event_id - event id. see BB_CPU_EVENT_ID.
|
|
* return: void.
|
|
*/
|
|
void bb_cpu_set_event(uint32_t event_id);
|
|
|
|
/*
|
|
* bb_cpu_set_event_from_isr() - bb set event from isr.
|
|
* event_id - event id. see BB_CPU_TRIGGER_BB_xx.
|
|
* return: void.
|
|
*/
|
|
void bb_cpu_set_event_from_isr(uint32_t event_id);
|
|
|
|
/*
|
|
* bb_cpu_set_vcs_timer_from_isr() - bb set vcs timer from isr.
|
|
* time_us - timer us.
|
|
* is_force - is force set or not.
|
|
* return: void.
|
|
*/
|
|
void bb_cpu_set_vcs_timer_from_isr(uint32_t time_us, uint32_t is_force);
|
|
|
|
/*
|
|
* bb_cpu_stop_vcs_working_from_isr() - bb cpu stop vcs working from isr.
|
|
* void - void.
|
|
* return: void.
|
|
*/
|
|
void bb_cpu_stop_vcs_working_from_isr();
|
|
|
|
/*
|
|
* bb_cpu_set_isr_vaild_from_isr() - bb set isr vaild from isr.
|
|
* is_vaild - is vaild or not.
|
|
* return: void.
|
|
*/
|
|
void bb_cpu_set_isr_vaild_from_isr(uint8_t is_vaild);
|
|
|
|
/*
|
|
* bb_cpu_trigger_bb() - bb cpu trigger bb.
|
|
* reason - event id. see BB_CPU_EVENT_ID.
|
|
* return: void.
|
|
*/
|
|
void bb_cpu_trigger_bb(uint32_t reason);
|
|
|
|
/*
|
|
* bb_cpu_fsm_init() - bb cpu fsm init.
|
|
* return: void.
|
|
*/
|
|
void bb_cpu_fsm_init();
|
|
|
|
/*
|
|
* bb_cpu_get_tx_pwr() - bb cpu get current wphy tx power.
|
|
* return: return tx power, uint is dBm
|
|
*/
|
|
int8_t bb_cpu_get_tx_pwr();
|
|
|
|
/*
|
|
* bb_cpu_get_proto() - bb cpu get protocol.
|
|
* return: return protocol
|
|
*/
|
|
uint32_t bb_cpu_get_proto();
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif // _BB_CPU_FSM_H_
|