kunlun/driver/src/hw3/inc/dma.h

/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/
#ifndef _DRIVER_HW_DMA_H
#define _DRIVER_HW_DMA_H

#ifdef __cplusplus
extern "C" {
#endif

typedef enum {
    DMA_CONTROLLER0,
    DMA_CONTROLLER1,
    DMA_CONTROLLER2,
    DMA_CONTROLLER_MAX,
    DMA_CONTROLLER_NONE,
} DMA_CONTROLLER;

typedef enum {
    DMA_CHANNEL_0 = 0,
    DMA_CHANNEL_1,
    DMA_CHANNEL_2,
    DMA_CHANNEL_3,
    DMA_CHANNEL_4,
    DMA_CHANNEL_5,
    DMA_CHANNEL_6,
    DMA_CHANNEL_7,
    DMA_CHANNEL_8,
    DMA_CHANNEL_9,
    DMA_CHANNEL_10,
    DMA0_CHANNEL_MAX, /* dma 0 only support 11 channel */
    DMA1_CHANNEL_MAX = DMA_CHANNEL_10, /* dma 1 only support 10 channel */
    DMA2_CHANNEL_MAX = DMA_CHANNEL_4, /* dma 2 only support 4 channel */

    DMA_CHANNEL_MAX = DMA0_CHANNEL_MAX,
    DMA_CHANNEL_NONE = 0xFF,
} DMA_CHANNEL_ID;

typedef enum {
    DMA_INT_0,
    DMA_INT_1,
    DMA_INT_2,
    DMA_INT_3,
    DMA_INT_MAX,
} DMA_INT_ID;

typedef enum {
    DMA_CRC_0,
    DMA_CRC_1,
    DMA_CRC_MAX,
    DMA_CRC_NONE = DMA_CRC_MAX,
} DMA_CRC_ID;

typedef enum {
    DMA_CKSUM_0,
    DMA_CKSUM_1,
    DMA_CKSUM_MAX,
    DMA_CKSUM_NONE = DMA_CKSUM_MAX,
} DMA_CKSUM_ID;

typedef enum {
    DMA_BURST_LEN_0,
    DMA_BURST_LEN_1,
    DMA_BURST_LEN_2,
    DMA_BURST_LEN_3,
    DMA_BURST_LEN_4,
    DMA_BURST_LEN_5,
    DMA_BURST_LEN_6,
    DMA_BURST_LEN_7,
    DMA_BURST_LEN_8,
    DMA_BURST_LEN_9,
    DMA_BURST_LEN_10,
    DMA_BURST_LEN_11,
    DMA_BURST_LEN_12,
    DMA_BURST_LEN_13,
    DMA_BURST_LEN_14,
    DMA_BURST_LEN_15,
} DMA_BURST_LEN;

typedef enum {
    // for dma0
    DMA0_PERI_RESERVED = 0,
    DMA0_PERI_ADA,
    DMA0_PERI_UART0_RX,
    DMA0_PERI_UART0_TX,
    DMA0_PERI_UART1_RX,
    DMA0_PERI_UART1_TX,
    DMA0_PERI_UART2_RX,
    DMA0_PERI_UART2_TX,
    DMA0_PERI_SPI_M0_RX,
    DMA0_PERI_SPI_M0_TX,
    DMA0_PERI_SPI_S0_RX,
    DMA0_PERI_SPI_S0_TX,
    DMA0_PERI_SADC,
    DMA0_PERI_MAX,
    // for dma1
    DMA1_PERI_RESERVED = 0,
    DMA1_PERI_UART4_RX,
    DMA1_PERI_UART4_TX,
    DMA1_PERI_UART5_RX,
    DMA1_PERI_UART5_TX,
    DMA1_PERI_UART6_RX,
    DMA1_PERI_UART6_TX,
    DMA1_PERI_SPI_M2_RX,
    DMA1_PERI_SPI_M2_TX,
    DMA1_PERI_TPID,
    DMA1_PERI_MAX,
    // for dma2
    DMA2_PERI_RESERVED = 0,
    DMA2_PERI_WPHY_TX,
    DMA2_PERI_WPHY_RX,
    DMA2_PERI_WPHY_STX,
    DMA2_PERI_MAX,

    DMA_PERI_REQ_NONE = 0xFF,
} DMA_PERI_REQ;

typedef enum {
    DMA_DATA_WIDTH_WORD = 0,//1word
    DMA_DATA_WIDTH_BYTE = 1,//1bytes
    DMA_DATA_WIDTH_HALF_WORD = 2,//2bytes
} DMA_DATA_WIDTH;

typedef enum {
    DMA_TRANS_MEM_TO_MEM,
    DMA_TRANS_MEM_TO_PERI,
    DMA_TRANS_PERI_TO_MEM,
    DMA_TRANS_PERI_TO_PERI,
} DMA_TRANS_TYPE;

typedef enum {
    DMA_LITTLE_ENDIAN,
    DMA_BIG_ENDIAN,
} DMA_WORD_ORDER;

typedef enum {
    DMA_MSB_LSB,
    DMA_LSB_MSB,
} DMA_BIT_ORDER;

typedef enum {
    DMA_CH_PRIORITY_LOW,
    DMA_CH_PRIORITY_HIGH,
} DMA_CH_PRIORITY;

typedef enum {
    DMA_WRAP_NORMAL,
    DMA_WRAP_4_BEAT_BURST,
    DMA_WRAP_8_BEAT_BURST,
    DMA_WRAP_16_BEAT_BURST,
    DMA_WRAP_MODE_MAX,
} DMA_WRAP_MODE;

typedef enum {
    /* 当前的descriptor的owner没有被置1，会触发此中断 */
    DMA_INT_DECR_IS_NOT_HW,
    /* 所有的descriptor做完会触发这个中断 */
    DMA_INT_ALL_DECR,
    /* 当前的descriptor做完会触发这个中断 */
    DMA_INT_CURR_DECR,
    /* 当RX作为PERI，所以这个中断会在dma_ack回过以后会触发 */
    DMA_INT_HW_ACK,
    /* 当读取回来的 descriptor，检测buff addr为空地址时，会触发此中断 */
    DMA_INT_BUFF_ADDR_NULL,
    /* 使用suspend之后，硬件suspend了，会触发此中断 */
    DMA_INT_SUSPEND,
    /* 使用stop之后，会触发此中断 */
    DMA_INT_STOP,
    DMA_INT_TYPE_MAX,
} DMA_INT_TYPE;

typedef struct dma_descriptor {
    uint32_t buf_size : 24;
    uint32_t int_eb : 1;
    uint32_t acc_start : 1;
    uint32_t acc_end : 1;
    uint32_t reserved : 2;
    uint32_t decr_pause : 1;
    uint32_t stop_flag : 1;
    uint32_t owner : 1;
    uint32_t src_addr;
    uint32_t dst_addr;
    struct dma_descriptor *next;
} dma_descriptor_t;

typedef struct dma_ch_config {
    DMA_TRANS_TYPE trans_type;
    DMA_DATA_WIDTH src_data_width;
    DMA_DATA_WIDTH dst_data_width;
    DMA_BIT_ORDER src_bit_order;
    DMA_BIT_ORDER dst_bit_order;
    DMA_WORD_ORDER src_word_order;
    DMA_WORD_ORDER dst_word_order;
    uint8_t src_burst_length;
    uint8_t dst_burst_length;
    bool_t src_addr_increase;
    bool_t dst_addr_increase;
} dma_ch_config_t;

bool_t dma_is_channel_idle(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch);
DMA_CHANNEL_ID dma_claim_channel(DMA_CONTROLLER dma);
void dma_release_channel(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch);
bool_t dma_is_crc_idle(DMA_CONTROLLER dma, DMA_CRC_ID crc);
DMA_CRC_ID dma_claim_crc(DMA_CONTROLLER dma);
void dma_release_crc(DMA_CONTROLLER dma, DMA_CRC_ID ch);
bool_t dma_is_cksum_idle(DMA_CONTROLLER dma, DMA_CKSUM_ID cksum);
DMA_CKSUM_ID dma_claim_cksum(DMA_CONTROLLER dma);
void dma_release_cksum(DMA_CONTROLLER dma, DMA_CKSUM_ID cksum);
void dma_clk_enable(DMA_CONTROLLER dma);
void dma_init(DMA_CONTROLLER dma);
void dma_deinit(DMA_CONTROLLER dma);
void dma_fifo_soft_rst(DMA_CONTROLLER dma);
void dma_rx_soft_rst(DMA_CONTROLLER dma);
void dma_tx_soft_rst(DMA_CONTROLLER dma);
void dma_channel_start(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch);
void dma_channel_stop(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch);
void dma_channel_reset(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch);
void dma_channel_suspend(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch, bool_t eb);
void dma_channel_int_select(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch, DMA_INT_ID n);
uint8_t dma_get_ch_max_burst_length(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch);
void dma_set_channel_descriptor(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch,
                                   dma_descriptor_t *desc);
void dma_set_channel_config(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch,
                            const dma_ch_config_t *ch_cfg);
DMA_TRANS_TYPE dma_get_channel_trans_type(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch);
void dma_set_channel_priority(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch,
                              DMA_CH_PRIORITY priority);
void dma_set_channel_request(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch, DMA_PERI_REQ req);
void dma_set_wrap_type(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch,
                        DMA_WRAP_MODE tx_wrap, DMA_WRAP_MODE rx_wrap);
uint32_t dma_get_ch_int_status(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch);
void dma_channel_int_enable(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch, DMA_INT_TYPE id);
void dma_channel_int_disable(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch, DMA_INT_TYPE id);
void dma_channel_int_clear(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch, DMA_INT_TYPE id);
void dma_channel_int_clear_all(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch);
void dma_channel_int_clear_bits(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch,
                           uint32_t clear_bits);
void dma_owner_eb_ignore(DMA_CONTROLLER dma, DMA_CHANNEL_ID ch);
void dma_crc_chn_id(DMA_CONTROLLER dma, DMA_CRC_ID crc, DMA_CHANNEL_ID ch);
void dma_crc_mode(DMA_CONTROLLER dma, DMA_CRC_ID crc, uint8_t mode);
bool_t dma_crc_out_done(DMA_CONTROLLER dma, DMA_CRC_ID crc);
void dma_crc_init(DMA_CONTROLLER dma, DMA_CRC_ID crc);
void dma_crc_eb(DMA_CONTROLLER dma, DMA_CRC_ID crc, bool_t eb);
uint32_t dma_crc_out(DMA_CONTROLLER dma, DMA_CRC_ID crc);
void dma_crc_polynomial(DMA_CONTROLLER dma, DMA_CRC_ID crc, uint32_t polynomial);
uint16_t dma_cksum_out(DMA_CONTROLLER dma, DMA_CKSUM_ID cksum);
void dma_cksum_id(DMA_CONTROLLER dma, DMA_CKSUM_ID cksum, DMA_CHANNEL_ID ch);
void dma_cksum_init(DMA_CONTROLLER dma, DMA_CKSUM_ID cksum);
void dma_cksum_eb(DMA_CONTROLLER dma, DMA_CKSUM_ID cksum, bool_t eb);
void dma_crc_claim_cfg(DMA_CONTROLLER dma, DMA_CRC_ID *crc, DMA_CHANNEL_ID ch,
    uint8_t mode, uint32_t polynomial);
void dma_crc_free_cfg(DMA_CONTROLLER dma, DMA_CRC_ID crc);
void dma_cksum_claim_cfg(DMA_CONTROLLER dma, DMA_CKSUM_ID *cksum, DMA_CHANNEL_ID ch);
void dma_cksum_free_cfg(DMA_CONTROLLER dma, DMA_CKSUM_ID cksum);

uint8_t dma_get_peri_req_max_cnt(DMA_CONTROLLER dma);
uint8_t dma_get_channel_max_cnt(DMA_CONTROLLER dma);

#ifdef __cplusplus
}
#endif

#endif /* _DRIVER_HW_DMA_H */