diff --git a/cpu.py b/cpu.py
index ddeda0a..ac7b72d 100644
--- a/cpu.py
+++ b/cpu.py
@@ -111,12 +111,65 @@ class cpu(object):
 # 在指定寄存器不为0时跳转
 #             1010_0010_0000_0000_juge_reg[8]_reg[8]
 
+# 栈操作指令   1011_xxxx_0000_0000_0000_0000_0000_0000
+# 所有寄存器入栈 fp sp rp regs[32]
+#             1011_0000_0000_0000_0000_0000_0000_0000
+# 所有寄存器出栈 fp sp rp regs[32]
+#             1011_0001_0000_0000_0000_0000_0000_0000
+# 栈增一个字长 并在原栈位置设置初值
+#             1011_0010_0000_0000_0000_0000_reg[8]
+# 栈增reg_num个字长 并在原栈位置reg_addr所指地址的初值
+#             1011_0011_0000_0000_reg_num[8]_reg_addr[8]
+# 栈减reg_num个字长
+#             1011_0100_0000_0000_0000_0000_reg_num[8]
+
 
 class instruction(object):
   def __init__(self) -> None:
-    self.jmp
-
+    pass
+  def add(self,src1:int,src2:int,dst:int):
+    return (0x81<<24)|(src1<<16)|(src2<<8)|(dst)
+  def sub(self,src1:int,src2:int,dst:int):
+    return (0x82<<24)|(src1<<16)|(src2<<8)|(dst)
+  def mul(self,src1:int,src2:int,dst:int):
+    return (0x83<<24)|(src1<<16)|(src2<<8)|(dst)
+  def div(self,src1:int,src2:int,dst:int):
+    return (0x84<<24)|(src1<<16)|(src2<<8)|(dst)
+  def bitand(self,src1:int,src2:int,dst:int):
+    return (0x85<<24)|(src1<<16)|(src2<<8)|(dst)
+  def bitor(self,src1:int,src2:int,dst:int):
+    return (0x86<<24)|(src1<<16)|(src2<<8)|(dst)
+  def bitxor(self,src1:int,src2:int,dst:int):
+    return (0x87<<24)|(src1<<16)|(src2<<8)|(dst)
+  def mov(self,src:int,dst:int):
+    return (0x88<<24)|(src<<8)|(dst)
+  def lsh(self,shift_bit:int,src:int,dst:int):
+    return (0x89<<24)|(shift_bit<<16)|(src<<8)|(dst)
+  def rsh(self,shift_bit:int,src:int,dst:int):
+    return (0x8a<<24)|(shift_bit<<16)|(src<<8)|(dst)
+  def neg(self,src:int,dst:int):
+    return (0x8b<<24)|(src<<8)|(dst)
 
+  def load(self,reg:int,mem_addr_reg:int):
+    return (0x91<<24)|(reg<<8)|(mem_addr_reg)
+  def save(self,reg:int,mem_addr_reg:int):
+    return (0x92<<24)|(reg<<8)|(mem_addr_reg)
 
+  def jmp(self,addr_reg:int):
+    return (0xa0<<24)|(addr_reg)
+  def jmp_zero(self,juge_reg:int,reg:int):
+    return (0xa1<<24)|(juge_reg<<8)|(reg)
+  def jmp_no_zero(self,juge_reg:int,reg:int):
+    return (0xa2<<24)|(juge_reg<<8)|(reg)
 
+  def push_all(self):
+    return (0xb0<<24)
+  def pop_all(self):
+    return (0xb1<<24)
+  def sp_add(self,reg:int):
+    return (0xb2<<24)|(reg)
+  def sp_add_count(self,count_reg:int,data_addr_reg:int):
+    return (0xb3<<24)|(count_reg<<8)|(data_addr_reg)
+  def sp_sub(self,count_reg:int):
+    return (0xb4<<24)|(count_reg)