351 lines
14 KiB
C
351 lines
14 KiB
C
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/**
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******************************************************************************
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* @file stm32f4xx_syscfg.h
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* @author MCD Application Team
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* @version V1.8.0
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* @date 04-November-2016
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* @brief This file contains all the functions prototypes for the SYSCFG firmware
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* library.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4xx_SYSCFG_H
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#define __STM32F4xx_SYSCFG_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx.h"
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/** @addtogroup STM32F4xx_StdPeriph_Driver
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* @{
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*/
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/** @addtogroup SYSCFG
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup SYSCFG_Exported_Constants
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* @{
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*/
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#if defined(STM32F413_423xx)
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/** @defgroup BITSTREAM_CLOCK Bit Stream clock source selection
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* @{
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*/
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#define BITSTREAM_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_BSCKSEL
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#define BITSTREAM_CLOCK_TIM2OC1 (uint32_t)0x00000000
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/**
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* @}
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*/
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/** @defgroup MCHDLY_CLOCK MCHDLY Clock enable
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* @{
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*/
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#define MCHDLY_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_MCHDLY2EN
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#define MCHDLY_CLOCK_DFSDM1 SYSCFG_MCHDLYCR_MCHDLY1EN
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/**
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* @}
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*/
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/** @defgroup DFSDM_CLOCKIN_SOURCE DFSDM Clock In Source Selection
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* @{
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*/
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#define DFSDM2_CKIN_PAD (uint32_t)0x00000000
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#define DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
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#define DFSDM1_CKIN_PAD (uint32_t)0x00000000
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#define DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG
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/**
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* @}
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*/
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/** @defgroup DFSDM_CLOCKOUT_SOURCE DFSDM Clock Source Selection
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* @{
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*/
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#define DFSDM2_CKOUT_DFSDM2 (uint32_t)0x00000000
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#define DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
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#define DFSDM1_CKOUT_DFSDM1 (uint32_t)0x00000000U
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#define DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
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/**
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* @}
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*/
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/** @defgroup DFSDM_DATAIN0_SOURCE DFSDM Source Selection For DATAIN0
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* @{
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*/
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#define DATAIN0_DFSDM2_PAD (uint32_t)0x00000000
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#define DATAIN0_DFSDM2_DATAIN1 SYSCFG_MCHDLYCR_DFSDM2D0SEL
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#define DATAIN0_DFSDM1_PAD (uint32_t)0x00000000
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#define DATAIN0_DFSDM1_DATAIN1 SYSCFG_MCHDLYCR_DFSDM1D0SEL
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/**
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* @}
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*/
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/** @defgroup DFSDM_DATAIN2_SOURCE DFSDM Source Selection For DATAIN2
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* @{
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*/
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#define DATAIN2_DFSDM2_PAD (uint32_t)0x00000000
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#define DATAIN2_DFSDM2_DATAIN3 SYSCFG_MCHDLYCR_DFSDM2D2SEL
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#define DATAIN2_DFSDM1_PAD (uint32_t)0x00000000
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#define DATAIN2_DFSDM1_DATAIN3 SYSCFG_MCHDLYCR_DFSDM1D2SEL
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/**
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* @}
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*/
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/** @defgroup DFSDM_DATAIN4_SOURCE DFSDM Source Selection For DATAIN4
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* @{
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*/
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#define DATAIN4_DFSDM2_PAD (uint32_t)0x00000000
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#define DATAIN4_DFSDM2_DATAIN5 SYSCFG_MCHDLYCR_DFSDM2D4SEL
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/**
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* @}
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*/
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/** @defgroup DFSDM_DATAIN6_SOURCE DFSDM Source Selection For DATAIN6
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* @{
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*/
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#define DATAIN6_DFSDM2_PAD (uint32_t)0x00000000
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#define DATAIN6_DFSDM2_DATAIN7 SYSCFG_MCHDLYCR_DFSDM2D6SEL
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/**
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* @}
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*/
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/** @defgroup DFSDM_CLKIN_SOURCE DFSDM1 Source Selection For CLKIN
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* @{
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*/
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#define DFSDM1_CLKIN0_TIM4OC2 (uint32_t)0x00000000
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#define DFSDM1_CLKIN2_TIM4OC2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
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#define DFSDM1_CLKIN1_TIM4OC1 (uint32_t)0x00000000
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#define DFSDM1_CLKIN3_TIM4OC1 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
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/**
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* @}
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*/
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/** @defgroup DFSDM_CLKIN_SOURCE DFSDM2 Source Selection For CLKIN
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* @{
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*/
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#define DFSDM2_CLKIN0_TIM3OC4 (uint32_t)0x00000000
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#define DFSDM2_CLKIN4_TIM3OC4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
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#define DFSDM2_CLKIN1_TIM3OC3 (uint32_t)0x00000000
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#define DFSDM2_CLKIN5_TIM3OC3 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
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#define DFSDM2_CLKIN2_TIM3OC2 (uint32_t)0x00000000
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#define DFSDM2_CLKIN6_TIM3OC2 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
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#define DFSDM2_CLKIN3_TIM3OC1 (uint32_t)0x00000000
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#define DFSDM2_CLKIN7_TIM3OC1 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
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/**
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* @}
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*/
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#endif /* STM32F413_423xx */
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/** @defgroup SYSCFG_EXTI_Port_Sources
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* @{
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*/
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#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
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#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
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#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
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#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
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#define EXTI_PortSourceGPIOE ((uint8_t)0x04)
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#define EXTI_PortSourceGPIOF ((uint8_t)0x05)
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#define EXTI_PortSourceGPIOG ((uint8_t)0x06)
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#define EXTI_PortSourceGPIOH ((uint8_t)0x07)
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#define EXTI_PortSourceGPIOI ((uint8_t)0x08)
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#define EXTI_PortSourceGPIOJ ((uint8_t)0x09)
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#define EXTI_PortSourceGPIOK ((uint8_t)0x0A)
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#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
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((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
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((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
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((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
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((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
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((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
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((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
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((PORTSOURCE) == EXTI_PortSourceGPIOH) || \
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((PORTSOURCE) == EXTI_PortSourceGPIOI) || \
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((PORTSOURCE) == EXTI_PortSourceGPIOJ) || \
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((PORTSOURCE) == EXTI_PortSourceGPIOK))
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/**
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* @}
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*/
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/** @defgroup SYSCFG_EXTI_Pin_Sources
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* @{
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*/
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#define EXTI_PinSource0 ((uint8_t)0x00)
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#define EXTI_PinSource1 ((uint8_t)0x01)
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#define EXTI_PinSource2 ((uint8_t)0x02)
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#define EXTI_PinSource3 ((uint8_t)0x03)
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#define EXTI_PinSource4 ((uint8_t)0x04)
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#define EXTI_PinSource5 ((uint8_t)0x05)
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#define EXTI_PinSource6 ((uint8_t)0x06)
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#define EXTI_PinSource7 ((uint8_t)0x07)
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#define EXTI_PinSource8 ((uint8_t)0x08)
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#define EXTI_PinSource9 ((uint8_t)0x09)
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#define EXTI_PinSource10 ((uint8_t)0x0A)
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#define EXTI_PinSource11 ((uint8_t)0x0B)
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#define EXTI_PinSource12 ((uint8_t)0x0C)
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#define EXTI_PinSource13 ((uint8_t)0x0D)
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#define EXTI_PinSource14 ((uint8_t)0x0E)
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#define EXTI_PinSource15 ((uint8_t)0x0F)
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#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
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((PINSOURCE) == EXTI_PinSource1) || \
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((PINSOURCE) == EXTI_PinSource2) || \
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((PINSOURCE) == EXTI_PinSource3) || \
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((PINSOURCE) == EXTI_PinSource4) || \
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((PINSOURCE) == EXTI_PinSource5) || \
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((PINSOURCE) == EXTI_PinSource6) || \
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((PINSOURCE) == EXTI_PinSource7) || \
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((PINSOURCE) == EXTI_PinSource8) || \
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((PINSOURCE) == EXTI_PinSource9) || \
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((PINSOURCE) == EXTI_PinSource10) || \
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((PINSOURCE) == EXTI_PinSource11) || \
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((PINSOURCE) == EXTI_PinSource12) || \
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((PINSOURCE) == EXTI_PinSource13) || \
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((PINSOURCE) == EXTI_PinSource14) || \
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((PINSOURCE) == EXTI_PinSource15))
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/**
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* @}
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*/
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/** @defgroup SYSCFG_Memory_Remap_Config
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* @{
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*/
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#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
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#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
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#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
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#define SYSCFG_MemoryRemap_SDRAM ((uint8_t)0x04)
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#if defined (STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
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#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
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#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
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#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
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#define SYSCFG_MemoryRemap_FMC ((uint8_t)0x02)
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#endif /* STM32F427_437xx || STM32F429_439xx */
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#if defined (STM32F446xx) || defined (STM32F469_479xx)
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#define SYSCFG_MemoryRemap_ExtMEM ((uint8_t)0x02)
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#endif /* STM32F446xx || STM32F469_479xx */
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#if defined (STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
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#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
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((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
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((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
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((REMAP) == SYSCFG_MemoryRemap_FSMC))
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#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
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#if defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE)
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#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
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((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
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((REMAP) == SYSCFG_MemoryRemap_SRAM))
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#endif /* STM32F401xx || STM32F410xx || STM32F411xE */
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#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
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#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
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((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
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((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
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((REMAP) == SYSCFG_MemoryRemap_SDRAM) || \
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((REMAP) == SYSCFG_MemoryRemap_FMC))
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#endif /* STM32F427_437xx || STM32F429_439xx */
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#if defined (STM32F446xx) || defined (STM32F469_479xx)
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#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
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((REMAP) == SYSCFG_MemoryRemap_ExtMEM) || \
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((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
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((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
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((REMAP) == SYSCFG_MemoryRemap_SDRAM))
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#endif /* STM32F446xx || STM32F469_479xx */
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#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
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#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVDL
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#define SYSCFG_Break_HardFault SYSCFG_CFGR2_CLL
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#define IS_SYSCFG_LOCK_CONFIG(BREAK) (((BREAK) == SYSCFG_Break_PVD) || \
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((BREAK) == SYSCFG_Break_HardFault))
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#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
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/**
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* @}
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*/
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/** @defgroup SYSCFG_ETHERNET_Media_Interface
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* @{
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*/
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#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000)
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#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001)
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#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \
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((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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void SYSCFG_DeInit(void);
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void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
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void SYSCFG_MemorySwappingBank(FunctionalState NewState);
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void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
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||
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void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface);
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||
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void SYSCFG_CompensationCellCmd(FunctionalState NewState);
|
||
|
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FlagStatus SYSCFG_GetCompensationCellStatus(void);
|
||
|
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#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
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void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
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||
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#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
|
||
|
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#if defined(STM32F413_423xx)
|
||
|
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void DFSDM_BitstreamClock_SourceSelection(uint32_t source);
|
||
|
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void DFSDM_DisableDelayClock(uint32_t MCHDLY);
|
||
|
|
void DFSDM_EnableDelayClock(uint32_t MCHDLY);
|
||
|
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void DFSDM_ClockIn_SourceSelection(uint32_t source);
|
||
|
|
void DFSDM_ClockOut_SourceSelection(uint32_t source);
|
||
|
|
void DFSDM_DataIn0_SourceSelection(uint32_t source);
|
||
|
|
void DFSDM_DataIn2_SourceSelection(uint32_t source);
|
||
|
|
void DFSDM_DataIn4_SourceSelection(uint32_t source);
|
||
|
|
void DFSDM_DataIn6_SourceSelection(uint32_t source);
|
||
|
|
void DFSDM1_BitStreamClk_Config(uint32_t source);
|
||
|
|
void DFSDM2_BitStreamClk_Config(uint32_t source);
|
||
|
|
#endif /* STM32F413_423xx */
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /*__STM32F4xx_SYSCFG_H */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|