player/Project/Src/Drive/Source/dac.c

#include "dac.h"
#include "buff.h"
#include "irq_vector.h"
#include "stm32f4xx.h"

#define DHR12RD_OFFSET ((uint32_t)0x00000020)

static DAC_UserStruct *g_dac = 0;
static int g_vol = 5;

/*
----<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>DACת<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>4<EFBFBD><EFBFBD>DAC<EFBFBD><EFBFBD>DMA
----ʹ<EFBFBD><EFBFBD>Ӳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ķ<EFBFBD>ʽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>4<EFBFBD>ж<EFBFBD><EFBFBD>Զ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DACת<EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMA<EFBFBD>Զ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/

int DAC_NormalInit(DAC_UserStruct *dac) {
  if (g_dac)
    return -1;

  DAC_NormalDeInit(dac);
  g_dac = dac;
  // <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
  TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure;
  RCC_APB1PeriphClockCmd(DAC_TIMER_RCC, ENABLE);
  TIM_TimeBaseInitStructure.TIM_Period = dac->rate; // <20>Զ<EFBFBD><D4B6><EFBFBD>װ<EFBFBD><D7B0>ֵ
  TIM_TimeBaseInitStructure.TIM_Prescaler = 0;      // <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>Ƶ
  TIM_TimeBaseInitStructure.TIM_CounterMode = TIM_CounterMode_Up; // <20><><EFBFBD>ϼ<EFBFBD><CFBC><EFBFBD>ģʽ
  TIM_TimeBaseInitStructure.TIM_ClockDivision = TIM_CKD_DIV1;
  TIM_TimeBaseInit(DAC_TIMER, &TIM_TimeBaseInitStructure); // <20><>ʼ<EFBFBD><CABC>TIM
  TIM_SelectOutputTrigger(DAC_TIMER, TIM_TRGOSource_Update);
  TIM_Cmd(DAC_TIMER, ENABLE);

  // <20><>ʼ<EFBFBD><CABC>DAC
  DAC_InitTypeDef DAC_InitStruct;
  RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);

  DAC_InitStruct.DAC_Trigger = DAC_Trigger_T4_TRGO; // <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
  DAC_InitStruct.DAC_WaveGeneration = DAC_WaveGeneration_None; // <20><>ʹ<EFBFBD>ò<EFBFBD><C3B2>η<EFBFBD><CEB7><EFBFBD>
  DAC_InitStruct.DAC_LFSRUnmask_TriangleAmplitude =
      DAC_LFSRUnmask_Bit0; // <20><><EFBFBD>Ρ<EFBFBD><CEA1><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>
  DAC_InitStruct.DAC_OutputBuffer =
      DAC_OutputBuffer_Disable; // DAC1<43><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ر<EFBFBD> BOFF1=1
  // DAC_InitStruct.DAC_OutputBuffer=DAC_OutputBuffer_Enable ;
  // //DAC1<43><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>

  DAC_Init(DAC_Channel_1, &DAC_InitStruct);
  DAC_Init(DAC_Channel_2, &DAC_InitStruct);

  DAC_SetChannel1Data(DAC_Align_12b_R, 0); // 12λ<32>Ҷ<EFBFBD><D2B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>DACֵ
  DAC_SetChannel2Data(DAC_Align_12b_R, 0); // 12λ<32>Ҷ<EFBFBD><D2B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>DACֵ

  DAC_Cmd(DAC_Channel_1, ENABLE); // ʹ<><CAB9>DACͨ<43><CDA8>1
  DAC_Cmd(DAC_Channel_2, ENABLE);
  DAC_DMACmd(DAC_Channel_1, ENABLE);
  // DAC_DMACmd (DAC_Channel_2,ENABLE);

  // <20><>ʼ<EFBFBD><CABC>GPIO
  GPIO_InitTypeDef GPIO_InitStructure;
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); // ʹ<><CAB9>GPIOAʱ<41><CAB1>
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;   // ģ<><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; // <20><><EFBFBD><EFBFBD>
  GPIO_Init(GPIOA, &GPIO_InitStructure);         // <20><>ʼ<EFBFBD><CABC>

  // DMA<4D><41>ʼ<EFBFBD><CABC>
  DMA_InitTypeDef DMA_InitStructure;
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);

  while (DMA_GetCmdStatus(DMA1_Stream5) != DISABLE) {
  } // <20>ȴ<EFBFBD>DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
  uint32_t tmp = (uint32_t)DAC_BASE;
  tmp += DHR12RD_OFFSET + DAC_Align_12b_R;

  DMA_InitStructure.DMA_Channel = DMA_Channel_7;
  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&DAC->DHR12RD;
  // DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&DAC->DHR12LD;
  DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)dac->buff1;
  DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
  DMA_InitStructure.DMA_BufferSize = dac->buff_size / 4;
  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
  DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
  DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
  DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
  DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
  DMA_Init(DMA1_Stream5, &DMA_InitStructure);
  DMA_ITConfig(DMA1_Stream5, DMA_IT_TC, ENABLE);
  // DMA_FlowControllerConfig(DMA1_Stream5, DMA_FlowCtrl_Peripheral);
  // DMA_FlowControllerConfig(DMA1_Stream5, DMA_FlowCtrl_Memory);
  DMA_DoubleBufferModeConfig(DMA1_Stream5, (uint32_t)dac->buff2,
                             DMA_Memory_0);      // ˫<><CBAB><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>
  DMA_DoubleBufferModeCmd(DMA1_Stream5, ENABLE); // ˫<><CBAB><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>

  // DMA<4D>ж<EFBFBD>
  NVIC_InitTypeDef NVIC_InitStructure;

  NVIC_InitStructure.NVIC_IRQChannel = DMA1_Stream5_IRQn;
  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  NVIC_Init(&NVIC_InitStructure);
  DMA_Cmd(DMA1_Stream5, ENABLE);

  return 0;
}

void DAC_NormalDeInit(DAC_UserStruct *dac) {
  if (dac != g_dac)
    return;

  DMA_Cmd(DMA1_Stream5, DISABLE);
  DMA_DeInit(DMA1_Stream5);
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, DISABLE);

  DAC_Cmd(DAC_Channel_1, DISABLE); // ʹ<><CAB9>DACͨ<43><CDA8>1
  DAC_Cmd(DAC_Channel_2, DISABLE);
  DAC_DeInit();
  RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, DISABLE);

  TIM_Cmd(DAC_TIMER, DISABLE);
  TIM_DeInit(DAC_TIMER);
  RCC_APB1PeriphClockCmd(DAC_TIMER_RCC, DISABLE);

  g_dac = 0;
}

// <20><>ȡDAC<41><43><EFBFBD><EFBFBD>
DAC_UserStruct *DAC_GetDacHander(void) { return g_dac; }

// <20><><EFBFBD>仺<EFBFBD><E4BBBA><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD>0<EFBFBD>ɹ<EFBFBD><C9B9><EFBFBD>-1<><31>ʧ<EFBFBD><CAA7>
int DAC_FillBuff(int16_t *buf, int size, int nch) {

  if (g_dac->buff_Invalid == 0)
    return -1;

  int16_t *p;
  if (g_dac->buff_useing == 0) {
    p = (s16 *)g_dac->buff2;
  } else {
    p = (s16 *)g_dac->buff2;
  }
  if (nch == 2) {
    for (int i = 0; i < size; i++) {
      int temp = (int16_t)buf[i];
      temp = temp * g_vol / DAC_VOL_MAX;
      p[i] = ((temp + 0x8000) >> 4);
    }
  } else // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
  {
    for (int i = 0; i < size; i++) {
      int temp = (int16_t)buf[i];
      temp = temp * g_vol / DAC_VOL_MAX;
      p[2 * i] = ((temp + 0x8000) >> 4);
      p[2 * i + 1] = p[2 * i];
    }
  }
  // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֮<EFBFBD><D6AE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>Ч
  g_dac->buff_Invalid = 0;
  return 0;
}

// DMA<4D>жϷ<D0B6><CFB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
void DMA1_Stream5_IRQHandler(void) {
  if (DMA1->HISR & DMA_FLAG_TCIF5) {
    DMA_ClearFlag(DMA1_Stream5, DMA_FLAG_TCIF5);
    if (DMA1_Stream5->CR & (1 << 19)) // Ŀǰ<C4BF><C7B0><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>buff2
    {
      g_dac->buff_useing = 1;
    } else {
      g_dac->buff_useing = 0;
    }
    g_dac->buff_Invalid = 1;
    if (g_dac->call_back)
      g_dac->call_back(g_dac);
  }
}

// <20><><EFBFBD>ݲ<EFBFBD><DDB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ö<EFBFBD>ʱ<EFBFBD><CAB1>Ƶ<EFBFBD><C6B5>
uint16_t DAC_GetRate(uint16_t rate) { return 90000000 / rate; }

static void tim_irq(void);

static data_buff g_buff = {0};
static void *g_irq_fun = 0;
// <20><>ȡ<EFBFBD><C8A1><EFBFBD>ݵĺ<DDB5><C4BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD>ɹ<EFBFBD>
static int (*g_get_value_fun)(uint16_t *value);
// <20><>fifo<66><6F>ʽ<EFBFBD><CABD>ʼ<EFBFBD><CABC>
int DAC_FifolInit(void) {

  if (g_dac)
    return -1;

  DAC_FifoDeInit();

  buff_init(&g_buff, 2048, 0, 0, 0);

  // <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
  TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure;
  RCC_APB1PeriphClockCmd(DAC_TIMER_RCC, ENABLE);
  TIM_TimeBaseInitStructure.TIM_Period = 90000000 / 11025; // <20>Զ<EFBFBD><D4B6><EFBFBD>װ<EFBFBD><D7B0>ֵ
  TIM_TimeBaseInitStructure.TIM_Prescaler = 0;             // <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>Ƶ
  TIM_TimeBaseInitStructure.TIM_CounterMode = TIM_CounterMode_Up; // <20><><EFBFBD>ϼ<EFBFBD><CFBC><EFBFBD>ģʽ
  TIM_TimeBaseInitStructure.TIM_ClockDivision = TIM_CKD_DIV1;
  TIM_TimeBaseInit(DAC_TIMER, &TIM_TimeBaseInitStructure); // <20><>ʼ<EFBFBD><CABC>TIM
  //    TIM_SelectOutputTrigger (DAC_TIMER,TIM_TRGOSource_Update);
  TIM_Cmd(DAC_TIMER, ENABLE);

  TIM_ITConfig(DAC_TIMER, TIM_IT_Update, ENABLE);

  // <20><>ʼ<EFBFBD><CABC>DAC
  DAC_InitTypeDef DAC_InitStruct;
  RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);

  DAC_InitStruct.DAC_Trigger = DAC_Trigger_None; // <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
  DAC_InitStruct.DAC_WaveGeneration = DAC_WaveGeneration_None; // <20><>ʹ<EFBFBD>ò<EFBFBD><C3B2>η<EFBFBD><CEB7><EFBFBD>
  DAC_InitStruct.DAC_LFSRUnmask_TriangleAmplitude =
      DAC_LFSRUnmask_Bit0; // <20><><EFBFBD>Ρ<EFBFBD><CEA1><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>
  DAC_InitStruct.DAC_OutputBuffer =
      DAC_OutputBuffer_Disable; // DAC1<43><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ر<EFBFBD> BOFF1=1
  // DAC_InitStruct.DAC_OutputBuffer=DAC_OutputBuffer_Enable ;
  // //DAC1<43><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>

  DAC_Init(DAC_Channel_1, &DAC_InitStruct);
  DAC_Init(DAC_Channel_2, &DAC_InitStruct);

  DAC_SetChannel1Data(DAC_Align_12b_R, 0); // 12λ<32>Ҷ<EFBFBD><D2B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>DACֵ
  DAC_SetChannel2Data(DAC_Align_12b_R, 0); // 12λ<32>Ҷ<EFBFBD><D2B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>DACֵ

  DAC_Cmd(DAC_Channel_1, ENABLE); // ʹ<><CAB9>DACͨ<43><CDA8>1
  DAC_Cmd(DAC_Channel_2, ENABLE);

  // <20><>ʼ<EFBFBD><CABC>GPIO
  GPIO_InitTypeDef GPIO_InitStructure;
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); // ʹ<><CAB9>GPIOAʱ<41><CAB1>
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;   // ģ<><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; // <20><><EFBFBD><EFBFBD>
  GPIO_Init(GPIOA, &GPIO_InitStructure);         // <20><>ʼ<EFBFBD><CABC>

  // <20><>ʱ<EFBFBD><CAB1><EFBFBD>ж<EFBFBD>
  NVIC_InitTypeDef NVIC_InitStructure;

  NVIC_InitStructure.NVIC_IRQChannel = TIM4_IRQn;
  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3;
  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  NVIC_Init(&NVIC_InitStructure);

  g_irq_fun = irq_vector_set_irq(TIM4_IRQn, tim_irq);

  return 0;
}

void DAC_FifoDeInit(void) {

  DAC_Cmd(DAC_Channel_1, DISABLE); // ʹ<><CAB9>DACͨ<43><CDA8>1
  DAC_Cmd(DAC_Channel_2, DISABLE);
  DAC_DeInit();
  RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, DISABLE);

  TIM_ITConfig(DAC_TIMER, TIM_IT_Update, DISABLE);
  TIM_Cmd(DAC_TIMER, DISABLE);
  TIM_DeInit(DAC_TIMER);
  RCC_APB1PeriphClockCmd(DAC_TIMER_RCC, DISABLE);

  buff_deinit(&g_buff);

  irq_vector_set_irq(TIM4_IRQn, g_irq_fun);
  g_get_value_fun = 0;
}

// <20><><EFBFBD>û<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD>ݺ<EFBFBD><DDBA><EFBFBD>
int DAC_SetSetValuwFun(int (*fun)(uint16_t *)) {
  g_get_value_fun = fun;
  return 0;
}

// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD>0<EFBFBD>ɹ<EFBFBD>
int DAC_SaveValue(uint16_t value) {
  return buff_save_bytes(&g_buff, (uint8_t *)&value, 2);
}

static void tim_irq(void) {
  uint8_t vs[2];
  uint32_t v = 0;
  if (TIM_GetITStatus(DAC_TIMER, TIM_IT_Update) == SET) // <20><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
  {
    TIM_ClearITPendingBit(DAC_TIMER, TIM_IT_Update); // <20><><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־λ
    if (g_get_value_fun == 0) {
      if (buff_read_bytes(&g_buff, vs, 2) == 0) {
        v = ((uint16_t)vs[1] << 8) | vs[0];
        v |= v << 16;
        DAC->DHR12RD = v;
      }
    } else {
      uint16_t v16 = 0;
      if (g_get_value_fun(&v16) == 0) {
        v = (v16 << 16) | v16;
        DAC->DHR12RD = v;
      }
    }
  }
}