2025-06-27 00:32:57 +08:00
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/*
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* File : ls1c.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2011-08-08 lgnq first version
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* 2015-07-06 chinesebear modified for loongson 1c
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*/
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#ifndef __LS1C_H__
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#define __LS1C_H__
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#include "../common/mipsregs.h"
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#define LS1C_ACPI_IRQ 0
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#define LS1C_HPET_IRQ 1
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2025-07-05 19:47:28 +08:00
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//#define LS1C_UART0_IRQ 3 // linux<75><78><EFBFBD><EFBFBD>3<EFBFBD><33>v1.4<EFBFBD>汾<EFBFBD><EFBFBD>1c<EFBFBD>ֲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Σ<EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><EFBFBD>
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#define LS1C_UART1_IRQ 4
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#define LS1C_UART2_IRQ 5
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#define LS1C_CAN0_IRQ 6
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#define LS1C_CAN1_IRQ 7
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#define LS1C_SPI0_IRQ 8
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#define LS1C_SPI1_IRQ 9
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#define LS1C_AC97_IRQ 10
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#define LS1C_MS_IRQ 11
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#define LS1C_KB_IRQ 12
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#define LS1C_DMA0_IRQ 13
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#define LS1C_DMA1_IRQ 14
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#define LS1C_DMA2_IRQ 15
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#define LS1C_NAND_IRQ 16
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#define LS1C_PWM0_IRQ 17
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#define LS1C_PWM1_IRQ 18
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#define LS1C_PWM2_IRQ 19
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#define LS1C_PWM3_IRQ 20
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#define LS1C_RTC_INT0_IRQ 21
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#define LS1C_RTC_INT1_IRQ 22
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#define LS1C_RTC_INT2_IRQ 23
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#define LS1C_UART3_IRQ 29
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#define LS1C_ADC_IRQ 30
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#define LS1C_SDIO_IRQ 31
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#define LS1C_EHCI_IRQ (32+0)
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#define LS1C_OHCI_IRQ (32+1)
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#define LS1C_OTG_IRQ (32+2)
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#define LS1C_MAC_IRQ (32+3)
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#define LS1C_CAM_IRQ (32+4)
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#define LS1C_UART4_IRQ (32+5)
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#define LS1C_UART5_IRQ (32+6)
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#define LS1C_UART6_IRQ (32+7)
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#define LS1C_UART7_IRQ (32+8)
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#define LS1C_UART8_IRQ (32+9)
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#define LS1C_UART9_IRQ (32+13)
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#define LS1C_UART10_IRQ (32+14)
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#define LS1C_UART11_IRQ (32+15)
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#define LS1C_I2C2_IRQ (32+17)
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#define LS1C_I2C1_IRQ (32+18)
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#define LS1C_I2C0_IRQ (32+19)
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#define LS1C_GPIO_IRQ 64
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#define LS1C_GPIO_FIRST_IRQ 64
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#define LS1C_GPIO_IRQ_COUNT 96
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#define LS1C_GPIO_LAST_IRQ (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1)
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#define LS1C_LAST_IRQ 159
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#define LS1C_INTREG_BASE 0xbfd01040
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2025-07-05 19:47:28 +08:00
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// <20><>о1c<31><63><EFBFBD>жϷ<D0B6>Ϊ<EFBFBD><CEAA><EFBFBD>飬ÿ<E9A3AC><C3BF>32<33><32>
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#define LS1C_NR_IRQS (32*5)
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2025-07-05 19:47:28 +08:00
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// GPIO<49><4F><EFBFBD>ź<EFBFBD><C5BA>жϺ<D0B6>֮<EFBFBD><D6AE><EFBFBD>Ļ<EFBFBD><C4BB><EFBFBD>ת<EFBFBD><D7AA>
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#define LS1C_GPIO_TO_IRQ(GPIOn) (LS1C_GPIO_FIRST_IRQ + (GPIOn))
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#define LS1C_IRQ_TO_GPIO(IRQn) ((IRQn) - LS1C_GPIO_FIRST_IRQ)
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struct ls1c_intc_regs
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{
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volatile unsigned int int_isr;
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volatile unsigned int int_en;
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volatile unsigned int int_set;
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volatile unsigned int int_clr; /* offset 0x10*/
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volatile unsigned int int_pol;
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volatile unsigned int int_edge; /* offset 0 */
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};
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struct ls1c_cop_global_regs
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{
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volatile unsigned int control;
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volatile unsigned int rd_inten;
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volatile unsigned int wr_inten;
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volatile unsigned int rd_intisr; /* offset 0x10*/
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volatile unsigned int wr_intisr;
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unsigned int unused[11];
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} ;
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struct ls1c_cop_channel_regs
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{
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volatile unsigned int rd_control;
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volatile unsigned int rd_src;
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volatile unsigned int rd_cnt;
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volatile unsigned int rd_status; /* offset 0x10*/
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volatile unsigned int wr_control;
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volatile unsigned int wr_src;
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volatile unsigned int wr_cnt;
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volatile unsigned int wr_status; /* offset 0x10*/
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} ;
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struct ls1c_cop_regs
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{
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struct ls1c_cop_global_regs global;
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struct ls1c_cop_channel_regs chan[8][2];
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} ;
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#define __REG8(addr) *((volatile unsigned char *)(addr))
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#define __REG16(addr) *((volatile unsigned short *)(addr))
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#define __REG32(addr) *((volatile unsigned int *)(addr))
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#define GMAC0_BASE 0xBFE10000
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#define GMAC0_DMA_BASE 0xBFE11000
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#define GMAC1_BASE 0xBFE20000
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#define GMAC1_DMA_BASE 0xBFE21000
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#define I2C0_BASE 0xBFE58000
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#define PWM0_BASE 0xBFE5C000
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#define PWM1_BASE 0xBFE5C010
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#define PWM2_BASE 0xBFE5C020
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#define PWM3_BASE 0xBFE5C030
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#define WDT_BASE 0xBFE5C060
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#define RTC_BASE 0xBFE64000
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#define I2C1_BASE 0xBFE68000
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#define I2C2_BASE 0xBFE70000
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#define AC97_BASE 0xBFE74000
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#define NAND_BASE 0xBFE78000
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#define SPI_BASE 0xBFE80000
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#define CAN1_BASE 0xBF004300
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#define CAN0_BASE 0xBF004400
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/* Watch Dog registers */
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#define WDT_EN __REG32(WDT_BASE + 0x00)
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#define WDT_SET __REG32(WDT_BASE + 0x04)
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#define WDT_TIMER __REG32(WDT_BASE + 0x08)
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#define PLL_FREQ __REG32(0xbfe78030)
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#define PLL_DIV_PARAM __REG32(0xbfe78034)
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#endif
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