2025-06-27 00:32:57 +08:00
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#ifndef __OPENLOONGSON_SDRAM_CFG_H
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#define __OPENLOONGSON_SDRAM_CFG_H
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//#define SD_FREQ (6 * PLL_M) / (2 * SDRAM_PARAM_DIV_NUM)
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#define SD_FREQ (((APB_CLK / 4) * (PLL_MULT / CPU_DIV)) / SDRAM_PARAM_DIV_NUM)
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2025-07-05 19:47:28 +08:00
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/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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2025-06-27 00:32:57 +08:00
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#define ROW_1K 0x7
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#define ROW_2K 0x0
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#define ROW_4K 0x1
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#define ROW_8K 0x2
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#define ROW_16K 0x3
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2025-07-05 19:47:28 +08:00
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/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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2025-06-27 00:32:57 +08:00
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#define COL_256 0x7
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#define COL_512 0x0
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#define COL_1K 0x1
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#define COL_2K 0x2
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#define COL_4K 0x3
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2025-07-05 19:47:28 +08:00
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/* <20><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB> */
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2025-06-27 00:32:57 +08:00
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#define WIDTH_8 0x0
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#define WIDTH_16 0x1
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#define WIDTH_32 0x2
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#define TRCD 3
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#define TCL 3
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#define TRP 3
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#define TRFC 8
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#define TRAS 6
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#define TREF 0x818
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#define TWR 2
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#define DEF_SEL 0x1
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#define DEF_SEL_N 0x0
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#define HANG_UP 0x1
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#define HANG_UP_N 0x0
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#define CFG_VALID 0x1
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#if 0
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2025-07-05 19:47:28 +08:00
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// <20>ײ˰<D7B2>8MB
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2025-06-27 00:32:57 +08:00
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/*
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2025-07-05 19:47:28 +08:00
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<EFBFBD><EFBFBD><EFBFBD>ͺ<EFBFBD>ΪIS42S16400<EFBFBD><EFBFBD>SDRAMΪ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><EFBFBD>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>8MB
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λ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>16λ
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<EFBFBD>п<EFBFBD><EFBFBD><EFBFBD>8λ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><EFBFBD>8<EFBFBD>η<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>256
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<EFBFBD>п<EFBFBD><EFBFBD><EFBFBD>12λ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><EFBFBD>12<EFBFBD>η<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>4K
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<EFBFBD><EFBFBD><EFBFBD>ԣ<EFBFBD>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD>=WIDTH_16
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>=COL_256
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>=ROW_4K
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<EFBFBD>ٽ<EFBFBD><EFBFBD>Ϻ<EFBFBD>SD_PARA0<EFBFBD><EFBFBD>оƬ<EFBFBD>ֲ<EFBFBD><EFBFBD>мĴ<EFBFBD><EFBFBD><EFBFBD>SD_CONFIG<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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<EFBFBD>滻<EFBFBD><EFBFBD>SD_PARA0<EFBFBD>е<EFBFBD><EFBFBD>п<EFBFBD><EFBFBD><EFBFBD><EFBFBD>п<EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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*/
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#define SDRAM_WIDTH (WIDTH_16)
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#define SDRAM_COL (COL_256)
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#define SDRAM_ROW (ROW_4K)
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#else
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2025-07-05 19:47:28 +08:00
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// <20><><EFBFBD><EFBFBD>32MByte
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2025-06-27 00:32:57 +08:00
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#define SDRAM_WIDTH (WIDTH_16)
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#define SDRAM_COL (COL_512)
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#define SDRAM_ROW (ROW_8K)
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#endif
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#define SD_PARA0 (0x7f<<25 | \
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(TRAS << 21) | \
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(TRFC << 17) | (TRP << 14) | (TCL << 11) | \
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(TRCD << 8) | (SDRAM_WIDTH << 6) | (SDRAM_COL << 3) | \
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SDRAM_ROW)
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#define SD_PARA1 ((HANG_UP_N << 8) | (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
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#define SD_PARA1_EN ((CFG_VALID << 9) | (HANG_UP_N << 8) | \
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(DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
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#endif
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