2025-06-27 00:32:57 +08:00
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#ifndef SWD_H__
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#define SWD_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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2025-07-05 19:47:28 +08:00
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//<2F><><EFBFBD><EFBFBD><EFBFBD>ֶ<EFBFBD><D6B6><EFBFBD>
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2025-06-27 00:32:57 +08:00
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#define SWD_REG_DP 0x00
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#define SWD_REG_AP 0x02
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#define SWD_READ 0x04
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#define SWD_WRITE 0x00
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2025-07-05 19:47:28 +08:00
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//DP<44>Ĵ<EFBFBD><C4B4><EFBFBD>
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#define SWD_REG_IDCODE (0x00<<1)//ֻ<><D6BB>
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#define SWD_REG_ABORT (0x00<<1)//ֻд
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#define SWD_REG_CTRL_STAT (0x04<<1)//<2F><>д
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#define SWD_REG_RESEND (0x08<<1)//ֻ<><D6BB>
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#define SWD_REG_SELECT (0x08<<1)//ֻд
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#define SWD_REG_RDBUFF (0x0c<<1)//ֻ<><D6BB>
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2025-06-27 00:32:57 +08:00
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2025-07-05 19:47:28 +08:00
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//AP<41>Ĵ<EFBFBD><C4B4><EFBFBD>
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2025-06-27 00:32:57 +08:00
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#define SWD_REG_CSW (0x00<<1)
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#define SWD_REG_TAR (0x04<<1)
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#define SWD_REG_BASE (0x08<<1)
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#define SWD_REG_DRW (0x0c<<1)
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#define SWD_REG_IDR (0x0c<<1)
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2025-07-05 19:47:28 +08:00
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//ͨ<>Ŵ<EFBFBD><C5B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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#define SWD_ERR_OK (0x01)
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#define SWD_ERR_WAIT (0x02)
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#define SWD_ERR_FAIL (0x04)
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#define SWD_ERR_OTHER (0x07)
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// Cortex M3 Debug Registers (AHB addresses)
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#define CM3_DDFSR 0xE000ED30 // Debug Fault StatusRegister
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#define CM3_DHCSR 0xE000EDF0 // Debug Halting Control and Status Register
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#define CM3_DCRSR 0xE000EDF4 // Debug Core Register Selector Register
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#define CM3_DCRDR 0xE000EDF8 // Debug Core Register Data Register
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#define CM3_DEMCR 0xE000EDFC // Debug Exception and Monitor Control Register
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#define CM3_AIRCR 0xE000ED0C // The Application Interrupt and Reset Control Register
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2025-07-05 19:47:28 +08:00
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//<2F><>д<EFBFBD>ں˼Ĵ<CBBC><C4B4><EFBFBD>
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2025-06-27 00:32:57 +08:00
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#define CM3_REG_READ 0x00000000
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#define CM3_REG_WRITE 0x00010000
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2025-07-05 19:47:28 +08:00
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//<2F>ں˼Ĵ<CBBC><C4B4><EFBFBD>ѡַ
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2025-06-27 00:32:57 +08:00
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#define CM3_REG_R0 0x0000
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#define CM3_REG_R1 0x0001
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#define CM3_REG_R2 0x0002
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#define CM3_REG_R3 0x0003
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#define CM3_REG_R4 0x0004
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#define CM3_REG_R5 0x0005
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#define CM3_REG_R6 0x0006
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#define CM3_REG_R7 0x0007
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#define CM3_REG_R8 0x0008
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#define CM3_REG_R9 0x0009
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#define CM3_REG_R10 0x000a
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#define CM3_REG_R11 0x000b
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#define CM3_REG_R12 0x000c
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#define CM3_REG_R13 0x000d
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#define CM3_REG_SP 0x000d
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#define CM3_REG_R14 0x000e
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#define CM3_REG_LR 0x000e
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#define CM3_REG_R15 0x000f
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#define CM3_REG_PC 0x000f
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#define CM3_REG_xPSR 0x0010
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#define CM3_REG_MSP 0x0011
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#define CM3_REG_PSP 0x0012
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2025-07-05 19:47:28 +08:00
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//<2F><>ʼ<EFBFBD><CABC>
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2025-06-27 00:32:57 +08:00
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void SWD_Init (void);
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2025-07-05 19:47:28 +08:00
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//<2F><><EFBFBD>߸<EFBFBD>λ
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2025-06-27 00:32:57 +08:00
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void SWD_LineReset (void);
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2025-07-05 19:47:28 +08:00
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//<2F><>ȡ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
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2025-06-27 00:32:57 +08:00
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u32 SWD_ReadReg (u8 cmd,u8 *err);
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2025-07-05 19:47:28 +08:00
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//д<><D0B4><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
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2025-06-27 00:32:57 +08:00
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void SWD_WriteReg (u8 cmd,u8 *err,u32 data);
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2025-07-05 19:47:28 +08:00
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//<2F><><EFBFBD>ڴ<EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C>ɹ<EFBFBD><C9B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸id
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2025-06-27 00:32:57 +08:00
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u32 SWD_WriteSram (u32 addr,u32 *data,u32 len);
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2025-07-05 19:47:28 +08:00
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//<2F><><EFBFBD>ڴ<EFBFBD><DAB4><EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>,<2C>ɹ<EFBFBD><C9B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸id
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2025-06-27 00:32:57 +08:00
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u32 SWD_ReadSram (u32 addr,u32 *data,u32 len);
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2025-07-05 19:47:28 +08:00
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//<2F><>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ں<EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>0<EFBFBD><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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u32 SWD_Cm3Halt (u8 value);
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2025-07-05 19:47:28 +08:00
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//<2F><><EFBFBD>ں˼Ĵ<CBBC><C4B4><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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u32 SWD_WriteCm3Reg (u16 reg_select,u32 data);
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#ifdef __cplusplus
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}
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#endif
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#endif
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