2025-06-27 00:32:57 +08:00
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#include "dac.h"
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#include "buff.h"
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#include "irq_vector.h"
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#define DHR12RD_OFFSET ((uint32_t)0x00000020)
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static DAC_UserStruct *g_dac=0;
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static int g_vol=5;
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/*
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2025-07-05 19:47:28 +08:00
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----<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>DACת<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>4<EFBFBD><EFBFBD>DAC<EFBFBD><EFBFBD>DMA
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----ʹ<EFBFBD><EFBFBD>Ӳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ķ<EFBFBD>ʽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>4<EFBFBD>ж<EFBFBD><EFBFBD>Զ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DACת<EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMA<EFBFBD>Զ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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*/
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int DAC_NormalInit (DAC_UserStruct *dac)
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{
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if (g_dac) return -1;
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DAC_NormalDeInit (dac);
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g_dac=dac;
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2025-07-05 19:47:28 +08:00
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//<2F><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
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2025-06-27 00:32:57 +08:00
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TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure;
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RCC_APB1PeriphClockCmd(DAC_TIMER_RCC,ENABLE);
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2025-07-05 19:47:28 +08:00
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TIM_TimeBaseInitStructure.TIM_Period = dac->rate; //<2F>Զ<EFBFBD><D4B6><EFBFBD>װ<EFBFBD><D7B0>ֵ
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TIM_TimeBaseInitStructure.TIM_Prescaler=0; //<2F><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>Ƶ
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TIM_TimeBaseInitStructure.TIM_CounterMode=TIM_CounterMode_Up; //<2F><><EFBFBD>ϼ<EFBFBD><CFBC><EFBFBD>ģʽ
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2025-06-27 00:32:57 +08:00
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TIM_TimeBaseInitStructure.TIM_ClockDivision=TIM_CKD_DIV1;
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2025-07-05 19:47:28 +08:00
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TIM_TimeBaseInit(DAC_TIMER,&TIM_TimeBaseInitStructure);//<2F><>ʼ<EFBFBD><CABC>TIM
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2025-06-27 00:32:57 +08:00
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TIM_SelectOutputTrigger (DAC_TIMER,TIM_TRGOSource_Update);
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TIM_Cmd(DAC_TIMER,ENABLE);
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2025-07-05 19:47:28 +08:00
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//<2F><>ʼ<EFBFBD><CABC>DAC
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2025-06-27 00:32:57 +08:00
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DAC_InitTypeDef DAC_InitStruct;
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC,ENABLE);
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2025-07-05 19:47:28 +08:00
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DAC_InitStruct.DAC_Trigger=DAC_Trigger_T4_TRGO; //<2F><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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DAC_InitStruct.DAC_WaveGeneration=DAC_WaveGeneration_None;//<2F><>ʹ<EFBFBD>ò<EFBFBD><C3B2>η<EFBFBD><CEB7><EFBFBD>
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DAC_InitStruct.DAC_LFSRUnmask_TriangleAmplitude=DAC_LFSRUnmask_Bit0;//<2F><><EFBFBD>Ρ<EFBFBD><CEA1><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>
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DAC_InitStruct.DAC_OutputBuffer=DAC_OutputBuffer_Disable ; //DAC1<43><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ر<EFBFBD> BOFF1=1
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//DAC_InitStruct.DAC_OutputBuffer=DAC_OutputBuffer_Enable ; //DAC1<43><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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DAC_Init (DAC_Channel_1,&DAC_InitStruct);
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DAC_Init (DAC_Channel_2,&DAC_InitStruct);
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2025-07-05 19:47:28 +08:00
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DAC_SetChannel1Data(DAC_Align_12b_R, 0); //12λ<32>Ҷ<EFBFBD><D2B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>DACֵ
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DAC_SetChannel2Data(DAC_Align_12b_R, 0); //12λ<32>Ҷ<EFBFBD><D2B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>DACֵ
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2025-06-27 00:32:57 +08:00
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2025-07-05 19:47:28 +08:00
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DAC_Cmd(DAC_Channel_1, ENABLE); //ʹ<><CAB9>DACͨ<43><CDA8>1
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2025-06-27 00:32:57 +08:00
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DAC_Cmd(DAC_Channel_2, ENABLE);
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DAC_DMACmd (DAC_Channel_1,ENABLE);
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//DAC_DMACmd (DAC_Channel_2,ENABLE);
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2025-07-05 19:47:28 +08:00
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//<2F><>ʼ<EFBFBD><CABC>GPIO
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2025-06-27 00:32:57 +08:00
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GPIO_InitTypeDef GPIO_InitStructure;
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2025-07-05 19:47:28 +08:00
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);//ʹ<><CAB9>GPIOAʱ<41><CAB1>
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2025-06-27 00:32:57 +08:00
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4|GPIO_Pin_5;
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2025-07-05 19:47:28 +08:00
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//ģ<><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;//<2F><><EFBFBD><EFBFBD>
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GPIO_Init(GPIOA, &GPIO_InitStructure);//<2F><>ʼ<EFBFBD><CABC>
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2025-06-27 00:32:57 +08:00
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2025-07-05 19:47:28 +08:00
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//DMA<4D><41>ʼ<EFBFBD><CABC>
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2025-06-27 00:32:57 +08:00
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DMA_InitTypeDef DMA_InitStructure;
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RCC_AHB1PeriphClockCmd (RCC_AHB1Periph_DMA1,ENABLE);
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2025-07-05 19:47:28 +08:00
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while (DMA_GetCmdStatus(DMA1_Stream5) != DISABLE){}//<2F>ȴ<EFBFBD>DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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u32 tmp = (uint32_t)DAC_BASE;
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tmp += DHR12RD_OFFSET + DAC_Align_12b_R;
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DMA_InitStructure.DMA_Channel = DMA_Channel_7;
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DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&DAC->DHR12RD;
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//DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&DAC->DHR12LD;
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DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)dac->buff1;
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DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
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DMA_InitStructure.DMA_BufferSize = dac->buff_size/4;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_Priority = DMA_Priority_High;
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DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
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DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
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DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
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DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
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DMA_Init(DMA1_Stream5, &DMA_InitStructure);
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DMA_ITConfig(DMA1_Stream5, DMA_IT_TC, ENABLE);
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//DMA_FlowControllerConfig(DMA1_Stream5, DMA_FlowCtrl_Peripheral);
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//DMA_FlowControllerConfig(DMA1_Stream5, DMA_FlowCtrl_Memory);
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2025-07-05 19:47:28 +08:00
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DMA_DoubleBufferModeConfig(DMA1_Stream5,(u32)dac->buff2,DMA_Memory_0);//˫<><CBAB><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>
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DMA_DoubleBufferModeCmd(DMA1_Stream5,ENABLE);//˫<><CBAB><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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2025-07-05 19:47:28 +08:00
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//DMA<4D>ж<EFBFBD>
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2025-06-27 00:32:57 +08:00
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NVIC_InitTypeDef NVIC_InitStructure;
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NVIC_InitStructure.NVIC_IRQChannel = DMA1_Stream5_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init (&NVIC_InitStructure);
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DMA_Cmd(DMA1_Stream5, ENABLE);
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return 0;
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}
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void DAC_NormalDeInit (DAC_UserStruct *dac)
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{
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if (dac!=g_dac) return;
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DMA_Cmd(DMA1_Stream5, DISABLE);
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DMA_DeInit(DMA1_Stream5);
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RCC_AHB1PeriphClockCmd (RCC_AHB1Periph_DMA1,DISABLE);
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2025-07-05 19:47:28 +08:00
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DAC_Cmd(DAC_Channel_1, DISABLE); //ʹ<><CAB9>DACͨ<43><CDA8>1
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2025-06-27 00:32:57 +08:00
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DAC_Cmd(DAC_Channel_2, DISABLE);
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DAC_DeInit ();
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC,DISABLE);
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TIM_Cmd(DAC_TIMER,DISABLE);
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TIM_DeInit (DAC_TIMER);
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RCC_APB1PeriphClockCmd(DAC_TIMER_RCC,DISABLE);
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g_dac=0;
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}
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2025-07-05 19:47:28 +08:00
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//<2F><>ȡDAC<41><43><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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DAC_UserStruct *DAC_GetDacHander (void)
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{
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return g_dac;
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}
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2025-07-05 19:47:28 +08:00
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// <20><><EFBFBD>仺<EFBFBD><E4BBBA><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD>0<EFBFBD>ɹ<EFBFBD><C9B9><EFBFBD>-1<><31>ʧ<EFBFBD><CAA7>
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2025-06-27 00:32:57 +08:00
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int DAC_FillBuff(int16_t *buf,int size,int nch)
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{
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if(g_dac->buff_Invalid==0) return -1;
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int16_t *p;
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if(g_dac->buff_useing==0)
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{
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p=(s16*)g_dac->buff2;
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}else
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{
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p=(s16*)g_dac->buff2;
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}
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if(nch==2)
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{
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for(int i=0;i<size;i++)
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{
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int temp=(int16_t)buf[i];
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temp=temp*g_vol/DAC_VOL_MAX;
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p[i]=((temp+0x8000)>>4);
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}
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}
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2025-07-05 19:47:28 +08:00
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else //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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{
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for(int i=0;i<size;i++)
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{
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int temp=(int16_t)buf[i];
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temp=temp*g_vol/DAC_VOL_MAX;
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p[2*i]=((temp+0x8000)>>4);
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p[2*i+1]=p[2*i];
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}
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}
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2025-07-05 19:47:28 +08:00
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֮<EFBFBD><D6AE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>Ч
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2025-06-27 00:32:57 +08:00
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g_dac->buff_Invalid=0;
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return 0;
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}
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2025-07-05 19:47:28 +08:00
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//DMA<4D>жϷ<D0B6><CFB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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void DMA1_Stream5_IRQHandler (void)
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{
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if (DMA1->HISR&DMA_FLAG_TCIF5)
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{
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DMA_ClearFlag(DMA1_Stream5, DMA_FLAG_TCIF5);
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2025-07-05 19:47:28 +08:00
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if (DMA1_Stream5->CR&(1<<19))//Ŀǰ<C4BF><C7B0><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>buff2
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2025-06-27 00:32:57 +08:00
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{
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g_dac->buff_useing=1;
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}
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else
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{
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g_dac->buff_useing=0;
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}
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g_dac->buff_Invalid=1;
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if (g_dac->call_back) g_dac->call_back(g_dac);
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}
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}
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2025-07-05 19:47:28 +08:00
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//<2F><><EFBFBD>ݲ<EFBFBD><DDB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ö<EFBFBD>ʱ<EFBFBD><CAB1>Ƶ<EFBFBD><C6B5>
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2025-06-27 00:32:57 +08:00
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u16 DAC_GetRate (u16 rate)
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{
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return 90000000/rate;
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}
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static void tim_irq(void);
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static data_buff g_buff={0};
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static void *g_irq_fun=0;
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2025-07-05 19:47:28 +08:00
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// <20><>ȡ<EFBFBD><C8A1><EFBFBD>ݵĺ<DDB5><C4BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD>ɹ<EFBFBD>
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2025-06-27 00:32:57 +08:00
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static int (*g_get_value_fun)(uint16_t *value);
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2025-07-05 19:47:28 +08:00
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// <20><>fifo<66><6F>ʽ<EFBFBD><CABD>ʼ<EFBFBD><CABC>
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2025-06-27 00:32:57 +08:00
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int DAC_FifolInit (void)
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{
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if (g_dac) return -1;
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DAC_FifoDeInit();
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buff_init(&g_buff,2048,0,0,0);
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2025-07-05 19:47:28 +08:00
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//<2F><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
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2025-06-27 00:32:57 +08:00
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TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure;
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RCC_APB1PeriphClockCmd(DAC_TIMER_RCC,ENABLE);
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2025-07-05 19:47:28 +08:00
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TIM_TimeBaseInitStructure.TIM_Period = 90000000/11025; //<2F>Զ<EFBFBD><D4B6><EFBFBD>װ<EFBFBD><D7B0>ֵ
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TIM_TimeBaseInitStructure.TIM_Prescaler=0; //<2F><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>Ƶ
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TIM_TimeBaseInitStructure.TIM_CounterMode=TIM_CounterMode_Up; //<2F><><EFBFBD>ϼ<EFBFBD><CFBC><EFBFBD>ģʽ
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2025-06-27 00:32:57 +08:00
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TIM_TimeBaseInitStructure.TIM_ClockDivision=TIM_CKD_DIV1;
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2025-07-05 19:47:28 +08:00
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TIM_TimeBaseInit(DAC_TIMER,&TIM_TimeBaseInitStructure);//<2F><>ʼ<EFBFBD><CABC>TIM
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2025-06-27 00:32:57 +08:00
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// TIM_SelectOutputTrigger (DAC_TIMER,TIM_TRGOSource_Update);
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TIM_Cmd(DAC_TIMER,ENABLE);
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TIM_ITConfig(DAC_TIMER,TIM_IT_Update,ENABLE);
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2025-07-05 19:47:28 +08:00
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//<2F><>ʼ<EFBFBD><CABC>DAC
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2025-06-27 00:32:57 +08:00
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DAC_InitTypeDef DAC_InitStruct;
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC,ENABLE);
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2025-07-05 19:47:28 +08:00
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DAC_InitStruct.DAC_Trigger=DAC_Trigger_None; //<2F><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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DAC_InitStruct.DAC_WaveGeneration=DAC_WaveGeneration_None;//<2F><>ʹ<EFBFBD>ò<EFBFBD><C3B2>η<EFBFBD><CEB7><EFBFBD>
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DAC_InitStruct.DAC_LFSRUnmask_TriangleAmplitude=DAC_LFSRUnmask_Bit0;//<2F><><EFBFBD>Ρ<EFBFBD><CEA1><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>
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DAC_InitStruct.DAC_OutputBuffer=DAC_OutputBuffer_Disable ; //DAC1<43><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ر<EFBFBD> BOFF1=1
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//DAC_InitStruct.DAC_OutputBuffer=DAC_OutputBuffer_Enable ; //DAC1<43><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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DAC_Init (DAC_Channel_1,&DAC_InitStruct);
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DAC_Init (DAC_Channel_2,&DAC_InitStruct);
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2025-07-05 19:47:28 +08:00
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DAC_SetChannel1Data(DAC_Align_12b_R, 0); //12λ<32>Ҷ<EFBFBD><D2B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>DACֵ
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DAC_SetChannel2Data(DAC_Align_12b_R, 0); //12λ<32>Ҷ<EFBFBD><D2B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>DACֵ
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2025-06-27 00:32:57 +08:00
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2025-07-05 19:47:28 +08:00
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DAC_Cmd(DAC_Channel_1, ENABLE); //ʹ<><CAB9>DACͨ<43><CDA8>1
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2025-06-27 00:32:57 +08:00
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DAC_Cmd(DAC_Channel_2, ENABLE);
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2025-07-05 19:47:28 +08:00
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//<2F><>ʼ<EFBFBD><CABC>GPIO
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2025-06-27 00:32:57 +08:00
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GPIO_InitTypeDef GPIO_InitStructure;
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2025-07-05 19:47:28 +08:00
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);//ʹ<><CAB9>GPIOAʱ<41><CAB1>
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2025-06-27 00:32:57 +08:00
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4|GPIO_Pin_5;
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2025-07-05 19:47:28 +08:00
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//ģ<><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;//<2F><><EFBFBD><EFBFBD>
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GPIO_Init(GPIOA, &GPIO_InitStructure);//<2F><>ʼ<EFBFBD><CABC>
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2025-06-27 00:32:57 +08:00
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2025-07-05 19:47:28 +08:00
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//<2F><>ʱ<EFBFBD><CAB1><EFBFBD>ж<EFBFBD>
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2025-06-27 00:32:57 +08:00
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NVIC_InitTypeDef NVIC_InitStructure;
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NVIC_InitStructure.NVIC_IRQChannel = TIM4_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init (&NVIC_InitStructure);
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g_irq_fun=irq_vector_set_irq(TIM4_IRQn,tim_irq);
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return 0;
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}
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void DAC_FifoDeInit (void)
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{
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2025-07-05 19:47:28 +08:00
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DAC_Cmd(DAC_Channel_1, DISABLE); //ʹ<><CAB9>DACͨ<43><CDA8>1
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2025-06-27 00:32:57 +08:00
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DAC_Cmd(DAC_Channel_2, DISABLE);
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DAC_DeInit ();
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC,DISABLE);
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TIM_ITConfig(DAC_TIMER,TIM_IT_Update,DISABLE);
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TIM_Cmd(DAC_TIMER,DISABLE);
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TIM_DeInit (DAC_TIMER);
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RCC_APB1PeriphClockCmd(DAC_TIMER_RCC,DISABLE);
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buff_deinit(&g_buff);
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irq_vector_set_irq(TIM4_IRQn,g_irq_fun);
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g_get_value_fun=0;
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}
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2025-07-05 19:47:28 +08:00
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// <20><><EFBFBD>û<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD>ݺ<EFBFBD><DDBA><EFBFBD>
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2025-06-27 00:32:57 +08:00
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int DAC_SetSetValuwFun(int (*fun)(uint16_t *))
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{
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g_get_value_fun=fun;
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return 0;
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}
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2025-07-05 19:47:28 +08:00
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD>0<EFBFBD>ɹ<EFBFBD>
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2025-06-27 00:32:57 +08:00
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int DAC_SaveValue(uint16_t value)
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{
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return buff_save_bytes(&g_buff,(uint8_t *)&value,2);
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}
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static void tim_irq(void)
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{
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uint8_t vs[2];
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uint32_t v=0;
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2025-07-05 19:47:28 +08:00
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if(TIM_GetITStatus(DAC_TIMER,TIM_IT_Update)==SET) //<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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2025-06-27 00:32:57 +08:00
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{
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2025-07-05 19:47:28 +08:00
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TIM_ClearITPendingBit(DAC_TIMER,TIM_IT_Update); //<2F><><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־λ
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2025-06-27 00:32:57 +08:00
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if(g_get_value_fun==0)
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{
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if(buff_read_bytes(&g_buff,vs,2)==0)
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{
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v=((uint16_t)vs[1]<<8)|vs[0];
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v|=v<<16;
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DAC->DHR12RD=v;
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}
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}
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else
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{
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uint16_t v16=0;
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if(g_get_value_fun(&v16)==0)
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{
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v=(v16<<16)|v16;
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DAC->DHR12RD=v;
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}
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}
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}
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}
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