2025-06-27 00:32:57 +08:00
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#ifndef BASE_H__
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#define BASE_H__
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#include "stm32f4xx.h"
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2025-07-05 19:47:28 +08:00
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//λ<><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,ʵ<><CAB5>51<35><31><EFBFBD>Ƶ<EFBFBD>GPIO<49><4F><EFBFBD>ƹ<EFBFBD><C6B9><EFBFBD>
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//<2F><><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5>˼<EFBFBD><CBBC>,<2C>ο<EFBFBD><<CM3Ȩ<33><C8A8>ָ<EFBFBD><D6B8>>><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(87ҳ~92ҳ).M4ͬM3<4D><33><EFBFBD><EFBFBD>,ֻ<>ǼĴ<C7BC><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>.
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//IO<49>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD>궨<EFBFBD><EAB6A8>
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2025-06-27 00:32:57 +08:00
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#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2))
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#define MEM_ADDR(addr) *((volatile unsigned long *)(addr))
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#define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum))
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2025-07-05 19:47:28 +08:00
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//IO<49>ڵ<EFBFBD>ַӳ<D6B7><D3B3>
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2025-06-27 00:32:57 +08:00
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#define GPIOA_ODR_Addr (GPIOA_BASE+20) //0x40020014
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#define GPIOB_ODR_Addr (GPIOB_BASE+20) //0x40020414
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#define GPIOC_ODR_Addr (GPIOC_BASE+20) //0x40020814
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#define GPIOD_ODR_Addr (GPIOD_BASE+20) //0x40020C14
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#define GPIOE_ODR_Addr (GPIOE_BASE+20) //0x40021014
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#define GPIOF_ODR_Addr (GPIOF_BASE+20) //0x40021414
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#define GPIOG_ODR_Addr (GPIOG_BASE+20) //0x40021814
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#define GPIOH_ODR_Addr (GPIOH_BASE+20) //0x40021C14
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#define GPIOI_ODR_Addr (GPIOI_BASE+20) //0x40022014
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#define GPIOA_IDR_Addr (GPIOA_BASE+16) //0x40020010
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#define GPIOB_IDR_Addr (GPIOB_BASE+16) //0x40020410
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#define GPIOC_IDR_Addr (GPIOC_BASE+16) //0x40020810
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#define GPIOD_IDR_Addr (GPIOD_BASE+16) //0x40020C10
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#define GPIOE_IDR_Addr (GPIOE_BASE+16) //0x40021010
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#define GPIOF_IDR_Addr (GPIOF_BASE+16) //0x40021410
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#define GPIOG_IDR_Addr (GPIOG_BASE+16) //0x40021810
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#define GPIOH_IDR_Addr (GPIOH_BASE+16) //0x40021C10
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#define GPIOI_IDR_Addr (GPIOI_BASE+16) //0x40022010
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2025-07-05 19:47:28 +08:00
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//IO<49>ڲ<EFBFBD><DAB2><EFBFBD>,ֻ<>Ե<EFBFBD>һ<EFBFBD><D2BB>IO<49><4F>!
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//ȷ<><C8B7>n<EFBFBD><6E>ֵС<D6B5><D0A1>16!
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#define PAout(n) BIT_ADDR(GPIOA_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PAin(n) BIT_ADDR(GPIOA_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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2025-07-05 19:47:28 +08:00
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#define PBout(n) BIT_ADDR(GPIOB_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PBin(n) BIT_ADDR(GPIOB_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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2025-07-05 19:47:28 +08:00
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#define PCout(n) BIT_ADDR(GPIOC_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PCin(n) BIT_ADDR(GPIOC_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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2025-07-05 19:47:28 +08:00
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#define PDout(n) BIT_ADDR(GPIOD_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PDin(n) BIT_ADDR(GPIOD_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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2025-07-05 19:47:28 +08:00
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#define PEout(n) BIT_ADDR(GPIOE_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PEin(n) BIT_ADDR(GPIOE_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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2025-07-05 19:47:28 +08:00
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#define PFout(n) BIT_ADDR(GPIOF_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PFin(n) BIT_ADDR(GPIOF_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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2025-07-05 19:47:28 +08:00
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#define PGout(n) BIT_ADDR(GPIOG_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PGin(n) BIT_ADDR(GPIOG_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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2025-07-05 19:47:28 +08:00
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#define PHout(n) BIT_ADDR(GPIOH_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PHin(n) BIT_ADDR(GPIOH_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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2025-07-05 19:47:28 +08:00
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#define PIout(n) BIT_ADDR(GPIOI_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PIin(n) BIT_ADDR(GPIOI_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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2025-06-27 00:32:57 +08:00
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#endif
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