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6502_gcc.S编译出来基本无差异

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andy
2025-07-09 00:55:12 +08:00
parent 403b03e115
commit 61093b6cdf
3 changed files with 16 additions and 32 deletions
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42
Project/Src/NES/6502_gcc.S
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@@ -103,9 +103,8 @@ _10:// BPL *
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
tst m6502_nz,#0x80000000 tst m6502_nz,#0x80000000
ldrsb r0,[m6502_pc],#1 ldrsb r0,[m6502_pc],#1
IT EQ ITT EQ
addeq m6502_pc,m6502_pc,r0 addeq m6502_pc,m6502_pc,r0
IT EQ
subeq cycles,cycles,#256 subeq cycles,cycles,#256
fetch 2 fetch 2
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
@@ -230,9 +229,8 @@ _30:// BMI *
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
tst m6502_nz,#0x80000000 tst m6502_nz,#0x80000000
ldrsb r0,[m6502_pc],#1 ldrsb r0,[m6502_pc],#1
IT NE ITT NE
addne m6502_pc,m6502_pc,r0 addne m6502_pc,m6502_pc,r0
IT NE
subne cycles,cycles,#256 subne cycles,cycles,#256
fetch 2 fetch 2
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
@@ -346,9 +344,8 @@ _50:// BVC *
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
tst cycles,#CYC_V tst cycles,#CYC_V
ldrsb r0,[m6502_pc],#1 ldrsb r0,[m6502_pc],#1
IT EQ ITT EQ
addeq m6502_pc,m6502_pc,r0 addeq m6502_pc,m6502_pc,r0
IT EQ
subeq cycles,cycles,#256 subeq cycles,cycles,#256
fetch 2 fetch 2
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
@@ -442,8 +439,7 @@ _6A:// ROR
_6C:// JMP ($nnnn) JMP ($data16) <EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ѱַ ********************************* _6C:// JMP ($nnnn) JMP ($data16) <EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ѱַ *********************************
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
doABS doABS
ldr r1, =memmap_tbl add r1, globalptr,#memmap_tbl
add r1, globalptr
and r2,addy,#0xE000 // and r2,addy,#0xE000 //
// ldr r1,[r1,r2,lsr#11] // >>11 addr&0x7FF // ldr r1,[r1,r2,lsr#11] // >>11 addr&0x7FF
lsr r0,r2,#11 lsr r0,r2,#11
@@ -473,9 +469,8 @@ _70:// BVS *
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
tst cycles,#CYC_V tst cycles,#CYC_V
ldrsb r0,[m6502_pc],#1 ldrsb r0,[m6502_pc],#1
IT NE ITT NE
addne m6502_pc,m6502_pc,r0 addne m6502_pc,m6502_pc,r0
IT NE
subne cycles,cycles,#256 subne cycles,cycles,#256
fetch 2 fetch 2
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
@@ -578,9 +573,8 @@ _90:// BCC *
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
tst cycles,#CYC_C // Test Carry tst cycles,#CYC_C // Test Carry
ldrsb r0,[m6502_pc],#1 ldrsb r0,[m6502_pc],#1
IT EQ ITT EQ
addeq m6502_pc,m6502_pc,r0 addeq m6502_pc,m6502_pc,r0
IT EQ
subeq cycles,cycles,#256 subeq cycles,cycles,#256
fetch 2 fetch 2
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
@@ -708,9 +702,8 @@ _B0:// BCS *
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
tst cycles,#CYC_C // Test Carry tst cycles,#CYC_C // Test Carry
ldrsb r0,[m6502_pc],#1 ldrsb r0,[m6502_pc],#1
IT NE ITT NE
addne m6502_pc,m6502_pc,r0 addne m6502_pc,m6502_pc,r0
IT NE
subne cycles,cycles,#256 subne cycles,cycles,#256
fetch 2 fetch 2
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
@@ -844,9 +837,8 @@ _D0:// BNE *
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
tst m6502_nz,#0xff tst m6502_nz,#0xff
ldrsb r0,[m6502_pc],#1 ldrsb r0,[m6502_pc],#1
IT NE ITT NE
addne m6502_pc,m6502_pc,r0 addne m6502_pc,m6502_pc,r0
IT NE
subne cycles,cycles,#256 subne cycles,cycles,#256
fetch 2 fetch 2
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
@@ -959,9 +951,8 @@ _F0:// BEQ *
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
tst m6502_nz,#0xff tst m6502_nz,#0xff
ldrsb r0,[m6502_pc],#1 ldrsb r0,[m6502_pc],#1
IT EQ ITT EQ
addeq m6502_pc,m6502_pc,r0 addeq m6502_pc,m6502_pc,r0
IT EQ
subeq cycles,cycles,#256 subeq cycles,cycles,#256
fetch 2 fetch 2
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
@@ -1066,8 +1057,7 @@ run6502:
ldr cpu_zpage,=NES_RAM // r11 ldr cpu_zpage,=NES_RAM // r11
ldr cpu_zpage,[cpu_zpage] // NES_RAM<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><EFBFBD> ldr cpu_zpage,[cpu_zpage] // NES_RAM<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><EFBFBD>
ldr r1, =cpuregs add r1, globalptr,#cpuregs
add r1, globalptr
ldmia r1,{m6502_nz-m6502_pc} // restore 6502 state<EFBFBD>ָ<EFBFBD>6502״̬ r3-r9 ldmia r1,{m6502_nz-m6502_pc} // restore 6502 state<EFBFBD>ָ<EFBFBD>6502״̬ r3-r9
add cycles,cycles,r0 add cycles,cycles,r0
@@ -1081,8 +1071,7 @@ exit_run:
cmp r0,#0x01; cmp r0,#0x01;
beq NMI6502 // EQ <EFBFBD><EFBFBD><EFBFBD><EFBFBD>(EQual) beq NMI6502 // EQ <EFBFBD><EFBFBD><EFBFBD><EFBFBD>(EQual)
exit_nmi: exit_nmi:
ldr r0, =cpuregs add r0, globalptr,#cpuregs
add r0, globalptr
stmia r0,{m6502_nz-m6502_pc} // <EFBFBD><EFBFBD><EFBFBD><EFBFBD>6502״̬ r3-r9 stmia r0,{m6502_nz-m6502_pc} // <EFBFBD><EFBFBD><EFBFBD><EFBFBD>6502״̬ r3-r9
ldmfd sp!,{r4-r11,pc} // exit ldmfd sp!,{r4-r11,pc} // exit
@ .end @ .end
@@ -1142,8 +1131,7 @@ CPU_reset: // called by loadcart (r0-r9 are free to use)
mov m6502_x,#0 mov m6502_x,#0
mov m6502_y,#0 mov m6502_y,#0
mov m6502_nz,#0 mov m6502_nz,#0
ldr m6502_rmem, =readmem_tbl add m6502_rmem, globalptr,#readmem_tbl // <EFBFBD><EFBFBD>readmem_tbl<EFBFBD>ĵ<EFBFBD>ַ<EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>m6502_rmem
add m6502_rmem, globalptr // <EFBFBD><EFBFBD>readmem_tbl<EFBFBD>ĵ<EFBFBD>ַ<EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>m6502_rmem
// ldr r0,=NES_RAM+0x100 // 256 // ldr r0,=NES_RAM+0x100 // 256
ldr r0,=NES_RAM // NES_RAM<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><EFBFBD> ldr r0,=NES_RAM // NES_RAM<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><EFBFBD>
@@ -1159,8 +1147,7 @@ CPU_reset: // called by loadcart (r0-r9 are free to use)
ldr r12,=RES_VECTOR // <EFBFBD><EFBFBD>λ<EFBFBD>ж<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ ldr r12,=RES_VECTOR // <EFBFBD><EFBFBD>λ<EFBFBD>ж<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
bl Vec6502 bl Vec6502
ldr r0, =cpuregs add r0, globalptr,#cpuregs // <EFBFBD><EFBFBD>ȡ<EFBFBD><EFBFBD>ַ
add r0, globalptr // <EFBFBD><EFBFBD>ȡ<EFBFBD><EFBFBD>ַ
stmia r0,{m6502_nz-m6502_pc} // <EFBFBD><EFBFBD><EFBFBD><EFBFBD>6502״̬ stmia r0,{m6502_nz-m6502_pc} // <EFBFBD><EFBFBD><EFBFBD><EFBFBD>6502״̬
ldr r1,=exit_run ldr r1,=exit_run
@@ -1365,8 +1352,7 @@ dma_W: // (4014) sprite DMA transfer
sub cycles,cycles,#512*256 sub cycles,cycles,#512*256
stmfd sp!,{r3,lr} stmfd sp!,{r3,lr}
and r1,r0,#0xe0 and r1,r0,#0xe0
ldr r2, =memmap_tbl add r2, globalptr,#memmap_tbl
add r2, globalptr
lsr r1,r1,#3 lsr r1,r1,#3
ldr r2,[r2,r1] ldr r2,[r2,r1]
and r0,r0,#0xff and r0,r0,#0xff

3
Project/Src/NES/6502cart_gcc.S
View File

@@ -156,8 +156,7 @@ flush: // update m6502_pc & lastbank
ldr r1,[globalptr,#lastbank] ldr r1,[globalptr,#lastbank]
sub r9,r9,r1 sub r9,r9,r1
and r1,r9,#0xE000 // //r9<EFBFBD><EFBFBD>0xe000<EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> and r1,r9,#0xE000 // //r9<EFBFBD><EFBFBD>0xe000<EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
ldr r2, =memmap_tbl add r2, globalptr,#memmap_tbl // //<EFBFBD>Ѵ洢<EFBFBD><EFBFBD>ӳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>r2
add r2, globalptr // //<EFBFBD>Ѵ洢<EFBFBD><EFBFBD>ӳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>r2
lsr r1,r1,#11 // //>>11λ r1/2048 lsr r1,r1,#11 // //>>11λ r1/2048
ldr r0,[r2,r1] // //<EFBFBD><EFBFBD>ȡr2<EFBFBD><EFBFBD>ַ+r1ƫ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD>r0 ldr r0,[r2,r1] // //<EFBFBD><EFBFBD>ȡr2<EFBFBD><EFBFBD>ַ+r1ƫ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD>r0

3
Project/Src/NES/6502mac_gcc.S
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@@ -9,8 +9,7 @@
// <EFBFBD><EFBFBD> 6502 PC <EFBFBD><EFBFBD>ַת<EFBFBD><EFBFBD>Ϊ ROM ƫ<EFBFBD>Ƶ<EFBFBD>ַ // <EFBFBD><EFBFBD> 6502 PC <EFBFBD><EFBFBD>ַת<EFBFBD><EFBFBD>Ϊ ROM ƫ<EFBFBD>Ƶ<EFBFBD>ַ
.macro encodePC .macro encodePC
and r1, m6502_pc, #0xE000 // r9 & 0xE000 and r1, m6502_pc, #0xE000 // r9 & 0xE000
ldr r2, =memmap_tbl add r2, globalptr,#memmap_tbl // <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD>ӳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><EFBFBD> r2
add r2, globalptr // <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD>ӳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><EFBFBD> r2
lsr r0, r1, #11 // >>11λ lsr r0, r1, #11 // >>11λ
ldr r0, [r2, r0] // <EFBFBD><EFBFBD> r2 + r0 <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD> r0 ldr r0, [r2, r0] // <EFBFBD><EFBFBD> r2 + r0 <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD> r0
str r0, [globalptr,#lastbank] // <EFBFBD><EFBFBD><EFBFBD>浱ǰ bank ƫ<EFBFBD><EFBFBD> str r0, [globalptr,#lastbank] // <EFBFBD><EFBFBD><EFBFBD>浱ǰ bank ƫ<EFBFBD><EFBFBD>