整理代码
This commit is contained in:
@@ -589,7 +589,7 @@ static void FILDER_Enter(WIN_FilderStruct *filder, int x, int y)
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// <20>ļ<EFBFBD><C4BC><EFBFBD>Ϣ
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char *txt_buff = mymalloc(512);
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FILDER_GetFileRoute(filder);
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sprintf(txt_buff, "·<EFBFBD><EFBFBD><EFBFBD><EFBFBD>%s\n<EFBFBD><EFBFBD>С<EFBFBD><EFBFBD>%lld Byte", filder->fileName, filder->file[filder->index].size);
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sprintf(txt_buff, "·<EFBFBD><EFBFBD><EFBFBD><EFBFBD>%s\n<EFBFBD><EFBFBD>С<EFBFBD><EFBFBD>%u Byte", filder->fileName, (uint32_t)filder->file[filder->index].size);
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MSGBOX_Tips((WIN_WindowStruct *)filder, "<EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD>Ϣ", txt_buff, "ȷ<EFBFBD><EFBFBD>");
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myfree(txt_buff);
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}
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -92,7 +92,6 @@ cpu6502_init:
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.type map67_, %function
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map67_: // rom paging.. r0=page#
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// ----------------------------------------------------------------------------
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ldr r1,[globalptr,#rommask]
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and r0,r1,r0,lsl#13
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ldr r1,[globalptr,#rombase]
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@@ -103,7 +102,6 @@ map67_: // rom paging.. r0=page#
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.type map89_, %function
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map89_: // rom paging.. r0=page# ROM<EFBFBD><EFBFBD>ҳ
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// ----------------------------------------------------------------------------
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ldr r1,[globalptr,#rombase] // rom<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>ַ
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sub r1,r1,#0x8000
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ldr r2,[globalptr,#rommask]
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@@ -114,7 +112,6 @@ map89_: // rom paging.. r0=page# ROM
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.type mapAB_, %function
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mapAB_:
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// ----------------------------------------------------------------------------
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ldr r1,[globalptr,#rombase]
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sub r1,r1,#0xa000
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ldr r2,[globalptr,#rommask]
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@@ -125,7 +122,6 @@ mapAB_:
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.type mapCD_, %function
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mapCD_:
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// ----------------------------------------------------------------------------
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ldr r1,[globalptr,#rombase]
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sub r1,r1,#0xc000
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ldr r2,[globalptr,#rommask]
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@@ -136,7 +132,6 @@ mapCD_:
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.type mapEF_, %function
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mapEF_:
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// ----------------------------------------------------------------------------
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ldr r1,[globalptr,#rombase]
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sub r1,r1,#0xe000
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ldr r2,[globalptr,#rommask]
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@@ -147,7 +142,6 @@ mapEF_:
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.type map89AB_, %function
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map89AB_:
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// ----------------------------------------------------------------------------
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ldr r1,[globalptr,#rombase] // rom<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD><EFBFBD>
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sub r1,r1,#0x8000
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ldr r2,[globalptr,#rommask]
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@@ -171,7 +165,6 @@ flush: // update m6502_pc & lastbank
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.type mapCDEF_, %function
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mapCDEF_:
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// ----------------------------------------------------------------------------
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ldr r1,[globalptr,#rombase]
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sub r1,r1,#0xc000
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ldr r2,[globalptr,#rommask]
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@@ -183,7 +176,6 @@ mapCDEF_:
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.type map89ABCDEF_, %function
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map89ABCDEF_:
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// ----------------------------------------------------------------------------
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ldr r1,[globalptr,#rombase]
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sub r1,r1,#0x8000
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ldr r2,[globalptr,#rommask]
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@@ -1,512 +0,0 @@
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C EQU 0x01 ;//6502 flags 6502<30><32>־
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Z EQU 0x02
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I EQU 0x04
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D EQU 0x08
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B EQU 0x10 ;//(allways 1 except when IRQ pushes it)IRQ<52>ⲿ<EFBFBD>ж<EFBFBD>
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R EQU 0x20 ;//(locked at 1)
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V EQU 0x40
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N EQU 0x80
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MACRO ;//translate from 6502 PC to rom offset<65><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD>6502 PC ROM<4F><4D>ƫ<EFBFBD><C6AB><EFBFBD><EFBFBD>
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encodePC
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and r1,m6502_pc,#0xE000 ;//r9<72><39>0xe000<30><30>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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adr r2,memmap_tbl ;//<2F>Ѵ洢<D1B4><E6B4A2>ӳ<EFBFBD><D3B3><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>ص<EFBFBD>r2
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;// ldr r0,[r2,r1,lsr#11] ;//<2F>Ĺ<EFBFBD><C4B9><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32>
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lsr r0,r1,#11 ;//>>11λ r1/2048
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ldr r0,[r2,r0] ;//<2F><>ȡr2<72><32>ַ+r1ƫ<31>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>ݵ<EFBFBD>r0
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str r0,lastbank ;//<2F><><EFBFBD><EFBFBD>6502PC<50><43> ROM<4F><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD><C6AB><EFBFBD><EFBFBD>
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add m6502_pc,m6502_pc,r0 ;//m6502_pc+r0
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MEND
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MACRO ;//pack 6502 flags into r0 6502<30><32>־<EFBFBD><D6BE>װ<EFBFBD><D7B0>R0
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encodeP $extra
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and r0,cycles,#CYC_V+CYC_D+CYC_I+CYC_C
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tst m6502_nz,#0x80000000;//PSR_N
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orrne r0,r0,#N ;N
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tst m6502_nz,#0xff
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orreq r0,r0,#Z ;Z
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orr r0,r0,#$extra ;R(&B)
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MEND
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MACRO ;//;<3B>궨<EFBFBD><EAB6A8>//unpack 6502 flags from r0 <20><>ѹ<EFBFBD><D1B9>6502<30><32>R0<52>ı<EFBFBD>־
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decodeP
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bic cycles,cycles,#CYC_V+CYC_D+CYC_I+CYC_C
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and r1,r0,#V+D+I+C
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orr cycles,cycles,r1 ;//VDIC
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bic m6502_nz,r0,#0xFD ;//r0 is signed
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eor m6502_nz,m6502_nz,#Z
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MEND ;// ;<3B>궨<EFBFBD><EAB6A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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MACRO
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fetch $count ;//<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ;$<24><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> $<24><><EFBFBD><EFBFBD>1<EFBFBD><31>$<24><><EFBFBD><EFBFBD>2<EFBFBD><32>...
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;//---------------------------------------------------------------------
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ldr r0,clocksh ;//<2F><><EFBFBD><EFBFBD>apu<70><75>Ҫ<EFBFBD><D2AA>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
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add r0,r0,#$count
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str r0,clocksh
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ldr r1,opz ;//<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>ַ
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;//-------------------------------------------------------------------------
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subs cycles,cycles,#$count*256;//CYCLE=256 ;// 3*256 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD><30>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD>2<EFBFBD><32>ָ<EFBFBD><D6B8>
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ldrplb r0,[m6502_pc],#1 ; //<2F>Ӵ洢<D3B4><E6B4A2><EFBFBD>м<EFBFBD><D0BC><EFBFBD><EFBFBD>ֽڵ<D6BD>һ<EFBFBD><D2BB><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD> r0=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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; ldrpl pc,[m6502_optbl,r0,lsl#2] ;//r10 ********r0=r0x4***<2A><><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD>ĵ<EFBFBD>ַ**************************************
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ldrpl pc,[r1,r0,lsl#2]
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ldr pc,nexttimeout
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MEND
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MACRO ;//<2F><>ͬ<EFBFBD><CDAC><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˽<EFBFBD>λ<EFBFBD><CEBB>λ0<CEBB><30>
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fetch_c $count ;//same as fetch except it adds the Carry (bit 0) also.
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;//---------------------------------------------------------------------
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ldr r0,clocksh ;//<2F><><EFBFBD><EFBFBD>apu<70><75>Ҫ<EFBFBD><D2AA>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
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add r0,r0,#$count
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str r0,clocksh
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ldr r1,opz ;//<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>ַ
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;//-------------------------------------------------------------------------
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sbcs cycles,cycles,#$count*256;//CYCLE=256
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ldrplb r0,[m6502_pc],#1
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; ldrpl pc,[m6502_optbl,r0,lsl#2]
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ldrpl pc,[r1,r0,lsl#2]
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ldr pc,nexttimeout
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MEND
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MACRO
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clearcycles
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and cycles,cycles,#CYC_MASK ;Save CPU bits
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MEND
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MACRO
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readmemabs
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and r1,addy,#0xE000
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adr lr,%F0
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;// ldr pc,[m6502_rmem,r1,lsr#11] ;//in: addy,r1=addy&0xE000 (for rom_R)
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lsr r1,r1,#11 ;//<2F>Ĺ<EFBFBD><C4B9><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32> >>11
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ldr pc,[m6502_rmem,r1]
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0 ;//out: r0=val (bits 8-31=0 (LSR,ROR,INC,DEC,ASL)), addy preserved for RMW instructions
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MEND
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MACRO
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readmemzp
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ldrb r0,[cpu_zpage,addy]
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MEND
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MACRO
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readmemzpi
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;// ldrb r0,[cpu_zpage,addy,lsr#24]
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lsr r0,addy,#24 ;//<2F>Ĺ<EFBFBD><C4B9><EFBFBD><EFBFBD><EFBFBD>3<EFBFBD><33>
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ldrb r0,[cpu_zpage,r0]
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MEND
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MACRO
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readmemzps
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ldrsb m6502_nz,[cpu_zpage,addy];RAM
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MEND
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MACRO
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readmemimm
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ldrb r0,[m6502_pc],#1 ;ROM
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MEND
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MACRO
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readmemimms
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ldrsb m6502_nz,[m6502_pc],#1
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MEND
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MACRO
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readmem
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[ _type = _ABS
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readmemabs
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]
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[ _type = _ZP
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readmemzp
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]
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[ _type = _ZPI
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readmemzpi
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]
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[ _type = _IMM
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readmemimm
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]
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MEND
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MACRO
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readmems
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[ _type = _ABS
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readmemabs
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orr m6502_nz,r0,r0,lsl#24
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]
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[ _type = _ZP
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readmemzps
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]
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[ _type = _IMM
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readmemimms
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]
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MEND
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MACRO
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writememabs
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and r1,addy,#0xe000
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adr r2,writemem_tbl
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adr lr,%F0
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;// ldr pc,[r2,r1,lsr#11] ;//in: addy,r0=val(bits 8-31=?)
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lsr r1,r1,#11 ;//<2F>Ĺ<EFBFBD><C4B9><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32> >>11
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ldr pc,[r2,r1]
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0 ;out: r0,r1,r2,addy=?
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MEND
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MACRO
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writememzp
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strb r0,[cpu_zpage,addy]
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MEND
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MACRO
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writememzpi
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;// strb r0,[cpu_zpage,addy,lsr#24]
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lsr r1,addy,#24 ;//<2F>Ĺ<EFBFBD><C4B9><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32> >>24
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strb r0,[cpu_zpage,r1]
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MEND
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MACRO
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writemem ;//д<>ڴ<EFBFBD>
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[ _type = _ABS
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writememabs
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]
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[ _type = _ZP
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writememzp
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]
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[ _type = _ZPI
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writememzpi
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]
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MEND
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;----------------------------------------------------------------------------
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MACRO ;///////////////////////////////// /////////////////////
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push16 ;push r0
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mov r1,r0,lsr#8
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ldr r2,m6502_s
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strb r1,[r2],#-1
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orr r2,r2,#0x100
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strb r0,[r2],#-1
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strb r2,m6502_s
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MEND ;r1,r2=?
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MACRO
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push8 $x
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ldr r2,m6502_s
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strb $x,[r2],#-1
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strb r2,m6502_s
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MEND ;r2=?
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MACRO
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pop16 ;pop m6502_pc
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ldrb r2,m6502_s
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add r2,r2,#2
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strb r2,m6502_s
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ldr r2,m6502_s
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ldrb r0,[r2],#-1
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orr r2,r2,#0x100
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ldrb m6502_pc,[r2]
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orr m6502_pc,m6502_pc,r0,lsl#8
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MEND ;r0,r1=?
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MACRO
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pop8 $x
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ldrb r2,m6502_s
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add r2,r2,#1
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strb r2,m6502_s
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orr r2,r2,#0x100
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ldrsb $x,[cpu_zpage,r2] ;signed for PLA & PLP
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MEND ;r2=?
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;----------------------------------------------------------------------------
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;doXXX: load addy, increment m6502_pc
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GBLA _type
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_IMM EQU 1 ;immediate
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_ZP EQU 2 ;zero page
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_ZPI EQU 3 ;zero page indexed
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_ABS EQU 4 ;absolute
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MACRO
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doABS ;absolute $nnnn
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_type SETA _ABS
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ldrb addy,[m6502_pc],#1
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ldrb r0,[m6502_pc],#1
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orr addy,addy,r0,lsl#8
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MEND
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MACRO
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doAIX ;absolute indexed X $nnnn,X
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_type SETA _ABS
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ldrb addy,[m6502_pc],#1
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ldrb r0,[m6502_pc],#1
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orr addy,addy,r0,lsl#8
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add addy,addy,m6502_x,lsr#24
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; bic addy,addy,#0xff0000 ;Base Wars needs this
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MEND
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MACRO
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doAIY ;absolute indexed Y $nnnn,Y
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_type SETA _ABS
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ldrb addy,[m6502_pc],#1
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ldrb r0,[m6502_pc],#1
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orr addy,addy,r0,lsl#8
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add addy,addy,m6502_y,lsr#24
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; bic addy,addy,#0xff0000 ;Tecmo Bowl needs this
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MEND
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MACRO
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doIMM ;immediate #$nn
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_type SETA _IMM
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MEND
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MACRO
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doIIX ;indexed indirect X ($nn,X)
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_type SETA _ABS
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ldrb r0,[m6502_pc],#1
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add r0,m6502_x,r0,lsl#24
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;//ldrb addy,[cpu_zpage,r0,lsr#24] ;//<2F><><EFBFBD><EFBFBD>:ָ<><D6B8><EFBFBD><EFBFBD>ת<EFBFBD>䲻<EFBFBD><E4B2BB><EFBFBD><EFBFBD>
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lsr addy,r0,#24 ;//<2F>Ĺ<EFBFBD><C4B9><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32> >>24
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ldrb addy,[cpu_zpage,addy]
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add r0,r0,#0x01000000
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;//ldrb r1,[cpu_zpage,r0,lsr#24] ;//R1,LSR#2;<3B><>R1<52>е<EFBFBD><D0B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2λ
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lsr r1,r0,#24 ;//<2F>Ĺ<EFBFBD><C4B9><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32>
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ldrb r1,[cpu_zpage,r1]
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orr addy,addy,r1,lsl#8
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MEND
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MACRO
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doIIY ;indirect indexed Y ($nn),Y
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_type SETA _ABS
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ldrb r0,[m6502_pc],#1
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;// ldrb addy,[r0,cpu_zpage]! ;;<3B><><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD><DDB4><EFBFBD>֮ǰ,<2C><>ƫ<EFBFBD><C6AB><EFBFBD><EFBFBD><EFBFBD>ӵ<EFBFBD>Rn <20><>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵĴ洢<C4B4><E6B4A2>ַ
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;//<2F><>ʹ<EFBFBD>ú<EFBFBD>"!",<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD>ص<EFBFBD>Rn<52><6E>
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ldrb addy,[r0,cpu_zpage]
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add r0,r0,cpu_zpage ;//////////////////////////////////////
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ldrb r1,[r0,#1]
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orr addy,addy,r1,lsl#8
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add addy,addy,m6502_y,lsr#24
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; bic addy,addy,#0xff0000 ;Zelda2 needs this
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
doZPI ;Zeropage indirect ($nn)
|
||||
_type SETA _ABS
|
||||
ldrb r0,[m6502_pc],#1
|
||||
;// ldrb addy,[r0,cpu_zpage]!;;<3B><><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD><DDB4><EFBFBD>֮ǰ,<2C><>ƫ<EFBFBD><C6AB><EFBFBD><EFBFBD><EFBFBD>ӵ<EFBFBD>Rn <20><>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵĴ洢<C4B4><E6B4A2>ַ
|
||||
;//<2F><>ʹ<EFBFBD>ú<EFBFBD>"!",<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD>ص<EFBFBD>Rn<52><6E>
|
||||
ldrb addy,[r0,cpu_zpage]
|
||||
add r0,r0,cpu_zpage
|
||||
|
||||
|
||||
ldrb r1,[r0,#1]
|
||||
orr addy,addy,r1,lsl#8
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
doZ ;zero page $nn
|
||||
_type SETA _ZP
|
||||
ldrb addy,[m6502_pc],#1
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
doZ2 ;zero page $nn
|
||||
_type SETA _ZP
|
||||
ldrb addy,[m6502_pc],#2 ;ugly thing for bbr/bbs
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
doZIX ;zero page indexed X $nn,X
|
||||
_type SETA _ZP
|
||||
ldrb addy,[m6502_pc],#1
|
||||
add addy,addy,m6502_x,lsr#24
|
||||
and addy,addy,#0xff ;Rygar needs this
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
doZIXf ;zero page indexed X $nn,X
|
||||
_type SETA _ZPI
|
||||
ldrb addy,[m6502_pc],#1
|
||||
add addy,m6502_x,addy,lsl#24
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
doZIY ;zero page indexed Y $nn,Y
|
||||
_type SETA _ZP
|
||||
ldrb addy,[m6502_pc],#1
|
||||
add addy,addy,m6502_y,lsr#24
|
||||
and addy,addy,#0xff
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
doZIYf ;zero page indexed Y $nn,Y
|
||||
_type SETA _ZPI
|
||||
ldrb addy,[m6502_pc],#1
|
||||
add addy,m6502_y,addy,lsl#24
|
||||
MEND
|
||||
|
||||
;----------------------------------------------------------------------------
|
||||
|
||||
MACRO
|
||||
opADC
|
||||
readmem
|
||||
movs r1,cycles,lsr#1 ;get C
|
||||
subcs r0,r0,#0x00000100
|
||||
adcs m6502_a,m6502_a,r0,ror#8
|
||||
mov m6502_nz,m6502_a,asr#24 ;NZ
|
||||
orr cycles,cycles,#CYC_C+CYC_V ;Prepare C & V
|
||||
bicvc cycles,cycles,#CYC_V ;V
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
opAND
|
||||
readmem
|
||||
and m6502_a,m6502_a,r0,lsl#24
|
||||
mov m6502_nz,m6502_a,asr#24 ;NZ
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
opASL
|
||||
readmem
|
||||
add r0,r0,r0
|
||||
orrs m6502_nz,r0,r0,lsl#24 ;NZ
|
||||
orr cycles,cycles,#CYC_C ;Prepare C
|
||||
writemem
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
opBIT
|
||||
readmem
|
||||
bic cycles,cycles,#CYC_V ;reset V
|
||||
tst r0,#V
|
||||
orrne cycles,cycles,#CYC_V ;V
|
||||
and m6502_nz,r0,m6502_a,lsr#24 ;Z
|
||||
orr m6502_nz,m6502_nz,r0,lsl#24 ;N
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
opCOMP $x ;A,X & Y
|
||||
readmem
|
||||
subs m6502_nz,$x,r0,lsl#24
|
||||
mov m6502_nz,m6502_nz,asr#24 ;NZ
|
||||
orr cycles,cycles,#CYC_C ;Prepare C
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
opDEC
|
||||
readmem
|
||||
sub r0,r0,#1
|
||||
orr m6502_nz,r0,r0,lsl#24 ;NZ
|
||||
writemem
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
opEOR
|
||||
readmem
|
||||
eor m6502_a,m6502_a,r0,lsl#24
|
||||
mov m6502_nz,m6502_a,asr#24 ;NZ
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
opINC
|
||||
readmem
|
||||
add r0,r0,#1
|
||||
orr m6502_nz,r0,r0,lsl#24 ;NZ
|
||||
writemem
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
opLOAD $x
|
||||
readmems
|
||||
mov $x,m6502_nz,lsl#24
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
opLSR
|
||||
[ _type = _ABS
|
||||
readmemabs
|
||||
movs r0,r0,lsr#1
|
||||
orr cycles,cycles,#CYC_C ;Prepare C
|
||||
mov m6502_nz,r0 ;Z, (N=0)
|
||||
writememabs
|
||||
]
|
||||
[ _type = _ZP
|
||||
ldrb m6502_nz,[cpu_zpage,addy]
|
||||
movs m6502_nz,m6502_nz,lsr#1 ;Z, (N=0)
|
||||
orr cycles,cycles,#CYC_C ;Prepare C
|
||||
strb m6502_nz,[cpu_zpage,addy]
|
||||
]
|
||||
[ _type = _ZPI
|
||||
;// ldrb m6502_nz,[cpu_zpage,addy,lsr#24]
|
||||
lsr m6502_nz,addy,#24 ;//<2F>Ĺ<EFBFBD><C4B9><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32>
|
||||
ldrb m6502_nz,[cpu_zpage,m6502_nz]
|
||||
|
||||
movs m6502_nz,m6502_nz,lsr#1 ;Z, (N=0)
|
||||
orr cycles,cycles,#CYC_C ;Prepare C
|
||||
;// strb m6502_nz,[cpu_zpage,addy,lsr#24]
|
||||
lsr r1,addy,#24 ;//<2F>Ĺ<EFBFBD><C4B9><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32>
|
||||
strb m6502_nz,[cpu_zpage,r1]
|
||||
|
||||
]
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
opORA
|
||||
readmem
|
||||
orr m6502_a,m6502_a,r0,lsl#24
|
||||
mov m6502_nz,m6502_a,asr#24
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
opROL
|
||||
readmem
|
||||
movs cycles,cycles,lsr#1 ;get C
|
||||
adc r0,r0,r0
|
||||
orrs m6502_nz,r0,r0,lsl#24 ;NZ
|
||||
adc cycles,cycles,cycles ;Set C
|
||||
writemem
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
opROR
|
||||
readmem
|
||||
movs cycles,cycles,lsr#1 ;get C
|
||||
orrcs r0,r0,#0x100
|
||||
movs r0,r0,lsr#1
|
||||
orr m6502_nz,r0,r0,lsl#24 ;NZ
|
||||
adc cycles,cycles,cycles ;Set C
|
||||
writemem
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
opSBC
|
||||
readmem
|
||||
movs r1,cycles,lsr#1 ;get C
|
||||
sbcs m6502_a,m6502_a,r0,lsl#24
|
||||
and m6502_a,m6502_a,#0xff000000
|
||||
mov m6502_nz,m6502_a,asr#24 ;NZ
|
||||
orr cycles,cycles,#CYC_C+CYC_V ;Prepare C & V
|
||||
bicvc cycles,cycles,#CYC_V ;V
|
||||
MEND
|
||||
|
||||
MACRO
|
||||
opSTORE $x
|
||||
mov r0,$x,lsr#24
|
||||
writemem
|
||||
MEND
|
||||
;----------------------------------------------------
|
||||
END
|
||||
@@ -1,199 +0,0 @@
|
||||
INCLUDE equates.s
|
||||
|
||||
|
||||
IMPORT NES_RAM
|
||||
IMPORT NES_SRAM
|
||||
IMPORT CPU_reset
|
||||
IMPORT romfile ;from main.c
|
||||
IMPORT cpu_data ; 6502.s
|
||||
IMPORT op_table
|
||||
|
||||
EXPORT cpu6502_init
|
||||
EXPORT map67_
|
||||
EXPORT map89_
|
||||
EXPORT mapAB_
|
||||
EXPORT mapCD_
|
||||
EXPORT mapEF_
|
||||
;----------------------------------------------------------------------------
|
||||
AREA rom_code, CODE, READONLY
|
||||
; THUMB
|
||||
PRESERVE8
|
||||
;----------------------------------------------------------------------------
|
||||
cpu6502_init PROC
|
||||
;----------------------------------------------------------------------------
|
||||
stmfd sp!,{r4-r11,lr}
|
||||
|
||||
ldr r10,=cpu_data ;<3B><>ȡ<EFBFBD><C8A1>ַ
|
||||
ldr r11,=NES_RAM ;r11=cpu_zpage
|
||||
|
||||
ldr r11,[r11] ;NES_RAM<41><4D><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
|
||||
;*******************************************************
|
||||
str r11,memmap_tbl ;NES_RAM<41><4D><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
|
||||
str r11,memmap_tbl+4
|
||||
str r11,memmap_tbl+8
|
||||
|
||||
ldr r0,=NES_SRAM ;NES_SRAM<41><4D><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
|
||||
ldr r0,[r0]
|
||||
str r0,memmap_tbl+12
|
||||
;**********************************************************************
|
||||
|
||||
ldr r0,=op_table ;<3B><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>ַ
|
||||
str r0,opz ;<3B><><EFBFBD><EFBFBD>
|
||||
|
||||
ldr r0,=romfile
|
||||
ldr r0,[r0] ;R0<52><30><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>ROMӳ<4D><EFBFBD><F1A3A8B0><EFBFBD>ͷ<EFBFBD><CDB7>
|
||||
add r3,r0,#16 ;r3<72><33><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>rom<6F><6D><EFBFBD><EFBFBD>(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7>
|
||||
str r3,rombase ;<3B><><EFBFBD><EFBFBD>rom<6F><6D><EFBFBD><EFBFBD>ַ
|
||||
;r3=rombase til end of loadcart so DON'T FUCK IT UP
|
||||
mov r2,#1
|
||||
ldrb r1,[r3,#-12] ; 16kB PROM<4F><4D><EFBFBD><EFBFBD>Ŀ 2
|
||||
rsb r0,r2,r1,lsl#14 ;romsize=X*16KB <<14 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8> r0=0x7fff
|
||||
str r0,rommask ;rommask=promsize-1 32768-1
|
||||
;------------------------------------------------------------------------------------
|
||||
mov r9,#0 ;(<28><><EFBFBD><EFBFBD><EFBFBD>κ<EFBFBD>encodePC<50><43>ӳ<EFBFBD><D3B3><EFBFBD><EFBFBD>*<2A><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>еĴ<D0B5><C4B4><EFBFBD>)
|
||||
str r9,lastbank ;6502PC<50><43> ROM<4F><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD><C6AB><EFBFBD><EFBFBD>д0
|
||||
|
||||
mov r0,#0 ;Ĭ<><C4AC>romӳ<6D><D3B3>
|
||||
bl map89AB_ ;89AB=1st 16k
|
||||
mov r0,#-1
|
||||
bl mapCDEF_ ;CDEF=last 16k
|
||||
;----------------------------------------------------------------------------
|
||||
|
||||
ldrb r1,[r3,#-10] ;get mapper#
|
||||
ldrb r2,[r3,#-9]
|
||||
tst r2,#0x0e ;long live DiskDude!
|
||||
and r1,r1,#0xf0
|
||||
and r2,r2,#0xf0
|
||||
orr r0,r2,r1,lsr#4
|
||||
movne r0,r1,lsr#4 ;ignore high nibble if header looks bad <09><><EFBFBD>Ը<EFBFBD><D4B8><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
;r0=mapper<65><72>
|
||||
;----------------------------------------------------------------------------
|
||||
|
||||
ldr r0,=Mapper_W
|
||||
str r0,writemem_tbl+16
|
||||
str r0,writemem_tbl+20
|
||||
str r0,writemem_tbl+24
|
||||
str r0,writemem_tbl+28
|
||||
;------------------------------------------------------------------------------
|
||||
|
||||
bl CPU_reset ;reset everything else
|
||||
ldmfd sp!,{r4-r11,lr}
|
||||
bx lr
|
||||
ENDP
|
||||
|
||||
;----------------------------------------------------------------------------
|
||||
map67_ ;rom paging.. r0=page#
|
||||
;----------------------------------------------------------------------------
|
||||
ldr r1,rommask
|
||||
and r0,r1,r0,lsl#13
|
||||
ldr r1,rombase
|
||||
add r0,r1,r0
|
||||
sub r0,r0,#0x6000
|
||||
str r0,memmap_tbl+12
|
||||
b flush
|
||||
;----------------------------------------------------------------------------
|
||||
map89_ ;rom paging.. r0=page# ROM<4F><4D>ҳ
|
||||
;----------------------------------------------------------------------------
|
||||
ldr r1,rombase ;rom<6F><6D>ʼ<EFBFBD><CABC>ַ
|
||||
sub r1,r1,#0x8000
|
||||
ldr r2,rommask
|
||||
and r0,r2,r0,lsl#13
|
||||
add r0,r1,r0
|
||||
str r0,memmap_tbl+16
|
||||
b flush
|
||||
;----------------------------------------------------------------------------
|
||||
mapAB_
|
||||
;----------------------------------------------------------------------------
|
||||
ldr r1,rombase
|
||||
sub r1,r1,#0xa000
|
||||
ldr r2,rommask
|
||||
and r0,r2,r0,lsl#13
|
||||
add r0,r1,r0
|
||||
str r0,memmap_tbl+20
|
||||
b flush
|
||||
;----------------------------------------------------------------------------
|
||||
mapCD_
|
||||
;----------------------------------------------------------------------------
|
||||
ldr r1,rombase
|
||||
sub r1,r1,#0xc000
|
||||
ldr r2,rommask
|
||||
and r0,r2,r0,lsl#13
|
||||
add r0,r1,r0
|
||||
str r0,memmap_tbl+24
|
||||
b flush
|
||||
;----------------------------------------------------------------------------
|
||||
mapEF_
|
||||
;----------------------------------------------------------------------------
|
||||
ldr r1,rombase
|
||||
sub r1,r1,#0xe000
|
||||
ldr r2,rommask
|
||||
and r0,r2,r0,lsl#13
|
||||
add r0,r1,r0
|
||||
str r0,memmap_tbl+28
|
||||
b flush
|
||||
;----------------------------------------------------------------------------
|
||||
map89AB_
|
||||
;----------------------------------------------------------------------------
|
||||
ldr r1,rombase ;rom<6F><6D><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7>
|
||||
sub r1,r1,#0x8000
|
||||
ldr r2,rommask
|
||||
and r0,r2,r0,lsl#14
|
||||
add r0,r1,r0
|
||||
str r0,memmap_tbl+16
|
||||
str r0,memmap_tbl+20
|
||||
flush ;update m6502_pc & lastbank
|
||||
ldr r1,lastbank
|
||||
sub r9,r9,r1
|
||||
and r1,r9,#0xE000 ;//r9<72><39>0xe000<30><30>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
adr r2,memmap_tbl ;//<2F>Ѵ洢<D1B4><E6B4A2>ӳ<EFBFBD><D3B3><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>ص<EFBFBD>r2
|
||||
lsr r1,r1,#11 ;//>>11λ r1/2048
|
||||
ldr r0,[r2,r1] ;//<2F><>ȡr2<72><32>ַ+r1ƫ<31>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>ݵ<EFBFBD>r0
|
||||
|
||||
str r0,lastbank ;//<2F><><EFBFBD><EFBFBD>6502PC<50><43> ROM<4F><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD><C6AB><EFBFBD><EFBFBD>
|
||||
add r9,r9,r0 ;//m6502_pc+r0
|
||||
orr lr,#0x01 ;lr<6C><72><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>1<EFBFBD><31>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>arm״̬
|
||||
bx lr
|
||||
|
||||
;----------------------------------------------------------------------------
|
||||
mapCDEF_
|
||||
;----------------------------------------------------------------------------
|
||||
ldr r1,rombase
|
||||
sub r1,r1,#0xc000
|
||||
ldr r2,rommask
|
||||
and r0,r2,r0,lsl#14
|
||||
add r0,r1,r0
|
||||
str r0,memmap_tbl+24
|
||||
str r0,memmap_tbl+28
|
||||
b flush
|
||||
;----------------------------------------------------------------------------
|
||||
map89ABCDEF_
|
||||
;----------------------------------------------------------------------------
|
||||
ldr r1,rombase
|
||||
sub r1,r1,#0x8000
|
||||
ldr r2,rommask
|
||||
and r0,r2,r0,lsl#15
|
||||
add r0,r1,r0
|
||||
str r0,memmap_tbl+16
|
||||
str r0,memmap_tbl+20
|
||||
str r0,memmap_tbl+24
|
||||
str r0,memmap_tbl+28
|
||||
b flush
|
||||
;*************************************************************************************
|
||||
IMPORT asm_Mapper_Write;
|
||||
Mapper_W
|
||||
;-------------------------------------------
|
||||
stmfd sp!,{r3,lr} ;LR <20>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ջ
|
||||
mov r1,r12
|
||||
bl asm_Mapper_Write
|
||||
ldmfd sp!,{r3,lr}
|
||||
orr lr,#0x01 ;lr<6C><72><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>1<EFBFBD><31>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>arm״̬
|
||||
bx lr
|
||||
; nop
|
||||
;---------------------------------------------------------------------------------------
|
||||
|
||||
END
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1,33 +0,0 @@
|
||||
|
||||
globalptr RN r10 ;//=wram_globals* ptr
|
||||
;//cpu_zpage RN r11 ;=CPU_RAM
|
||||
;----------------------------------------------------------------------------
|
||||
|
||||
|
||||
MAP 0,globalptr ;//MAP <20><><EFBFBD>ڶ<EFBFBD><DAB6><EFBFBD>һ<EFBFBD><D2BB><EFBFBD>ṹ<EFBFBD><E1B9B9><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD><DAB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
|
||||
;//6502.s ;//<2F><><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD><DAB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַΪglobalptr
|
||||
opz # 4 ;opz # 256*4 ;//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
|
||||
readmem_tbl # 8*4 ;//8*4
|
||||
writemem_tbl # 8*4 ;//8*4
|
||||
memmap_tbl # 8*4 ;//<2F>洢<EFBFBD><E6B4A2>ӳ<EFBFBD><D3B3> ram+rom
|
||||
cpuregs # 7*4 ;//1208<30><38><EFBFBD><EFBFBD>6502<30>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD>ʼ<EFBFBD><CABC>ַ
|
||||
m6502_s # 4 ;//
|
||||
lastbank # 4 ;//6502PC<50><43> ROM<4F><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD><C6AB><EFBFBD><EFBFBD>
|
||||
nexttimeout # 4
|
||||
|
||||
rombase # 4 ;//ROM<4F><4D>ʼ<EFBFBD><CABC>ַ
|
||||
romnumber # 4 ;// ROM<4F><4D>С
|
||||
rommask # 4 ;//ROM<4F><4D>Ĥ rommask=romsize-1
|
||||
|
||||
joy0data # 4 ;//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
joy1data # 4 ;//<2F>ֱ<EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
clocksh # 4 ;//ִ<>е<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> apu<70><75>
|
||||
cpunmif # 4 ;cpu<70>жϱ<D0B6>־
|
||||
cpuirqf # 4 ;cpu<70>жϱ<D0B6>־
|
||||
;------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
;// # 2 ;align
|
||||
|
||||
END
|
||||
@@ -1,17 +1,18 @@
|
||||
#include "main.h"
|
||||
#include "main.h"
|
||||
#include "nes_apu.h"
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
#include "nes_main.h"
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֲ<EFBFBD><D6B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ye781205<30><35>NESģ<53><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//ALIENTEK STM32F407<30><37><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//NES APU <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//NES APU <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD>@ALIENTEK
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̳:www.openedv.com
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:2014/7/1
|
||||
//<2F>汾<EFBFBD><E6B1BE>V1.0
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//<2F>汾<EFBFBD><E6B1BE>V1.0
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/* look up table madness */
|
||||
/* look up table madness */
|
||||
#define APU_OVERSAMPLE
|
||||
#define APU_VOLUME_DECAY(x) ((x) -= ((x) >> 7))
|
||||
//<2F><>Ҫ<EFBFBD>õ<EFBFBD><C3B5>Ļ<EFBFBD><C4BB><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4>뼰<EFBFBD><EBBCB0><EFBFBD><EFBFBD>
|
||||
@@ -27,7 +28,7 @@ static char noise_short_lut[APU_NOISE_93];//APU_NOISE_93 93
|
||||
/* vblank<6E><6B><EFBFBD>ȱ<EFBFBD><C8B1><EFBFBD><EFBFBD>ھ<EFBFBD><DABE>Ρ<EFBFBD><CEA1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ρ<EFBFBD><CEA1><EFBFBD><EFBFBD><EFBFBD> */
|
||||
static const u8 vbl_length[32] =
|
||||
{
|
||||
5, 127, 10, 1, 19, 2, 40, 3, 80, 4, 30, 5, 7, 6, 13, 7,
|
||||
5, 127, 10, 1, 19, 2, 40, 3, 80, 4, 30, 5, 7, 6, 13, 7,
|
||||
6, 8, 12, 9, 24, 10, 48, 11, 96, 12, 36, 13, 8, 14, 16, 15
|
||||
};
|
||||
|
||||
@@ -62,7 +63,7 @@ void apu_enqueue(apudata_t *d)
|
||||
{
|
||||
apu->queue[apu->q_head] = *d;
|
||||
|
||||
apu->q_head = (apu->q_head + 1) & APUQUEUE_MASK;
|
||||
apu->q_head = (apu->q_head + 1) & APUQUEUE_MASK;
|
||||
}
|
||||
|
||||
apudata_t *apu_dequeue(void)
|
||||
@@ -182,7 +183,7 @@ int apu_rectangle(rectangle_t *chan)
|
||||
{
|
||||
if(env_delay==0)break;//*******<2A>Ҽӵ<D2BC>*****************1943<34><33><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϸ<EFBFBD><CFB7>0
|
||||
env_phase += env_delay;
|
||||
|
||||
|
||||
if (holdnote)
|
||||
env_vol = (env_vol + 1) & 0x0F;
|
||||
else if (env_vol < 0x0F)
|
||||
@@ -195,7 +196,7 @@ int apu_rectangle(rectangle_t *chan)
|
||||
}
|
||||
|
||||
/* TODO: using a table of max frequencies is not technically
|
||||
** clean, but it is fast and (or should be) accurate
|
||||
** clean, but it is fast and (or should be) accurate
|
||||
*/
|
||||
if (chan->freq < 8 || (FALSE == chan->sweep_inc && chan->freq > chan->freq_limit))
|
||||
return APU_RECTANGLE_OUTPUT;
|
||||
@@ -365,7 +366,7 @@ int apu_noise(noise_t *chan)
|
||||
while (env_phase < 0)
|
||||
{
|
||||
env_phase += env_delay;
|
||||
|
||||
|
||||
if (holdnote)
|
||||
env_vol = (env_vol + 1) & 0x0F;
|
||||
else if (env_vol < 0x0F)
|
||||
@@ -381,7 +382,7 @@ int apu_noise(noise_t *chan)
|
||||
chan->phaseacc -= apu->cycle_rate; /* # of cycles per sample */
|
||||
if (chan->phaseacc >= 0)
|
||||
return APU_NOISE_OUTPUT;
|
||||
|
||||
|
||||
#ifdef APU_OVERSAMPLE
|
||||
num_times = total = 0;
|
||||
|
||||
@@ -393,7 +394,7 @@ int apu_noise(noise_t *chan)
|
||||
|
||||
while (chan->phaseacc < 0)
|
||||
{
|
||||
|
||||
|
||||
if(chan->freq==0)break;//*******<2A>Ҽӵ<D2BC>*****************<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϸ<EFBFBD><CFB7>0/////////////////////////
|
||||
chan->phaseacc += chan->freq;
|
||||
|
||||
@@ -490,13 +491,13 @@ int apu_dmc(dmc_t *chan)
|
||||
if (chan->dma_length)
|
||||
{
|
||||
chan->phaseacc -= apu->cycle_rate; /* # of cycles per sample */
|
||||
|
||||
|
||||
while (chan->phaseacc < 0)
|
||||
{
|
||||
chan->phaseacc += chan->freq;
|
||||
|
||||
|
||||
delta_bit = (chan->dma_length & 7) ^ 7;
|
||||
|
||||
|
||||
if (7 == delta_bit)
|
||||
{
|
||||
chan->cur_byte =K6502_Read(chan->address);//chan->cur_byte = nes6502_getbyte(chan->address);*********************
|
||||
@@ -539,7 +540,7 @@ int apu_dmc(dmc_t *chan)
|
||||
}
|
||||
}
|
||||
/* negative delta */
|
||||
else
|
||||
else
|
||||
{
|
||||
if (chan->regs[1] > 1)
|
||||
{
|
||||
@@ -555,7 +556,7 @@ int apu_dmc(dmc_t *chan)
|
||||
|
||||
|
||||
void apu_regwrite(u32 address, u8 value)
|
||||
{
|
||||
{
|
||||
int chan = (address & 4) ? 1 : 0;
|
||||
rectangle_t * rect = chan ? &(apu->rectangle[1]) : &(apu->rectangle[0]);
|
||||
|
||||
@@ -590,7 +591,7 @@ void apu_regwrite(u32 address, u8 value)
|
||||
apu->rectangle[chan].sweep_on = (value & 0x80) ? TRUE : FALSE;
|
||||
apu->rectangle[chan].sweep_shifts = value & 7;
|
||||
apu->rectangle[chan].sweep_delay = apu->decay_lut[(value >> 4) & 7];
|
||||
|
||||
|
||||
apu->rectangle[chan].sweep_inc = (value & 0x08) ? TRUE : FALSE;
|
||||
apu->rectangle[chan].freq_limit = freq_limit[value & 7];
|
||||
*/
|
||||
@@ -598,7 +599,7 @@ void apu_regwrite(u32 address, u8 value)
|
||||
rect->sweep_on = (value & 0x80) ? TRUE : FALSE;
|
||||
rect->sweep_shifts = value & 7;
|
||||
rect->sweep_delay = apu->decay_lut[(value >> 4) & 7];
|
||||
|
||||
|
||||
rect->sweep_inc = (value & 0x08) ? TRUE : FALSE;
|
||||
rect->freq_limit = freq_limit[value & 7];
|
||||
break;
|
||||
@@ -647,7 +648,7 @@ void apu_regwrite(u32 address, u8 value)
|
||||
triangle_t * tri = &(apu->triangle);
|
||||
tri->regs[0] = value;
|
||||
tri->holdnote = (value & 0x80) ? TRUE : FALSE;
|
||||
|
||||
|
||||
if (FALSE == tri->counter_started && tri->vbl_length)
|
||||
tri->linear_length = apu->trilength_lut[value & 0x7F];
|
||||
}
|
||||
@@ -668,16 +669,16 @@ void apu_regwrite(u32 address, u8 value)
|
||||
case APU_WRC3:
|
||||
#if 0
|
||||
apu->triangle.regs[2] = value;
|
||||
|
||||
/* this is somewhat of a hack. there appears to be some latency on
|
||||
** the Real Thing between when trireg0 is written to and when the
|
||||
** linear length counter actually begins its countdown. we want to
|
||||
** prevent the case where the program writes to the freq regs first,
|
||||
** then to reg 0, and the counter accidentally starts running because
|
||||
|
||||
/* this is somewhat of a hack. there appears to be some latency on
|
||||
** the Real Thing between when trireg0 is written to and when the
|
||||
** linear length counter actually begins its countdown. we want to
|
||||
** prevent the case where the program writes to the freq regs first,
|
||||
** then to reg 0, and the counter accidentally starts running because
|
||||
** of the sound queue's timestamp processing.
|
||||
**
|
||||
** set latency to a couple hundred cycles -- should be plenty of time
|
||||
** for the 6502 code to do a couple of table dereferences and load up
|
||||
** set latency to a couple hundred cycles -- should be plenty of time
|
||||
** for the 6502 code to do a couple of table dereferences and load up
|
||||
** the other triregs
|
||||
*/
|
||||
|
||||
@@ -693,7 +694,7 @@ void apu_regwrite(u32 address, u8 value)
|
||||
triangle_t * tri = &(apu->triangle);
|
||||
tri->regs[2] = value;
|
||||
tri->write_latency = (int) (228 / APU_FROM_FIXED(apu->cycle_rate));
|
||||
|
||||
|
||||
tri->freq = APU_TO_FIXED((((value & 7) << 8) + tri->regs[1]) + 1);
|
||||
tri->vbl_length = apu->vbl_lut[value >> 3];
|
||||
tri->counter_started = FALSE;
|
||||
@@ -742,7 +743,7 @@ void apu_regwrite(u32 address, u8 value)
|
||||
noise_t * noise = &(apu->noise);
|
||||
noise->regs[1] = value;
|
||||
noise->freq = APU_TO_FIXED(noise_freq[value & 0x0F]);
|
||||
|
||||
|
||||
#ifdef REALTIME_NOISE
|
||||
noise->xor_tap = (value & 0x80) ? 0x40: 0x02;
|
||||
#else /* !REALTIME_NOISE */
|
||||
@@ -768,7 +769,7 @@ void apu_regwrite(u32 address, u8 value)
|
||||
{
|
||||
noise_t * noise = &(apu->noise);
|
||||
noise->regs[2] = value;
|
||||
|
||||
|
||||
noise->vbl_length = apu->vbl_lut[value >> 3];
|
||||
noise->env_vol = 0; /* reset envelope */
|
||||
}
|
||||
@@ -792,12 +793,12 @@ void apu_regwrite(u32 address, u8 value)
|
||||
*/
|
||||
{
|
||||
dmc_t * dmc = &(apu->dmc);
|
||||
|
||||
|
||||
dmc->regs[0] = value;
|
||||
|
||||
|
||||
dmc->freq = APU_TO_FIXED(dmc_clocks[value & 0x0F]);
|
||||
dmc->looping = (value & 0x40) ? TRUE : FALSE;
|
||||
|
||||
|
||||
if (value & 0x80)
|
||||
dmc->irq_gen = TRUE;
|
||||
else
|
||||
@@ -902,9 +903,9 @@ void apu_regwrite(u32 address, u8 value)
|
||||
noise_t * noise = &(apu->noise);
|
||||
|
||||
dmc->enabled = (value & 0x10) ? TRUE : FALSE;
|
||||
|
||||
|
||||
apu->enable_reg = value;
|
||||
|
||||
|
||||
for (chan = 0; chan < 2; chan++)
|
||||
{
|
||||
if (value & (1 << chan))
|
||||
@@ -915,7 +916,7 @@ void apu_regwrite(u32 address, u8 value)
|
||||
apu->rectangle[chan].vbl_length = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (value & 0x04)
|
||||
tri->enabled = TRUE;
|
||||
else
|
||||
@@ -926,7 +927,7 @@ void apu_regwrite(u32 address, u8 value)
|
||||
tri->counter_started = FALSE;
|
||||
tri->write_latency = 0;
|
||||
}
|
||||
|
||||
|
||||
if (value & 0x08)
|
||||
noise->enabled = TRUE;
|
||||
else
|
||||
@@ -934,7 +935,7 @@ void apu_regwrite(u32 address, u8 value)
|
||||
noise->enabled = FALSE;
|
||||
noise->vbl_length = 0;
|
||||
}
|
||||
|
||||
|
||||
if (value & 0x10)
|
||||
{
|
||||
if (0 == dmc->dma_length)
|
||||
@@ -942,7 +943,7 @@ void apu_regwrite(u32 address, u8 value)
|
||||
}
|
||||
else
|
||||
dmc->dma_length = 0;
|
||||
|
||||
|
||||
dmc->irq_occurred = FALSE;
|
||||
}
|
||||
break;
|
||||
@@ -951,7 +952,7 @@ void apu_regwrite(u32 address, u8 value)
|
||||
case 0x4009:
|
||||
case 0x400D:
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
//DCR
|
||||
if(apu->ext)
|
||||
@@ -996,8 +997,8 @@ u8 Apu_Read4015(u32 address)//**************************************************
|
||||
if (apu->dmc.irq_occurred)
|
||||
value |= 0x80;
|
||||
|
||||
return value | 0x40;
|
||||
}
|
||||
return value | 0x40;
|
||||
}
|
||||
// return value;
|
||||
}
|
||||
void Apu_Write4015(u8 value,u32 address )
|
||||
@@ -1007,32 +1008,32 @@ void Apu_Write4015(u8 value,u32 address )
|
||||
d.timestamp = clocks; //d.timestamp = nes6502_getcycles(0);*********************
|
||||
d.address = address|0x4000;
|
||||
d.value = value;
|
||||
apu_enqueue(&d);
|
||||
apu_enqueue(&d);
|
||||
}
|
||||
|
||||
void Apu_Write(u8 value,u32 address )
|
||||
{
|
||||
apudata_t d;
|
||||
apudata_t d;
|
||||
d.timestamp = clocks; //d.timestamp = nes6502_getcycles(0);*********************
|
||||
d.address = address|0x4000;
|
||||
d.value = value;
|
||||
apu_enqueue(&d);
|
||||
}
|
||||
apu_enqueue(&d);
|
||||
}
|
||||
void apu_getpcmdata(void **data, int *num_samples, int *sample_bits)
|
||||
{
|
||||
*data = apu->buffer;
|
||||
*num_samples = apu->num_samples;
|
||||
*sample_bits = apu->sample_bits;
|
||||
}
|
||||
// _local_sample_size = 8
|
||||
// _local_sample_size = 8
|
||||
// apu_process(buf, buf_len/(_local_sample_size/8));
|
||||
void apu_process(u16 *buffer, int num_samples)
|
||||
{
|
||||
apudata_t *d;
|
||||
u32 elapsed_cycles;
|
||||
static int prev_sample = 0;
|
||||
int next_sample, accum;
|
||||
|
||||
int next_sample, accum;
|
||||
|
||||
/* grab it, keep it local for speed */
|
||||
elapsed_cycles = (u32) apu->elapsed_cycles;
|
||||
|
||||
@@ -1055,7 +1056,7 @@ void apu_process(u16 *buffer, int num_samples)
|
||||
u8 * mix_enable = apu->mix_enable;
|
||||
|
||||
/* bleh */
|
||||
apu->buffer = buffer;
|
||||
apu->buffer = buffer;
|
||||
|
||||
while (num_samples--)
|
||||
{
|
||||
@@ -1097,10 +1098,10 @@ void apu_process(u16 *buffer, int num_samples)
|
||||
/* prevent clipping */
|
||||
if (accum > 0x7FFF)accum = 0x7FFF;
|
||||
else if (accum < -0x8000)accum = -0x8000;
|
||||
|
||||
|
||||
*buffer++=(u16)accum;//<2F><>Ƶ<EFBFBD><C6B5><EFBFBD>ݴ<EFBFBD><DDB4>뻺<EFBFBD><EBBBBA>
|
||||
}
|
||||
}
|
||||
}
|
||||
/* resync cycle counter <20><><EFBFBD><EFBFBD>ͬ<EFBFBD><CDAC>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
|
||||
apu->elapsed_cycles =clocks; // apu->elapsed_cycles = nes6502_getcycles(0);//*****************************************************************
|
||||
}
|
||||
@@ -1163,12 +1164,12 @@ void apu_setparams(int sample_rate, int refresh_rate, int frag_size, int sample_
|
||||
apu->ext->paramschanged();
|
||||
}
|
||||
/*Ӳ<><D3B2><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD> */
|
||||
// _local_sample_rate = 11025; _local_sample_size = 8;
|
||||
// _local_sample_rate = 11025; _local_sample_size = 8;
|
||||
// apu_create(_local_sample_rate, 60, 0, _local_sample_size);
|
||||
//void apu_create(int sample_rate, int refresh_rate, int frag_size, int sample_bits)
|
||||
void apu_init(void)
|
||||
void apu_init(void)
|
||||
{
|
||||
int channel;
|
||||
int channel;
|
||||
mymemset(apu, 0, sizeof(apu_t));
|
||||
/* set the stupid flag to tell difference between two rectangles */
|
||||
apu->rectangle[0].sweep_complement = TRUE;
|
||||
@@ -1178,17 +1179,17 @@ void apu_init(void)
|
||||
apu_setparams(APU_SAMPLE_RATE,60,0,16);//APU_SAMPLE_RATEΪ22050Hz //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
apu_reset();
|
||||
for(channel=0;channel<6;channel++)apu_setchan(channel,TRUE);
|
||||
apu->filter_type=APU_FILTER_LOWPASS; //<2F><><EFBFBD><EFBFBD>ɸѡ<C9B8><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
apu->filter_type=APU_FILTER_LOWPASS; //<2F><><EFBFBD><EFBFBD>ɸѡ<C9B8><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
}
|
||||
//apu<70><75><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
void apu_soundoutput(void)
|
||||
{
|
||||
void apu_soundoutput(void)
|
||||
{
|
||||
u16 i;
|
||||
apu_process(wave_buffers,APU_PCMBUF_SIZE);
|
||||
for(i=0;i<30;i++)if(wave_buffers[i]!=wave_buffers[i+1])break;//<2F>ж<EFBFBD>ǰ30<33><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C>Dz<EFBFBD><C7B2>Ƕ<EFBFBD><C7B6><EFBFBD><EFBFBD><EFBFBD>?
|
||||
if(i==30&&wave_buffers[i])//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C>Ҳ<EFBFBD><D2B2><EFBFBD><EFBFBD><EFBFBD>0
|
||||
{
|
||||
for(i=0;i<APU_PCMBUF_SIZE;i++)wave_buffers[i]=0;//<2F><><EFBFBD><EFBFBD>ͣ״̬<D7B4><CCAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ظ<EFBFBD><D8B8><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD>,ֱ<><D6B1><EFBFBD><EFBFBD>Ϊ0.<2E>Ӷ<EFBFBD><D3B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
|
||||
for(i=0;i<APU_PCMBUF_SIZE;i++)wave_buffers[i]=0;//<2F><><EFBFBD><EFBFBD>ͣ״̬<D7B4><CCAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ظ<EFBFBD><D8B8><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD>,ֱ<><D6B1><EFBFBD><EFBFBD>Ϊ0.<2E>Ӷ<EFBFBD><D3B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
|
||||
}
|
||||
clocks=0;
|
||||
nes_apu_fill_buffer(0,wave_buffers);
|
||||
|
||||
@@ -22,7 +22,7 @@ CFLAG=[
|
||||
'-mthumb',
|
||||
'-mfpu=fpv4-sp-d16',
|
||||
'-mfloat-abi=hard',
|
||||
'-Og',
|
||||
'-O3',
|
||||
'-Wall',
|
||||
'-fdata-sections',
|
||||
'-ffunction-sections',
|
||||
@@ -347,7 +347,7 @@ def main():
|
||||
if build_target(SRC):
|
||||
os.system(f"{OBJCPY} -O binary -S {OUTPUT}/{TARGET}.elf {OUTPUT}/{TARGET}.bin")
|
||||
os.system(f"{OBJCPY} -O ihex {OUTPUT}/{TARGET}.elf {OUTPUT}/{TARGET}.hex")
|
||||
os.system(f"{OBJDUMP} -d {OUTPUT}/{TARGET}.elf > {OUTPUT}/{TARGET}.lst")
|
||||
os.system(f"{OBJDUMP} -D {OUTPUT}/{TARGET}.elf > {OUTPUT}/{TARGET}.lst")
|
||||
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user