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设置usb时钟

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andy
2025-09-24 00:02:37 +08:00
parent 316b2ab330
commit d1b4de66b7
6 changed files with 720 additions and 707 deletions
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2
Project/Src/MY/stm32f4xx_it.c
View File

@@ -195,7 +195,6 @@ void OTG_HS_EP1_OUT_IRQHandler(void)
#endif
#if PKG_TINYUSB_DEVICE_ENABLE
void OTG_FS_IRQHandler(void) {
tusb_int_handler(0, true);
}
@@ -204,7 +203,6 @@ void OTG_HS_IRQHandler(void) {
tusb_int_handler(1, true);
}
#endif
#else

484
Project/Src/STM32/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
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File diff suppressed because it is too large Load Diff

171
Project/Src/STM32/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h
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@@ -16,8 +16,8 @@
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
@@ -42,7 +42,7 @@
/** @addtogroup RCC
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
typedef struct
@@ -51,6 +51,7 @@ typedef struct
uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
uint32_t USBCLK_Frequency;
}RCC_ClocksTypeDef;
/* Exported constants --------------------------------------------------------*/
@@ -58,8 +59,8 @@ typedef struct
/** @defgroup RCC_Exported_Constants
* @{
*/
/** @defgroup RCC_HSE_configuration
/** @defgroup RCC_HSE_configuration
* @{
*/
#define RCC_HSE_OFF ((uint8_t)0x00)
@@ -69,7 +70,7 @@ typedef struct
((HSE) == RCC_HSE_Bypass))
/**
* @}
*/
*/
/** @defgroup RCC_LSE_Dual_Mode_Selection
* @{
@@ -97,7 +98,7 @@ typedef struct
* @}
*/
/** @defgroup RCC_PLL_Clock_Source
/** @defgroup RCC_PLL_Clock_Source
* @{
*/
#define RCC_PLLSource_HSI ((uint32_t)0x00000000)
@@ -116,7 +117,7 @@ typedef struct
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#if defined(STM32F446xx)
#if defined(STM32F446xx)
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
#elif defined(STM32F412xG) || defined(STM32F413_423xx)
@@ -128,7 +129,7 @@ typedef struct
#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
#endif /* STM32F446xx || STM32F469_479xx */
#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
@@ -139,9 +140,9 @@ typedef struct
#endif /* STM32F413_423xx */
/**
* @}
*/
/** @defgroup RCC_System_Clock_Source
*/
/** @defgroup RCC_System_Clock_Source
* @{
*/
@@ -155,7 +156,7 @@ typedef struct
((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \
((SOURCE) == RCC_SYSCLKSource_PLLRCLK))
/* Add legacy definition */
#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK
#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK
#endif /* STM32F446xx */
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
@@ -165,11 +166,11 @@ typedef struct
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
((SOURCE) == RCC_SYSCLKSource_HSE) || \
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
/**
* @}
*/
*/
/** @defgroup RCC_AHB_Clock_Source
* @{
*/
@@ -189,8 +190,8 @@ typedef struct
((HCLK) == RCC_SYSCLK_Div512))
/**
* @}
*/
*/
/** @defgroup RCC_APB1_APB2_Clock_Source
* @{
*/
@@ -204,9 +205,9 @@ typedef struct
((PCLK) == RCC_HCLK_Div16))
/**
* @}
*/
/** @defgroup RCC_Interrupt_Source
*/
/** @defgroup RCC_Interrupt_Source
* @{
*/
#define RCC_IT_LSIRDY ((uint8_t)0x01)
@@ -214,7 +215,7 @@ typedef struct
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
#define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
#define RCC_IT_CSS ((uint8_t)0x80)
@@ -227,9 +228,9 @@ typedef struct
/**
* @}
*/
/** @defgroup RCC_LSE_Configuration
*/
/** @defgroup RCC_LSE_Configuration
* @{
*/
#define RCC_LSE_OFF ((uint8_t)0x00)
@@ -239,8 +240,8 @@ typedef struct
((LSE) == RCC_LSE_Bypass))
/**
* @}
*/
*/
/** @defgroup RCC_RTC_Clock_Source
* @{
*/
@@ -310,7 +311,7 @@ typedef struct
((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
/**
* @}
*/
*/
#if defined(STM32F410xx) || defined(STM32F413_423xx)
/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
@@ -338,7 +339,7 @@ typedef struct
#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) || ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) || \
((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
/**
* @}
*/
@@ -355,7 +356,7 @@ typedef struct
#define RCC_I2SCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_I2S1SRC_0 | RCC_DCKCFGR_I2S1SRC_1)
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \
((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE))
((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE))
/**
* @}
*/
@@ -365,11 +366,11 @@ typedef struct
*/
#define RCC_I2SBus_APB1 ((uint8_t)0x00)
#define RCC_I2SBus_APB2 ((uint8_t)0x01)
#define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2))
#define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2))
/**
* @}
*/
#if defined(STM32F446xx)
#if defined(STM32F446xx)
/** @defgroup RCC_SAI_Clock_Source
* @{
*/
@@ -379,22 +380,22 @@ typedef struct
#define RCC_SAICLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1SRC_0 | RCC_DCKCFGR_SAI1SRC_1)
#define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \
((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE))
((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE))
/**
* @}
*/
*/
/** @defgroup RCC_SAI_Instance
* @{
*/
#define RCC_SAIInstance_SAI1 ((uint8_t)0x00)
#define RCC_SAIInstance_SAI2 ((uint8_t)0x01)
#define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2))
#define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2))
/**
* @}
*/
#endif /* STM32F446xx */
#if defined(STM32F413_423xx)
#if defined(STM32F413_423xx)
/** @defgroup RCC_SAI_BlockA_Clock_Source
* @{
@@ -433,10 +434,10 @@ typedef struct
#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
/**
* @}
*/
*/
/** @defgroup RCC_SAI_BlockA_Clock_Source
* @{
@@ -450,7 +451,7 @@ typedef struct
((SOURCE) == RCC_SAIACLKSource_Ext))
/**
* @}
*/
*/
/** @defgroup RCC_SAI_BlockB_Clock_Source
* @{
@@ -464,7 +465,7 @@ typedef struct
((SOURCE) == RCC_SAIBCLKSource_Ext))
/**
* @}
*/
*/
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
/** @defgroup RCC_TIM_PRescaler_Selection
@@ -515,7 +516,7 @@ typedef struct
#endif /* STM32F446xx || STM32F469_479xx */
#if defined(STM32F412xG) || defined(STM32F413_423xx)
#define RCC_CK48CLKSOURCE_PLLQ ((uint8_t)0x00)
#define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG and STM32F413_423xx Devices */
#define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG and STM32F413_423xx Devices */
#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLQ) || \
((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLI2SQ))
#endif /* STM32F412xG || STM32F413_423xx */
@@ -524,7 +525,7 @@ typedef struct
*/
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
#if defined(STM32F446xx)
#if defined(STM32F446xx)
/** @defgroup RCC_SPDIFRX_Clock_Source_Selection
* @{
*/
@@ -549,7 +550,7 @@ typedef struct
/** @defgroup RCC_AHB1_ClockGating
* @{
*/
*/
#define RCC_AHB1ClockGating_APB1Bridge ((uint32_t)0x00000001)
#define RCC_AHB1ClockGating_APB2Bridge ((uint32_t)0x00000002)
#define RCC_AHB1ClockGating_CM4DBG ((uint32_t)0x00000004)
@@ -572,7 +573,7 @@ typedef struct
#define RCC_FMPI2C1CLKSource_APB1 ((uint32_t)0x00)
#define RCC_FMPI2C1CLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
#define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
#define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \
((SOURCE) == RCC_FMPI2C1CLKSource_HSI))
/**
@@ -622,9 +623,9 @@ typedef struct
#endif /* STM32F413_423xx */
#endif /* STM32F412xG || STM32F413_423xx */
/** @defgroup RCC_AHB1_Peripherals
/** @defgroup RCC_AHB1_Peripherals
* @{
*/
*/
#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
@@ -633,7 +634,7 @@ typedef struct
#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)
#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)
#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
@@ -661,26 +662,26 @@ typedef struct
/**
* @}
*/
/** @defgroup RCC_AHB2_Peripherals
*/
/** @defgroup RCC_AHB2_Peripherals
* @{
*/
*/
#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup RCC_AHB3_Peripherals
*/
/** @defgroup RCC_AHB3_Peripherals
* @{
*/
*/
#if defined(STM32F40_41xxx)
#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
@@ -691,7 +692,7 @@ typedef struct
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
#endif /* STM32F427_437xx || STM32F429_439xx */
#if defined(STM32F446xx) || defined(STM32F469_479xx)
#if defined(STM32F446xx) || defined(STM32F469_479xx)
#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
@@ -705,11 +706,11 @@ typedef struct
/**
* @}
*/
/** @defgroup RCC_APB1_Peripherals
*/
/** @defgroup RCC_APB1_Peripherals
* @{
*/
*/
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
@@ -727,7 +728,7 @@ typedef struct
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
#if defined(STM32F446xx)
#define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000)
#endif /* STM32F446xx */
#endif /* STM32F446xx */
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
@@ -737,7 +738,7 @@ typedef struct
#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
#define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000)
#endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/
#endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#if defined(STM32F413_423xx)
@@ -745,7 +746,7 @@ typedef struct
#endif /* STM32F413_423xx */
#if defined(STM32F446xx)
#define RCC_APB1Periph_CEC ((uint32_t)0x08000000)
#endif /* STM32F446xx */
#endif /* STM32F446xx */
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
@@ -753,11 +754,11 @@ typedef struct
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup RCC_APB2_Peripherals
*/
/** @defgroup RCC_APB2_Peripherals
* @{
*/
*/
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
@@ -801,7 +802,7 @@ typedef struct
/**
* @}
*/
*/
/** @defgroup RCC_MCO1_Clock_Source_Prescaler
* @{
@@ -817,14 +818,14 @@ typedef struct
#define RCC_MCO1Div_5 ((uint32_t)0x07000000)
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
((DIV) == RCC_MCO1Div_5))
((DIV) == RCC_MCO1Div_5))
/**
* @}
*/
*/
/** @defgroup RCC_MCO2_Clock_Source_Prescaler
* @{
*/
@@ -839,15 +840,15 @@ typedef struct
#define RCC_MCO2Div_5 ((uint32_t)0x38000000)
#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
((DIV) == RCC_MCO2Div_5))
((DIV) == RCC_MCO2Div_5))
/**
* @}
*/
/** @defgroup RCC_Flag
*/
/** @defgroup RCC_Flag
* @{
*/
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
@@ -876,14 +877,14 @@ typedef struct
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
/**
* @}
*/
*/
/**
* @}
*/
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the RCC clock configuration to the default reset state */
void RCC_DeInit(void);
@@ -949,7 +950,7 @@ void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource);
#if defined(STM32F446xx)
void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource);
@@ -1057,10 +1058,10 @@ void RCC_ClearITPendingBit(uint8_t RCC_IT);
/**
* @}
*/
*/
/**
* @}
*/
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

759
Project/Src/STM32/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c
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File diff suppressed because it is too large Load Diff

6
Project/Src/rt-thread/board.c
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@@ -102,8 +102,10 @@ const libc_device_file *g_usart;
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӣ<EFBFBD>25m<35><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA>֤usbΪ48m<38><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ168m
void reconfig_clock(void) {
RCC_PLLConfig(RCC_PLLSource_HSE, 25, 336, 2, 7);
SystemCoreClock = 168000000;
RCC_ClocksTypeDef rcc = {0};
// RCC_PLLConfig(RCC_PLLSource_HSE, 25, 336, 2, 7);
RCC_GetClocksFreq(&rcc);
SystemCoreClock = rcc.SYSCLK_Frequency;
}
/**

5
Project/make.py
View File

@@ -41,8 +41,9 @@ DEF=[
'-D__packed=__attribute__((__packed__))',
'-D__weak=__attribute__((weak))',
'-D__RTTHREAD__',
'-DSOC_SERIES_STM32F4',
'-DPKG_TINYUSB_DEVICE_ENABLE',
# 使用usb时打开这个宏 系统时钟会被设置为168MHz USB时钟为48MHz
# 如果不打开这个宏 系统时钟会被设置为180MHz USB会通信异常
'-D__USB_USB__',
]
INC=[