From d1b4de66b7fcaa4e9c76d72eeba95a3797e975d2 Mon Sep 17 00:00:00 2001 From: andy <1414772332@qq.com> Date: Wed, 24 Sep 2025 00:02:37 +0800 Subject: [PATCH] =?UTF-8?q?=E8=AE=BE=E7=BD=AEusb=E6=97=B6=E9=92=9F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Project/Src/MY/stm32f4xx_it.c | 2 - .../Source/Templates/system_stm32f4xx.c | 484 +++++------ .../inc/stm32f4xx_rcc.h | 171 ++-- .../src/stm32f4xx_rcc.c | 759 +++++++++--------- Project/Src/rt-thread/board.c | 6 +- Project/make.py | 5 +- 6 files changed, 720 insertions(+), 707 deletions(-) diff --git a/Project/Src/MY/stm32f4xx_it.c b/Project/Src/MY/stm32f4xx_it.c index accc161..9b3bb1e 100644 --- a/Project/Src/MY/stm32f4xx_it.c +++ b/Project/Src/MY/stm32f4xx_it.c @@ -195,7 +195,6 @@ void OTG_HS_EP1_OUT_IRQHandler(void) #endif -#if PKG_TINYUSB_DEVICE_ENABLE void OTG_FS_IRQHandler(void) { tusb_int_handler(0, true); } @@ -204,7 +203,6 @@ void OTG_HS_IRQHandler(void) { tusb_int_handler(1, true); } -#endif #else diff --git a/Project/Src/STM32/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c b/Project/Src/STM32/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c index c837ca1..02b4582 100644 --- a/Project/Src/STM32/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c +++ b/Project/Src/STM32/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c @@ -6,20 +6,20 @@ * @date 09-November-2016 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * This file contains the system clock configuration for STM32F4xx devices. - * - * 1. This file provides two functions and one global variable to be called from + * + * 1. This file provides two functions and one global variable to be called from * user application: * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f4xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick + * by the user application to setup the SysTick * timer or configure other parameters. - * + * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. @@ -29,7 +29,7 @@ * configure the system clock before to branch to main program. * * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can + * function will do nothing and HSI still used as system clock source. User can * add some code to deal with this issue inside the SetSysClock() function. * * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define @@ -293,8 +293,8 @@ * * http://www.st.com/software_license_agreement_liberty_v2 * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. @@ -308,8 +308,8 @@ /** @addtogroup stm32f4xx_system * @{ - */ - + */ + /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ @@ -334,34 +334,34 @@ /************************* Miscellaneous Configuration ************************/ /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted - on STM324xG_EVAL/STM324x7I_EVAL/STM324x9I_EVAL boards as data memory */ + on STM324xG_EVAL/STM324x7I_EVAL/STM324x9I_EVAL boards as data memory */ #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) || defined(STM32F413_423xx) /* #define DATA_IN_ExtSRAM */ #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F469_479xx || STM32F413_423xx */ #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) /* #define DATA_IN_ExtSDRAM */ -#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ +#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ #if defined(STM32F410xx) || defined(STM32F411xE) /*!< Uncomment the following line if you need to clock the STM32F410xx/STM32F411xE by HSE Bypass through STLINK MCO pin of STM32F103 microcontroller. The frequency cannot be changed - and is fixed at 8 MHz. + and is fixed at 8 MHz. Hardware configuration needed for Nucleo Board: - SB54, SB55 OFF - R35 removed - SB16, SB50 ON */ + ? SB54, SB55 OFF + ? R35 removed + ? SB16, SB50 ON */ /* #define USE_HSE_BYPASS */ -#if defined(USE_HSE_BYPASS) +#if defined(USE_HSE_BYPASS) #define HSE_BYPASS_INPUT_FREQUENCY 8000000 -#endif /* USE_HSE_BYPASS */ +#endif /* USE_HSE_BYPASS */ #endif /* STM32F410xx || STM32F411xE */ - + /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ /******************************************************************************/ @@ -373,12 +373,12 @@ #define PLL_M 8 #elif defined (STM32F410xx) || defined (STM32F411xE) #if defined(USE_HSE_BYPASS) - #define PLL_M 8 + #define PLL_M 8 #else /* !USE_HSE_BYPASS */ #define PLL_M 16 #endif /* USE_HSE_BYPASS */ #else -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */ +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */ /* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ #define PLL_Q 7 @@ -389,10 +389,14 @@ #elif defined(STM32F412xG) || defined(STM32F413_423xx) #define PLL_R 2 #else -#endif /* STM32F446xx */ +#endif /* STM32F446xx */ #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) +#ifdef __USB_USB__ +#define PLL_N 336 +#else /* !__USB_USB__ */ #define PLL_N 360 +#endif /* SYSCLK = PLL_VCO / PLL_P */ #define PLL_P 2 #endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ @@ -412,7 +416,7 @@ #if defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx) #define PLL_N 400 /* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 4 +#define PLL_P 4 #endif /* STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx */ /******************************************************************************/ @@ -438,7 +442,11 @@ #endif /* STM32F40_41xxx */ #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) +#ifdef __USB_USB__ + uint32_t SystemCoreClock = 168000000; +#else /* !__USB_USB__ */ uint32_t SystemCoreClock = 180000000; +#endif #endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ #if defined(STM32F401xx) @@ -462,7 +470,7 @@ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9} static void SetSysClock(void); #if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM) -static void SystemInit_ExtMemCtl(void); +static void SystemInit_ExtMemCtl(void); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ /** @@ -475,7 +483,7 @@ static void SystemInit_ExtMemCtl(void); /** * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the + * Initialize the Embedded Flash Interface, the PLL and update the * SystemFrequency variable. * @param None * @retval None @@ -506,10 +514,10 @@ void SystemInit(void) RCC->CIR = 0x00000000; #if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM) - SystemInit_ExtMemCtl(); + SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ - - /* Configure the System clock source, PLL Multiplier and Divider factors, + + /* Configure the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings ----------------------------------*/ SetSysClock(); @@ -526,41 +534,41 @@ void SystemInit(void) * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. - * + * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: - * + * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * + * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * + * * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * + * in voltage and temperature. + * * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value * 25 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. - * + * * - The result of this function could be not correct when using fractional * value for HSE crystal. - * + * * @param None * @retval None */ void SystemCoreClockUpdate(void) { uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) +#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) uint32_t pllr = 2; #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ /* Get SYSCLK source -------------------------------------------------------*/ @@ -577,10 +585,10 @@ void SystemCoreClockUpdate(void) case 0x08: /* PLL P used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N SYSCLK = PLL_VCO / PLL_P - */ + */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - + #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) if (pllsource != 0) { @@ -598,23 +606,23 @@ void SystemCoreClockUpdate(void) { /* HSE used as PLL clock source */ pllvco = (HSE_BYPASS_INPUT_FREQUENCY / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } -#else + } +#else if (pllsource == 0) { /* HSI used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } -#endif /* USE_HSE_BYPASS */ -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ + } +#endif /* USE_HSE_BYPASS */ +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; + SystemCoreClock = pllvco/pllp; break; -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) +#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) case 0x0C: /* PLL R used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N SYSCLK = PLL_VCO / PLL_R - */ + */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; if (pllsource != 0) @@ -625,11 +633,11 @@ void SystemCoreClockUpdate(void) else { /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } - + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2; - SystemCoreClock = pllvco/pllr; + SystemCoreClock = pllvco/pllr; break; #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ default: @@ -644,10 +652,10 @@ void SystemCoreClockUpdate(void) } /** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings - * @Note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). * @param None * @retval None */ @@ -658,10 +666,10 @@ static void SetSysClock(void) /* PLL (clocked by HSE) used as System clock source */ /******************************************************************************/ __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - + /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); - + /* Wait till HSE is ready and if Time out is reached exit */ do { @@ -687,10 +695,10 @@ static void SetSysClock(void) /* HCLK = SYSCLK / 1*/ RCC->CFGR |= RCC_CFGR_HPRE_DIV1; -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx) +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx) /* PCLK2 = HCLK / 2*/ RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - + /* PCLK1 = HCLK / 4*/ RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F412xG || STM32F446xx || STM32F469_479xx */ @@ -698,12 +706,12 @@ static void SetSysClock(void) #if defined(STM32F401xx) || defined(STM32F413_423xx) /* PCLK2 = HCLK / 1*/ RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; - + /* PCLK1 = HCLK / 2*/ RCC->CFGR |= RCC_CFGR_PPRE1_DIV2; #endif /* STM32F401xx || STM32F413_423xx */ -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F469_479xx) +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F469_479xx) /* Configure the main PLL */ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); @@ -713,8 +721,8 @@ static void SetSysClock(void) /* Configure the main PLL */ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) | (PLL_R << 28); -#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ - +#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ + /* Enable the main PLL */ RCC->CR |= RCC_CR_PLLON; @@ -722,7 +730,7 @@ static void SetSysClock(void) while((RCC->CR & RCC_CR_PLLRDY) == 0) { } - + #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ PWR->CR |= PWR_CR_ODEN; @@ -732,17 +740,17 @@ static void SetSysClock(void) PWR->CR |= PWR_CR_ODSWEN; while((PWR->CSR & PWR_CSR_ODSWRDY) == 0) { - } + } /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; #endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ -#if defined(STM32F40_41xxx) || defined(STM32F412xG) +#if defined(STM32F40_41xxx) || defined(STM32F412xG) /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; #endif /* STM32F40_41xxx || STM32F412xG */ -#if defined(STM32F413_423xx) +#if defined(STM32F413_423xx) /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS; #endif /* STM32F413_423xx */ @@ -766,15 +774,15 @@ static void SetSysClock(void) configuration. User can add here some code to deal with this error */ } #elif defined(STM32F410xx) || defined(STM32F411xE) -#if defined(USE_HSE_BYPASS) +#if defined(USE_HSE_BYPASS) /******************************************************************************/ /* PLL (clocked by HSE) used as System clock source */ /******************************************************************************/ __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - + /* Enable HSE and HSE BYPASS */ RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP); - + /* Wait till HSE is ready and if Time out is reached exit */ do { @@ -802,14 +810,14 @@ static void SetSysClock(void) /* PCLK2 = HCLK / 2*/ RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; - + /* PCLK1 = HCLK / 4*/ RCC->CFGR |= RCC_CFGR_PPRE1_DIV2; /* Configure the main PLL */ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); - + /* Enable the main PLL */ RCC->CR |= RCC_CR_PLLON; @@ -838,40 +846,40 @@ static void SetSysClock(void) /* Select regulator voltage output Scale 1 mode */ RCC->APB1ENR |= RCC_APB1ENR_PWREN; PWR->CR |= PWR_CR_VOS; - + /* HCLK = SYSCLK / 1*/ RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - + /* PCLK2 = HCLK / 2*/ RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; - + /* PCLK1 = HCLK / 4*/ RCC->CFGR |= RCC_CFGR_PPRE1_DIV2; - + /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (PLL_Q << 24); - + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (PLL_Q << 24); + /* Enable the main PLL */ RCC->CR |= RCC_CR_PLLON; - + /* Wait till the main PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { } - + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS; - + /* Select the main PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= RCC_CFGR_SW_PLL; - + /* Wait till the main PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); { } -#endif /* USE_HSE_BYPASS */ -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */ +#endif /* USE_HSE_BYPASS */ +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */ } #if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ @@ -896,79 +904,79 @@ void SystemInit_ExtMemCtl(void) /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); - + /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x00CCC0CC; GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ + /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ + /* Configure PDx pins speed to 100 MHz */ GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ + /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ + /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00CC0CC; GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ + /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ + /* Configure PEx pins speed to 100 MHz */ GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ + /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ + /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; - + /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0xCCCCCCCC; GPIOF->AFR[1] = 0xCCCCCCCC; - /* Configure PFx pins in Alternate function mode */ + /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ + /* Configure PFx pins speed to 50 MHz */ GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ + /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ + /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0xCCCCCCCC; GPIOG->AFR[1] = 0xCCCCCCCC; - /* Configure PGx pins in Alternate function mode */ + /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0xAAAAAAAA; - /* Configure PGx pins speed to 50 MHz */ + /* Configure PGx pins speed to 50 MHz */ GPIOG->OSPEEDR = 0xAAAAAAAA; - /* Configure PGx pins Output type to push-pull */ + /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ + /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; - + /* Connect PHx pins to FMC Alternate function */ GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ + /* Configure PHx pins in Alternate function mode */ GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ + /* Configure PHx pins speed to 50 MHz */ GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ + /* Configure PHx pins Output type to push-pull */ GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ + /* No pull-up, pull-down for PHx pins */ GPIOH->PUPDR = 0x00000000; - + /* Connect PIx pins to FMC Alternate function */ GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ + /* Configure PIx pins in Alternate function mode */ GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ + /* Configure PIx pins speed to 50 MHz */ GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ + /* Configure PIx pins Output type to push-pull */ GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ + /* No pull-up, pull-down for PIx pins */ GPIOI->PUPDR = 0x00000000; - + /*-- FMC Configuration -------------------------------------------------------*/ /* Enable the FMC interface clock */ RCC->AHB3ENR |= 0x00000001; @@ -976,50 +984,50 @@ void SystemInit_ExtMemCtl(void) tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); FMC_Bank5_6->SDCR[0] = 0x000019E4; - FMC_Bank5_6->SDTR[0] = 0x01115351; - + FMC_Bank5_6->SDTR[0] = 0x01115351; + /* SDRAM initialization sequence */ /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Delay */ for (index = 0; index<1000; index++); - + /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; + FMC_Bank5_6->SDCMR = 0x00000012; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* Auto refresh command */ FMC_Bank5_6->SDCMR = 0x00000073; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* MRD register program */ FMC_Bank5_6->SDCMR = 0x00046014; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + /* Set refresh count */ tmpreg = FMC_Bank5_6->SDRTR; FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); - + /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; + tmpreg = FMC_Bank5_6->SDCR[0]; FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) @@ -1027,7 +1035,7 @@ void SystemInit_ExtMemCtl(void) FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #if defined(STM32F469xx) || defined(STM32F479xx) /* Configure and enable Bank1_SRAM2 */ FMC_Bank1->BTCR[2] = 0x00001091; @@ -1035,16 +1043,16 @@ void SystemInit_ExtMemCtl(void) FMC_Bank1E->BWTR[2] = 0x0fffffff; #endif /* STM32F469xx || STM32F479xx */ - (void)(tmp); + (void)(tmp); } #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #elif defined (DATA_IN_ExtSRAM) /** - * @brief Setup the external memory controller. Called in startup_stm32f4xx.s + * @brief Setup the external memory controller. Called in startup_stm32f4xx.s * before jump to __main * @param None * @retval None - */ + */ /** * @brief Setup the external memory controller. * Called in startup_stm32f4xx.s before jump to main. @@ -1060,16 +1068,16 @@ void SystemInit_ExtMemCtl(void) +-------------------+--------------------+------------------+--------------+ + SRAM pins assignment + +-------------------+--------------------+------------------+--------------+ - | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | - | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | - | PD4 <-> FMC_NOE | PE3 <-> FMC_A19 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 | - | PD5 <-> FMC_NWE | PE4 <-> FMC_A20 | PF3 <-> FMC_A3 | PG3 <-> FMC_A13 | - | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF4 <-> FMC_A4 | PG4 <-> FMC_A14 | - | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF5 <-> FMC_A5 | PG5 <-> FMC_A15 | - | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 | + | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | + | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | + | PD4 <-> FMC_NOE | PE3 <-> FMC_A19 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 | + | PD5 <-> FMC_NWE | PE4 <-> FMC_A20 | PF3 <-> FMC_A3 | PG3 <-> FMC_A13 | + | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF4 <-> FMC_A4 | PG4 <-> FMC_A14 | + | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF5 <-> FMC_A5 | PG5 <-> FMC_A15 | + | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 | | PD11 <-> FMC_A16 | PE10 <-> FMC_D7 | PF13 <-> FMC_A7 |-----------------+ - | PD12 <-> FMC_A17 | PE11 <-> FMC_D8 | PF14 <-> FMC_A8 | - | PD13 <-> FMC_A18 | PE12 <-> FMC_D9 | PF15 <-> FMC_A9 | + | PD12 <-> FMC_A17 | PE11 <-> FMC_D8 | PF14 <-> FMC_A8 | + | PD13 <-> FMC_A18 | PE12 <-> FMC_D9 | PF15 <-> FMC_A9 | | PD14 <-> FMC_D0 | PE13 <-> FMC_D10 |-----------------+ | PD15 <-> FMC_D1 | PE14 <-> FMC_D11 | | | PE15 <-> FMC_D12 | @@ -1077,65 +1085,65 @@ void SystemInit_ExtMemCtl(void) */ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ RCC->AHB1ENR |= 0x00000078; - + /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x00cc00cc; GPIOD->AFR[1] = 0xcccccccc; - /* Configure PDx pins in Alternate function mode */ + /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xaaaa0a0a; - /* Configure PDx pins speed to 100 MHz */ + /* Configure PDx pins speed to 100 MHz */ GPIOD->OSPEEDR = 0xffff0f0f; - /* Configure PDx pins Output type to push-pull */ + /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ + /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xcccccccc; GPIOE->AFR[1] = 0xcccccccc; - /* Configure PEx pins in Alternate function mode */ + /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xaaaaaaaa; - /* Configure PEx pins speed to 100 MHz */ + /* Configure PEx pins speed to 100 MHz */ GPIOE->OSPEEDR = 0xffffffff; - /* Configure PEx pins Output type to push-pull */ + /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ + /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0x00cccccc; GPIOF->AFR[1] = 0xcccc0000; - /* Configure PFx pins in Alternate function mode */ + /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xaa000aaa; - /* Configure PFx pins speed to 100 MHz */ + /* Configure PFx pins speed to 100 MHz */ GPIOF->OSPEEDR = 0xff000fff; - /* Configure PFx pins Output type to push-pull */ + /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ + /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0x00cccccc; GPIOG->AFR[1] = 0x000000c0; - /* Configure PGx pins in Alternate function mode */ + /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0x00080aaa; - /* Configure PGx pins speed to 100 MHz */ + /* Configure PGx pins speed to 100 MHz */ GPIOG->OSPEEDR = 0x000c0fff; - /* Configure PGx pins Output type to push-pull */ + /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ + /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; - + /*-- FMC Configuration ------------------------------------------------------*/ /* Enable the FMC/FSMC interface clock */ RCC->AHB3ENR |= 0x00000001; - + #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) /* Configure and enable Bank1_SRAM2 */ FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ +#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ #if defined(STM32F40_41xxx) /* Configure and enable Bank1_SRAM2 */ @@ -1146,7 +1154,7 @@ void SystemInit_ExtMemCtl(void) /* Bank1_SRAM2 is configured as follow: - In case of FSMC configuration + In case of FSMC configuration NORSRAMTimingStructure.FSMC_AddressSetupTime = 1; NORSRAMTimingStructure.FSMC_AddressHoldTime = 0; NORSRAMTimingStructure.FSMC_DataSetupTime = 2; @@ -1160,7 +1168,7 @@ void SystemInit_ExtMemCtl(void) FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; @@ -1171,7 +1179,7 @@ void SystemInit_ExtMemCtl(void) FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure; FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure; - In case of FMC configuration + In case of FMC configuration NORSRAMTimingStructure.FMC_AddressSetupTime = 1; NORSRAMTimingStructure.FMC_AddressHoldTime = 0; NORSRAMTimingStructure.FMC_DataSetupTime = 2; @@ -1185,7 +1193,7 @@ void SystemInit_ExtMemCtl(void) FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM; FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b; FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable; - FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable; + FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable; FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low; FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable; FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState; @@ -1197,8 +1205,8 @@ void SystemInit_ExtMemCtl(void) FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure; FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure; */ - -} + +} #elif defined (DATA_IN_ExtSDRAM) /** * @brief Setup the external memory controller. @@ -1213,170 +1221,170 @@ void SystemInit_ExtMemCtl(void) register uint32_t tmpreg = 0, timeout = 0xFFFF; register uint32_t index; - /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ RCC->AHB1ENR |= 0x000001FC; - + /* Connect PCx pins to FMC Alternate function */ GPIOC->AFR[0] = 0x0000000c; GPIOC->AFR[1] = 0x00007700; - /* Configure PCx pins in Alternate function mode */ + /* Configure PCx pins in Alternate function mode */ GPIOC->MODER = 0x00a00002; - /* Configure PCx pins speed to 50 MHz */ + /* Configure PCx pins speed to 50 MHz */ GPIOC->OSPEEDR = 0x00a00002; - /* Configure PCx pins Output type to push-pull */ + /* Configure PCx pins Output type to push-pull */ GPIOC->OTYPER = 0x00000000; - /* No pull-up, pull-down for PCx pins */ + /* No pull-up, pull-down for PCx pins */ GPIOC->PUPDR = 0x00500000; - + /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x000000CC; GPIOD->AFR[1] = 0xCC000CCC; - /* Configure PDx pins in Alternate function mode */ + /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xA02A000A; - /* Configure PDx pins speed to 50 MHz */ + /* Configure PDx pins speed to 50 MHz */ GPIOD->OSPEEDR = 0xA02A000A; - /* Configure PDx pins Output type to push-pull */ + /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ + /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00000CC; GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ + /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA800A; - /* Configure PEx pins speed to 50 MHz */ + /* Configure PEx pins speed to 50 MHz */ GPIOE->OSPEEDR = 0xAAAA800A; - /* Configure PEx pins Output type to push-pull */ + /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ + /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0xcccccccc; GPIOF->AFR[1] = 0xcccccccc; - /* Configure PFx pins in Alternate function mode */ + /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ + /* Configure PFx pins speed to 50 MHz */ GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ + /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ + /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0xcccccccc; GPIOG->AFR[1] = 0xcccccccc; - /* Configure PGx pins in Alternate function mode */ + /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0xaaaaaaaa; - /* Configure PGx pins speed to 50 MHz */ + /* Configure PGx pins speed to 50 MHz */ GPIOG->OSPEEDR = 0xaaaaaaaa; - /* Configure PGx pins Output type to push-pull */ + /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ + /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; - + /* Connect PHx pins to FMC Alternate function */ GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ + /* Configure PHx pins in Alternate function mode */ GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ + /* Configure PHx pins speed to 50 MHz */ GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ + /* Configure PHx pins Output type to push-pull */ GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ + /* No pull-up, pull-down for PHx pins */ GPIOH->PUPDR = 0x00000000; - + /* Connect PIx pins to FMC Alternate function */ GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ + /* Configure PIx pins in Alternate function mode */ GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ + /* Configure PIx pins speed to 50 MHz */ GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ + /* Configure PIx pins Output type to push-pull */ GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ + /* No pull-up, pull-down for PIx pins */ GPIOI->PUPDR = 0x00000000; - + /*-- FMC Configuration ------------------------------------------------------*/ /* Enable the FMC interface clock */ RCC->AHB3ENR |= 0x00000001; - + /* Configure and enable SDRAM bank1 */ FMC_Bank5_6->SDCR[0] = 0x000039D0; - FMC_Bank5_6->SDTR[0] = 0x01115351; - + FMC_Bank5_6->SDTR[0] = 0x01115351; + /* SDRAM initialization sequence */ /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; while((tmpreg != 0) & (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* Delay */ for (index = 0; index<1000; index++); - + /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; + FMC_Bank5_6->SDCMR = 0x00000012; timeout = 0xFFFF; while((tmpreg != 0) & (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* Auto refresh command */ FMC_Bank5_6->SDCMR = 0x00000073; timeout = 0xFFFF; while((tmpreg != 0) & (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* MRD register program */ FMC_Bank5_6->SDCMR = 0x00046014; timeout = 0xFFFF; while((tmpreg != 0) & (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + /* Set refresh count */ tmpreg = FMC_Bank5_6->SDRTR; FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); - + /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; + tmpreg = FMC_Bank5_6->SDCR[0]; FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); - + /* Bank1_SDRAM is configured as follow: - FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2; - FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6; - FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4; - FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6; - FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2; - FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2; - FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; + FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2; + FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6; + FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4; + FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6; + FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2; + FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2; + FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK; FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b; FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b; FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4; - FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3; + FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3; FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable; FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2; FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable; FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1; FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure; */ - + } #endif /* DATA_IN_ExtSDRAM && DATA_IN_ExtSRAM */ @@ -1388,8 +1396,8 @@ void SystemInit_ExtMemCtl(void) /** * @} */ - + /** * @} - */ + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Project/Src/STM32/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h b/Project/Src/STM32/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h index c3d4cad..30c8fd5 100644 --- a/Project/Src/STM32/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h +++ b/Project/Src/STM32/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h @@ -16,8 +16,8 @@ * * http://www.st.com/software_license_agreement_liberty_v2 * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. @@ -42,7 +42,7 @@ /** @addtogroup RCC * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ typedef struct @@ -51,6 +51,7 @@ typedef struct uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ + uint32_t USBCLK_Frequency; }RCC_ClocksTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -58,8 +59,8 @@ typedef struct /** @defgroup RCC_Exported_Constants * @{ */ - -/** @defgroup RCC_HSE_configuration + +/** @defgroup RCC_HSE_configuration * @{ */ #define RCC_HSE_OFF ((uint8_t)0x00) @@ -69,7 +70,7 @@ typedef struct ((HSE) == RCC_HSE_Bypass)) /** * @} - */ + */ /** @defgroup RCC_LSE_Dual_Mode_Selection * @{ @@ -97,7 +98,7 @@ typedef struct * @} */ -/** @defgroup RCC_PLL_Clock_Source +/** @defgroup RCC_PLL_Clock_Source * @{ */ #define RCC_PLLSource_HSI ((uint32_t)0x00000000) @@ -116,7 +117,7 @@ typedef struct #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) #define IS_RCC_PLLI2SM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63)) #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) -#if defined(STM32F446xx) +#if defined(STM32F446xx) #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63) #elif defined(STM32F412xG) || defined(STM32F413_423xx) @@ -128,7 +129,7 @@ typedef struct #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) #endif /* STM32F446xx || STM32F469_479xx */ #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) -#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) +#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) @@ -139,9 +140,9 @@ typedef struct #endif /* STM32F413_423xx */ /** * @} - */ - -/** @defgroup RCC_System_Clock_Source + */ + +/** @defgroup RCC_System_Clock_Source * @{ */ @@ -155,7 +156,7 @@ typedef struct ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \ ((SOURCE) == RCC_SYSCLKSource_PLLRCLK)) /* Add legacy definition */ -#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK +#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK #endif /* STM32F446xx */ #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx) @@ -165,11 +166,11 @@ typedef struct #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ ((SOURCE) == RCC_SYSCLKSource_HSE) || \ ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */ +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */ /** * @} - */ - + */ + /** @defgroup RCC_AHB_Clock_Source * @{ */ @@ -189,8 +190,8 @@ typedef struct ((HCLK) == RCC_SYSCLK_Div512)) /** * @} - */ - + */ + /** @defgroup RCC_APB1_APB2_Clock_Source * @{ */ @@ -204,9 +205,9 @@ typedef struct ((PCLK) == RCC_HCLK_Div16)) /** * @} - */ - -/** @defgroup RCC_Interrupt_Source + */ + +/** @defgroup RCC_Interrupt_Source * @{ */ #define RCC_IT_LSIRDY ((uint8_t)0x01) @@ -214,7 +215,7 @@ typedef struct #define RCC_IT_HSIRDY ((uint8_t)0x04) #define RCC_IT_HSERDY ((uint8_t)0x08) #define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) +#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) #define RCC_IT_PLLSAIRDY ((uint8_t)0x40) #define RCC_IT_CSS ((uint8_t)0x80) @@ -227,9 +228,9 @@ typedef struct /** * @} - */ - -/** @defgroup RCC_LSE_Configuration + */ + +/** @defgroup RCC_LSE_Configuration * @{ */ #define RCC_LSE_OFF ((uint8_t)0x00) @@ -239,8 +240,8 @@ typedef struct ((LSE) == RCC_LSE_Bypass)) /** * @} - */ - + */ + /** @defgroup RCC_RTC_Clock_Source * @{ */ @@ -310,7 +311,7 @@ typedef struct ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) /** * @} - */ + */ #if defined(STM32F410xx) || defined(STM32F413_423xx) /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source @@ -338,7 +339,7 @@ typedef struct #define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) #define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) || ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) || \ - ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) + ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) /** * @} */ @@ -355,7 +356,7 @@ typedef struct #define RCC_I2SCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_I2S1SRC_0 | RCC_DCKCFGR_I2S1SRC_1) #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \ - ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE)) + ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE)) /** * @} */ @@ -365,11 +366,11 @@ typedef struct */ #define RCC_I2SBus_APB1 ((uint8_t)0x00) #define RCC_I2SBus_APB2 ((uint8_t)0x01) -#define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2)) +#define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2)) /** * @} */ -#if defined(STM32F446xx) +#if defined(STM32F446xx) /** @defgroup RCC_SAI_Clock_Source * @{ */ @@ -379,22 +380,22 @@ typedef struct #define RCC_SAICLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1SRC_0 | RCC_DCKCFGR_SAI1SRC_1) #define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \ - ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE)) + ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE)) /** * @} - */ - + */ + /** @defgroup RCC_SAI_Instance * @{ */ #define RCC_SAIInstance_SAI1 ((uint8_t)0x00) #define RCC_SAIInstance_SAI2 ((uint8_t)0x01) -#define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2)) +#define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2)) /** * @} */ #endif /* STM32F446xx */ -#if defined(STM32F413_423xx) +#if defined(STM32F413_423xx) /** @defgroup RCC_SAI_BlockA_Clock_Source * @{ @@ -433,10 +434,10 @@ typedef struct #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) -#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) +#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) /** * @} - */ + */ /** @defgroup RCC_SAI_BlockA_Clock_Source * @{ @@ -450,7 +451,7 @@ typedef struct ((SOURCE) == RCC_SAIACLKSource_Ext)) /** * @} - */ + */ /** @defgroup RCC_SAI_BlockB_Clock_Source * @{ @@ -464,7 +465,7 @@ typedef struct ((SOURCE) == RCC_SAIBCLKSource_Ext)) /** * @} - */ + */ #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */ /** @defgroup RCC_TIM_PRescaler_Selection @@ -515,7 +516,7 @@ typedef struct #endif /* STM32F446xx || STM32F469_479xx */ #if defined(STM32F412xG) || defined(STM32F413_423xx) #define RCC_CK48CLKSOURCE_PLLQ ((uint8_t)0x00) -#define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG and STM32F413_423xx Devices */ +#define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG and STM32F413_423xx Devices */ #define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLQ) || \ ((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLI2SQ)) #endif /* STM32F412xG || STM32F413_423xx */ @@ -524,7 +525,7 @@ typedef struct */ #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ -#if defined(STM32F446xx) +#if defined(STM32F446xx) /** @defgroup RCC_SPDIFRX_Clock_Source_Selection * @{ */ @@ -549,7 +550,7 @@ typedef struct /** @defgroup RCC_AHB1_ClockGating * @{ - */ + */ #define RCC_AHB1ClockGating_APB1Bridge ((uint32_t)0x00000001) #define RCC_AHB1ClockGating_APB2Bridge ((uint32_t)0x00000002) #define RCC_AHB1ClockGating_CM4DBG ((uint32_t)0x00000004) @@ -572,7 +573,7 @@ typedef struct #define RCC_FMPI2C1CLKSource_APB1 ((uint32_t)0x00) #define RCC_FMPI2C1CLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) #define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) - + #define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \ ((SOURCE) == RCC_FMPI2C1CLKSource_HSI)) /** @@ -622,9 +623,9 @@ typedef struct #endif /* STM32F413_423xx */ #endif /* STM32F412xG || STM32F413_423xx */ -/** @defgroup RCC_AHB1_Peripherals +/** @defgroup RCC_AHB1_Peripherals * @{ - */ + */ #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) @@ -633,7 +634,7 @@ typedef struct #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) -#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) +#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) #define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200) #define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400) #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) @@ -661,26 +662,26 @@ typedef struct /** * @} - */ - -/** @defgroup RCC_AHB2_Peripherals + */ + +/** @defgroup RCC_AHB2_Peripherals * @{ - */ + */ #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) -#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) +#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) /** * @} - */ - -/** @defgroup RCC_AHB3_Peripherals + */ + +/** @defgroup RCC_AHB3_Peripherals * @{ - */ + */ #if defined(STM32F40_41xxx) #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) @@ -691,7 +692,7 @@ typedef struct #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) #endif /* STM32F427_437xx || STM32F429_439xx */ -#if defined(STM32F446xx) || defined(STM32F469_479xx) +#if defined(STM32F446xx) || defined(STM32F469_479xx) #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) #define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002) #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00)) @@ -705,11 +706,11 @@ typedef struct /** * @} - */ - -/** @defgroup RCC_APB1_Peripherals + */ + +/** @defgroup RCC_APB1_Peripherals * @{ - */ + */ #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) @@ -727,7 +728,7 @@ typedef struct #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) #if defined(STM32F446xx) #define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000) -#endif /* STM32F446xx */ +#endif /* STM32F446xx */ #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) @@ -737,7 +738,7 @@ typedef struct #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) #define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000) -#endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/ +#endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/ #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) #if defined(STM32F413_423xx) @@ -745,7 +746,7 @@ typedef struct #endif /* STM32F413_423xx */ #if defined(STM32F446xx) #define RCC_APB1Periph_CEC ((uint32_t)0x08000000) -#endif /* STM32F446xx */ +#endif /* STM32F446xx */ #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) #define RCC_APB1Periph_UART7 ((uint32_t)0x40000000) @@ -753,11 +754,11 @@ typedef struct #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00)) /** * @} - */ - -/** @defgroup RCC_APB2_Peripherals + */ + +/** @defgroup RCC_APB2_Peripherals * @{ - */ + */ #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) @@ -801,7 +802,7 @@ typedef struct /** * @} - */ + */ /** @defgroup RCC_MCO1_Clock_Source_Prescaler * @{ @@ -817,14 +818,14 @@ typedef struct #define RCC_MCO1Div_5 ((uint32_t)0x07000000) #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) - + #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ - ((DIV) == RCC_MCO1Div_5)) + ((DIV) == RCC_MCO1Div_5)) /** * @} - */ - + */ + /** @defgroup RCC_MCO2_Clock_Source_Prescaler * @{ */ @@ -839,15 +840,15 @@ typedef struct #define RCC_MCO2Div_5 ((uint32_t)0x38000000) #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) - + #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ - ((DIV) == RCC_MCO2Div_5)) + ((DIV) == RCC_MCO2Div_5)) /** * @} - */ - -/** @defgroup RCC_Flag + */ + +/** @defgroup RCC_Flag * @{ */ #define RCC_FLAG_HSIRDY ((uint8_t)0x21) @@ -876,14 +877,14 @@ typedef struct #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) /** * @} - */ + */ /** * @} - */ + */ /* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /* Function used to set the RCC clock configuration to the default reset state */ void RCC_DeInit(void); @@ -949,7 +950,7 @@ void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); void RCC_RTCCLKCmd(FunctionalState NewState); void RCC_BackupResetCmd(FunctionalState NewState); -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) +#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource); #if defined(STM32F446xx) void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource); @@ -1057,10 +1058,10 @@ void RCC_ClearITPendingBit(uint8_t RCC_IT); /** * @} - */ + */ /** * @} - */ + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Project/Src/STM32/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c b/Project/Src/STM32/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c index 823c1ba..d410922 100644 --- a/Project/Src/STM32/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c +++ b/Project/Src/STM32/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c @@ -4,7 +4,7 @@ * @author MCD Application Team * @version V1.8.0 * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following + * @brief This file provides firmware functions to manage the following * functionalities of the Reset and clock control (RCC) peripheral: * + Internal/external clocks, PLL, CSS and MCO configuration * + System, AHB and APB busses clocks configuration @@ -15,9 +15,9 @@ =============================================================================== ##### RCC specific features ##### =============================================================================== - [..] - After reset the device is running from Internal High Speed oscillator - (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache and I-Cache are disabled, and all peripherals are off except internal SRAM, Flash and JTAG. (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; @@ -25,16 +25,16 @@ (+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) All GPIOs are in input floating state, except the JTAG pins which are assigned to be used for debug purpose. - [..] + [..] Once the device started from reset, the user application has to: (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings + (+) Configure the System clock frequency and Flash settings (+) Configure the AHB and APB busses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals which clocks are not derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) - @endverbatim + @endverbatim ****************************************************************************** * @attention * @@ -46,8 +46,8 @@ * * http://www.st.com/software_license_agreement_liberty_v2 * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. @@ -62,10 +62,10 @@ * @{ */ -/** @defgroup RCC +/** @defgroup RCC * @brief RCC driver modules * @{ - */ + */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -116,7 +116,7 @@ #define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C) #define TIMPRE_BitNumber 0x18 #define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4)) - + /* --- CFGR Register ---*/ #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08) #if defined(STM32F410xx) @@ -157,19 +157,19 @@ static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6 /** @defgroup RCC_Private_Functions * @{ - */ + */ /** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions - * @brief Internal and external clocks, PLL, CSS and MCO configuration functions + * @brief Internal and external clocks, PLL, CSS and MCO configuration functions * -@verbatim +@verbatim =================================================================================== ##### Internal and external clocks, PLL, CSS and MCO configuration functions ##### =================================================================================== [..] This section provide functions allowing to configure the internal/external clocks, PLLs, CSS and MCO pins. - + (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through the PLL as System clock source. @@ -179,25 +179,25 @@ static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or through the PLL as System clock source. Can be used also as RTC clock source. - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. (#) PLL (clocked by HSI or HSE), featuring two different output clocks: (++) The first output is used to generate the high speed system clock (up to 168 MHz) (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). - (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve - high-quality audio performance on the I2S interface or SAI interface in case + (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve + high-quality audio performance on the I2S interface or SAI interface in case of STM32F429x/439x devices. - - (#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI + + (#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI interface and LCD TFT controller available only for STM32F42xxx/43xxx/446xx/469xx/479xx devices. - - (#) CSS (Clock security system), once enable and if a HSE clock failure occurs + + (#) CSS (Clock security system), once enable and if a HSE clock failure occurs (HSE used directly or through PLL as System clock source), the System clock - is automatically switched to HSI and an interrupt is generated if enabled. - The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) - exception vector. + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) + exception vector. (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL clock (through a configurable prescaler) on PA8 pin. @@ -217,8 +217,8 @@ static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6 * - CSS, MCO1 and MCO2 OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks + * - Peripheral clocks + * - LSI, LSE and RTC clocks * @param None * @retval None */ @@ -232,20 +232,20 @@ void RCC_DeInit(void) /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42xxx/43xxx/446xx/469xx/479xx devices) bits */ RCC->CR &= (uint32_t)0xEAF6FFFF; - + /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x24003010; -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F413_423xx) || defined(STM32F469_479xx) +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F413_423xx) || defined(STM32F469_479xx) /* Reset PLLI2SCFGR register */ RCC->PLLI2SCFGR = 0x20003000; #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F413_423xx || STM32F469_479xx */ -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) /* Reset PLLSAICFGR register, only available for STM32F42xxx/43xxx/446xx/469xx/479xx devices */ RCC->PLLSAICFGR = 0x24003000; #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ - + /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; @@ -254,11 +254,11 @@ void RCC_DeInit(void) /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx and STM32F413_423xx devices */ RCC->DCKCFGR = 0x00000000; - + #if defined(STM32F410xx) || defined(STM32F413_423xx) /* Disable LPTIM and FMPI2C clock prescalers selection, only available for STM32F410xx and STM32F413_423xx devices */ RCC->DCKCFGR2 = 0x00000000; -#endif /* STM32F410xx || STM32F413_423xx */ +#endif /* STM32F410xx || STM32F413_423xx */ } /** @@ -269,10 +269,10 @@ void RCC_DeInit(void) * @note HSE state can not be changed if it is used directly or through the * PLL as system clock. In this case, you have to select another source * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. * @note This function reset the CSSON bit, so if the Clock security system(CSS) * was previously enabled you have to enable it again after calling this - * function. + * function. * @param RCC_HSE: specifies the new state of the HSE. * This parameter can be one of the following values: * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after @@ -295,11 +295,11 @@ void RCC_HSEConfig(uint8_t RCC_HSE) /** * @brief Waits for HSE start-up. - * @note This functions waits on HSERDY flag to be set and return SUCCESS if - * this flag is set, otherwise returns ERROR if the timeout is reached + * @note This functions waits on HSERDY flag to be set and return SUCCESS if + * this flag is set, otherwise returns ERROR if the timeout is reached * and this flag is not set. The timeout value is defined by the constant * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending - * on the HSE crystal used in your application. + * on the HSE crystal used in your application. * @param None * @retval An ErrorStatus enumeration value: * - SUCCESS: HSE oscillator is stable and ready to use @@ -360,16 +360,16 @@ void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) * It is used (enabled by hardware) as system clock source after startup * from Reset, wakeup from STOP and STANDBY mode, or in case of failure * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). + * Security System CSS is enabled). * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. + * you have to select another source of the system clock then stop the HSI. * @note After enabling the HSI, the application software should wait on HSIRDY * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. + * system clock source. * @param NewState: new state of the HSI. * This parameter can be: ENABLE or DISABLE. * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. + * clock cycles. * @retval None */ void RCC_HSICmd(FunctionalState NewState) @@ -383,9 +383,9 @@ void RCC_HSICmd(FunctionalState NewState) /** * @brief Configures the External Low Speed oscillator (LSE). * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using + * this domain after reset, you have to enable write access using * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE - * (to be done once after reset). + * (to be done once after reset). * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. @@ -427,14 +427,14 @@ void RCC_LSEConfig(uint8_t RCC_LSE) /** * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on + * @note After enabling the LSI, the application software should wait on * LSIRDY flag to be set indicating that LSI clock is stable and can * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. + * @note LSI can not be disabled if the IWDG is running. * @param NewState: new state of the LSI. * This parameter can be: ENABLE or DISABLE. * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. + * clock cycles. * @retval None */ void RCC_LSICmd(FunctionalState NewState) @@ -449,29 +449,29 @@ void RCC_LSICmd(FunctionalState NewState) /** * @brief Configures the main PLL clock source, multiplication and division factors. * @note This function must be used only when the main PLL is disabled. - * + * * @param RCC_PLLSource: specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * * @param PLLM: specifies the division factor for PLL VCO input clock * This parameter must be a number between 0 and 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 2 MHz to limit PLL jitter. - * + * * @param PLLN: specifies the multiplication factor for PLL VCO output clock * This parameter must be a number between 50 and 432. * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 100 and 432 MHz. - * + * * @param PLLP: specifies the division factor for main system clock (SYSCLK) * This parameter must be a number in the range {2, 4, 6, or 8}. * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on * the System clock frequency. - * + * * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks * This parameter must be a number between 4 and 15. * @@ -482,7 +482,7 @@ void RCC_LSICmd(FunctionalState NewState) * PLLQ parameter correctly to have 48 MHz clock for the USB. However, * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work * correctly. - * + * * @retval None */ void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR) @@ -494,7 +494,7 @@ void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_ assert_param(IS_RCC_PLLP_VALUE(PLLP)); assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); assert_param(IS_RCC_PLLR_VALUE(PLLR)); - + RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | (PLLQ << 24) | (PLLR << 28); } @@ -504,36 +504,36 @@ void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_ /** * @brief Configures the main PLL clock source, multiplication and division factors. * @note This function must be used only when the main PLL is disabled. - * + * * @param RCC_PLLSource: specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * * @param PLLM: specifies the division factor for PLL VCO input clock * This parameter must be a number between 0 and 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 2 MHz to limit PLL jitter. - * + * * @param PLLN: specifies the multiplication factor for PLL VCO output clock * This parameter must be a number between 50 and 432. * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 100 and 432 MHz. - * + * * @param PLLP: specifies the division factor for main system clock (SYSCLK) * This parameter must be a number in the range {2, 4, 6, or 8}. * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on * the System clock frequency. - * + * * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks * This parameter must be a number between 4 and 15. * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work * correctly. - * + * * @retval None */ void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) @@ -552,7 +552,7 @@ void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_ /** * @brief Enables or disables the main PLL. - * @note After enabling the main PLL, the application software should wait on + * @note After enabling the main PLL, the application software should wait on * PLLRDY flag to be set indicating that PLL clock is stable and can * be used as system clock source. * @note The main PLL can not be disabled if it is used as system clock source @@ -570,24 +570,24 @@ void RCC_PLLCmd(FunctionalState NewState) #if defined(STM32F40_41xxx) || defined(STM32F401xx) /** * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note This function can be used only for STM32F405xx/407xx, STM32F415xx/417xx - * or STM32F401xx devices. - * + * + * @note This function can be used only for STM32F405xx/407xx, STM32F415xx/417xx + * or STM32F401xx devices. + * * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * + * @note PLLI2S clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between 50 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between 100 and 432 MHz. - * + * * @param PLLI2SR: specifies the division factor for I2S clock * This parameter must be a number between 2 and 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. - * + * * @retval None */ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) @@ -603,12 +603,12 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) #if defined(STM32F411xE) /** * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note This function can be used only for STM32F411xE devices. - * + * + * @note This function can be used only for STM32F411xE devices. + * * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) + * @note PLLI2S clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) * * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. @@ -618,14 +618,14 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) * * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between 50 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between 100 and 432 MHz. - * + * * @param PLLI2SR: specifies the division factor for I2S clock * This parameter must be a number between 2 and 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. - * + * * @retval None */ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM) @@ -642,26 +642,26 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM) #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) /** * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note This function can be used only for STM32F42xxx/43xxx devices - * + * + * @note This function can be used only for STM32F42xxx/43xxx devices + * * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * + * @note PLLI2S clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between 50 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between 100 and 432 MHz. - * + * * @param PLLI2SQ: specifies the division factor for SAI1 clock * This parameter must be a number between 2 and 15. - * + * * @param PLLI2SR: specifies the division factor for I2S clock * This parameter must be a number between 2 and 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. - * + * * @retval None */ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR) @@ -678,13 +678,13 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR) #if defined(STM32F412xG ) || defined(STM32F413_423xx) || defined(STM32F446xx) /** * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note This function can be used only for STM32F446xx devices - * + * + * @note This function can be used only for STM32F446xx devices + * * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * + * @note PLLI2S clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input @@ -693,7 +693,7 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR) * * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between 50 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between 100 and 432 MHz. * * @param PLLI2SP: specifies the division factor for PLL 48Mhz clock output @@ -701,13 +701,13 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR) * * @param PLLI2SQ: specifies the division factor for SAI1 clock * This parameter must be a number between 2 and 15. - * + * * @param PLLI2SR: specifies the division factor for I2S clock * This parameter must be a number between 2 and 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. - * @note the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices. - * + * @note the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices. + * * @retval None */ void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR) @@ -724,8 +724,8 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ /** - * @brief Enables or disables the PLLI2S. - * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + * @brief Enables or disables the PLLI2S. + * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. * @retval None */ @@ -740,26 +740,26 @@ void RCC_PLLI2SCmd(FunctionalState NewState) /** * @brief Configures the PLLSAI clock multiplication and division factors. * - * @note This function can be used only for STM32F469_479xx devices - * + * @note This function can be used only for STM32F469_479xx devices + * * @note This function must be used only when the PLLSAI is disabled. - * @note PLLSAI clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) + * @note PLLSAI clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) * * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock * This parameter must be a number between 50 and 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO * output frequency is between 100 and 432 MHz. * * @param PLLSAIP: specifies the division factor for PLL 48Mhz clock output * This parameter must be a number in the range {2, 4, 6, or 8}.. - * + * * @param PLLSAIQ: specifies the division factor for SAI1 clock * This parameter must be a number between 2 and 15. - * + * * @param PLLSAIR: specifies the division factor for LTDC clock * This parameter must be a number between 2 and 7. - * + * * @retval None */ void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR) @@ -778,12 +778,12 @@ void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint /** * @brief Configures the PLLSAI clock multiplication and division factors. * - * @note This function can be used only for STM32F446xx devices - * + * @note This function can be used only for STM32F446xx devices + * * @note This function must be used only when the PLLSAI is disabled. - * @note PLLSAI clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * + * @note PLLSAI clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * * @param PLLSAIM: specifies the division factor for PLLSAI VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input @@ -792,15 +792,15 @@ void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint * * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock * This parameter must be a number between 50 and 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO * output frequency is between 100 and 432 MHz. - * + * * @param PLLSAIP: specifies the division factor for PLL 48Mhz clock output * This parameter must be a number in the range {2, 4, 6, or 8}. * * @param PLLSAIQ: specifies the division factor for SAI1 clock * This parameter must be a number between 2 and 15. - * + * * @retval None */ void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ) @@ -819,23 +819,23 @@ void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint /** * @brief Configures the PLLSAI clock multiplication and division factors. * - * @note This function can be used only for STM32F42xxx/43xxx devices - * + * @note This function can be used only for STM32F42xxx/43xxx devices + * * @note This function must be used only when the PLLSAI is disabled. - * @note PLLSAI clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * + * @note PLLSAI clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock * This parameter must be a number between 50 and 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO * output frequency is between 100 and 432 MHz. - * + * * @param PLLSAIQ: specifies the division factor for SAI1 clock * This parameter must be a number between 2 and 15. - * + * * @param PLLSAIR: specifies the division factor for LTDC clock * This parameter must be a number between 2 and 7. - * + * * @retval None */ void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR) @@ -844,17 +844,17 @@ void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR) assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN)); assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR)); assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ)); - + RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28); } #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ /** - * @brief Enables or disables the PLLSAI. - * - * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices - * - * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. + * @brief Enables or disables the PLLSAI. + * + * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices + * + * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. * @param NewState: new state of the PLLSAI. This parameter can be: ENABLE or DISABLE. * @retval None */ @@ -870,8 +870,8 @@ void RCC_PLLSAICmd(FunctionalState NewState) * @note If a failure is detected on the HSE oscillator clock, this oscillator * is automatically disabled and an interrupt is generated to inform the * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. * @param NewState: new state of the Clock Security System. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -904,10 +904,10 @@ void RCC_ClockSecuritySystemCmd(FunctionalState NewState) void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source)); - assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); + assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); tmpreg = RCC->CFGR; @@ -916,13 +916,13 @@ void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) /* Select MCO1 clock source and prescaler */ tmpreg |= RCC_MCO1Source | RCC_MCO1Div; - + /* Store the new value */ RCC->CFGR = tmpreg; #if defined(STM32F410xx) RCC_MCO1Cmd(ENABLE); -#endif /* STM32F410xx */ +#endif /* STM32F410xx */ } /** @@ -931,8 +931,8 @@ void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) * @param RCC_MCO2Source: specifies the clock source to output. * This parameter can be one of the following values: * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx - * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410xx devices + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx + * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410xx devices * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source * @param RCC_MCO2Div: specifies the MCO2 prescaler. @@ -949,25 +949,25 @@ void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source)); assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div)); - + tmpreg = RCC->CFGR; - + /* Clear MCO2 and MCO2PRE[2:0] bits */ tmpreg &= CFGR_MCO2_RESET_MASK; /* Select MCO2 clock source and prescaler */ tmpreg |= RCC_MCO2Source | RCC_MCO2Div; - + /* Store the new value */ RCC->CFGR = tmpreg; #if defined(STM32F410xx) RCC_MCO2Cmd(ENABLE); -#endif /* STM32F410xx */ +#endif /* STM32F410xx */ } /** @@ -977,37 +977,37 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) /** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions * @brief System, AHB and APB busses clocks configuration functions * -@verbatim +@verbatim =============================================================================== ##### System, AHB and APB busses clocks configuration functions ##### - =============================================================================== + =============================================================================== [..] - This section provide functions allowing to configure the System, AHB, APB1 and + This section provide functions allowing to configure the System, AHB, APB1 and APB2 busses clocks. - + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use - "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or - from an external clock mapped on the I2S_CKIN pin. - You have to use RCC_I2SCLKConfig() function to configure this clock. + from an external clock mapped on the I2S_CKIN pin. + You have to use RCC_I2SCLKConfig() function to configure this clock. (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() - functions to configure this clock. + functions to configure this clock. (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz to work correctly, while the SDIO require a frequency equal or lower than to 48. This clock is derived of the main PLL through PLLQ divider. (+@) IWDG clock which is always the LSI clock. - - (#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency - of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending + + (#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency + of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly: +-------------------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | @@ -1031,8 +1031,8 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) |---------------|----------------|----------------|-----------------|-----------------| |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160| +---------------|----------------|----------------|-----------------|-----------------+ - (#) For STM32F42xxx/43xxx/469xx/479xx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz, - PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum + (#) For STM32F42xxx/43xxx/469xx/479xx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz, + PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly: +-------------------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | @@ -1058,9 +1058,9 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) |---------------|----------------|----------------|-----------------|-----------------| |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168| +-------------------------------------------------------------------------------------+ - - (#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz, - PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum + + (#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz, + PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly: +-------------------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | @@ -1079,8 +1079,8 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 | +-------------------------------------------------------------------------------------+ - (#) For STM32F410xx/STM32F411xE devices, the maximum frequency of the SYSCLK and HCLK is 100 MHz, - PCLK2 100 MHz and PCLK1 50 MHz. Depending on the device voltage range, the maximum + (#) For STM32F410xx/STM32F411xE devices, the maximum frequency of the SYSCLK and HCLK is 100 MHz, + PCLK2 100 MHz and PCLK1 50 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly: +-------------------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | @@ -1102,16 +1102,16 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) |---------------|----------------|----------------|-----------------|-----------------| |6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 | +-------------------------------------------------------------------------------------+ - - -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: - (++) when VOS = '0', the maximum value of fHCLK = 144MHz. - (++) when VOS = '1', the maximum value of fHCLK = 168MHz. - [..] + + -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: + (++) when VOS = '0', the maximum value of fHCLK = 144MHz. + (++) when VOS = '1', the maximum value of fHCLK = 168MHz. + [..] On STM32F42xxx/43xxx/469xx/479xx devices: (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz. (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz. - (++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz - [..] + (++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz + [..] On STM32F401x devices: (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz. (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz. @@ -1133,11 +1133,11 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) * of failure of the HSE used directly or indirectly as system clock * (if the Clock Security System CSS is enabled). * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). + * clock source is ready (clock stable after startup delay or PLL locked). * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. + * occur when the clock source will be ready. * You can use RCC_GetSYSCLKSource() function to know which clock is - * currently used as system clock source. + * currently used as system clock source. * @param RCC_SYSCLKSource: specifies the clock source used as system clock. * This parameter can be one of the following values: * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source @@ -1186,7 +1186,7 @@ uint8_t RCC_GetSYSCLKSource(void) * these bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above * "CPU, AHB and APB busses clocks configuration functions") - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from * the system clock (SYSCLK). * This parameter can be one of the following values: * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK @@ -1203,7 +1203,7 @@ uint8_t RCC_GetSYSCLKSource(void) void RCC_HCLKConfig(uint32_t RCC_SYSCLK) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_RCC_HCLK(RCC_SYSCLK)); @@ -1221,7 +1221,7 @@ void RCC_HCLKConfig(uint32_t RCC_SYSCLK) /** * @brief Configures the Low Speed APB clock (PCLK1). - * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from + * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from * the AHB clock (HCLK). * This parameter can be one of the following values: * @arg RCC_HCLK_Div1: APB1 clock = HCLK @@ -1252,7 +1252,7 @@ void RCC_PCLK1Config(uint32_t RCC_HCLK) /** * @brief Configures the High Speed APB clock (PCLK2). - * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from + * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from * the AHB clock (HCLK). * This parameter can be one of the following values: * @arg RCC_HCLK_Div1: APB2 clock = HCLK @@ -1282,16 +1282,16 @@ void RCC_PCLK2Config(uint32_t RCC_HCLK) } /** - * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, + * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, * PCLK1 and PCLK2. - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. @@ -1299,31 +1299,32 @@ void RCC_PCLK2Config(uint32_t RCC_HCLK) * 25 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. - * + * * @note The result of this function could be not correct when using fractional * value for HSE crystal. - * + * * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold * the clocks frequencies. - * - * @note This function can be used by the user application to compute the + * + * @note This function can be used by the user application to compute the * baudrate for the communication peripherals or configure other parameters. * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function * must be called to update the structure's field. Otherwise, any * configuration based on this function will be incorrect. - * + * * @retval None */ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) { - uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) + uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllq = 7, pllsource = 0, + pllm = 2; +#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) uint32_t pllr = 2; #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ - + /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; - + switch (tmp) { case 0x00: /* HSI used as system clock source */ @@ -1333,13 +1334,13 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; break; case 0x08: /* PLL P used as system clock source */ - + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP - */ + */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - + if (pllsource != 0) { /* HSE used as PLL clock source */ @@ -1348,21 +1349,23 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) else { /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } - + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + pllq = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >>24); RCC_Clocks->SYSCLK_Frequency = pllvco/pllp; + RCC_Clocks->USBCLK_Frequency = pllvco/pllq; break; #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) case 0x0C: /* PLL R used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLR - */ + */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - + if (pllsource != 0) { /* HSE used as PLL clock source */ @@ -1371,20 +1374,20 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) else { /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } - + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2; - RCC_Clocks->SYSCLK_Frequency = pllvco/pllr; + RCC_Clocks->SYSCLK_Frequency = pllvco/pllr; break; #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ - + default: RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; break; } /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/ - + /* Get HCLK prescaler */ tmp = RCC->CFGR & RCC_CFGR_HPRE; tmp = tmp >> 4; @@ -1412,30 +1415,30 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) */ /** @defgroup RCC_Group3 Peripheral clocks configuration functions - * @brief Peripheral clocks configuration functions + * @brief Peripheral clocks configuration functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral clocks configuration functions ##### - =============================================================================== - [..] This section provide functions allowing to configure the Peripheral clocks. - - (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided + =============================================================================== + [..] This section provide functions allowing to configure the Peripheral clocks. + + (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31. - + (#) After restart from Reset or wakeup from STANDBY, all peripherals are off - except internal SRAM, Flash and JTAG. Before to start using a peripheral - you have to enable its interface clock. You can do this using + except internal SRAM, Flash and JTAG. Before to start using a peripheral + you have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. (#) To reset the peripherals configuration (to the default state after device reset) - you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and + you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and RCC_APB1PeriphResetCmd() functions. - - (#) To further reduce power consumption in SLEEP mode the peripheral clocks - can be disabled prior to executing the WFI or WFE instructions. - You can do this using RCC_AHBPeriphClockLPModeCmd(), - RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions. + + (#) To further reduce power consumption in SLEEP mode the peripheral clocks + can be disabled prior to executing the WFI or WFE instructions. + You can do this using RCC_AHBPeriphClockLPModeCmd(), + RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions. @endverbatim * @{ @@ -1446,25 +1449,25 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) * @note As the RTC clock configuration bits are in the Backup domain and write * access is denied to this domain after reset, you have to enable write * access using PWR_BackupAccessCmd(ENABLE) function before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the * Backup domain is reset using RCC_BackupResetCmd() function, or by * a Power On Reset (POR). - * + * * @param RCC_RTCCLKSource: specifies the RTC clock source. * This parameter can be one of the following values: * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected * as RTC clock, where x:[2,31] - * + * * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wakeup source. * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. + * cannot be used in STOP and STANDBY modes. * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as * RTC clock source). - * + * * @retval None */ void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) @@ -1487,7 +1490,7 @@ void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) /* Store the new value */ RCC->CFGR = tmpreg; } - + /* Select the RTC clock source */ RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF); } @@ -1511,7 +1514,7 @@ void RCC_RTCCLKCmd(FunctionalState NewState) * @brief Forces or releases the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. + * @note The BKPSRAM is not affected by this reset. * @param NewState: new state of the Backup domain reset. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1547,7 +1550,7 @@ void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource) /* Check the parameters */ assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); assert_param(IS_RCC_I2S_APBx(RCC_I2SAPBx)); - + if(RCC_I2SAPBx == RCC_I2SBus_APB1) { /* Clear APB1 I2Sx clock source selection bits */ @@ -1586,7 +1589,7 @@ void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource) /* Check the parameters */ assert_param(IS_RCC_SAICLK_SOURCE(RCC_SAICLKSource)); assert_param(IS_RCC_SAI_INSTANCE(RCC_SAIInstance)); - + if(RCC_SAIInstance == RCC_SAIInstance_SAI1) { /* Clear SAI1 clock source selection bits */ @@ -1606,8 +1609,8 @@ void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource) #if defined(STM32F413_423xx) /** - * @brief Configures SAI1BlockA clock source selection. - * @note This function must be called before enabling PLLSAI, PLLI2S and + * @brief Configures SAI1BlockA clock source selection. + * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source. * This parameter can be one of the following values: @@ -1620,10 +1623,10 @@ void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource) void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource)); - + tmpreg = RCC->DCKCFGR; /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */ @@ -1637,8 +1640,8 @@ void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource) } /** - * @brief Configures SAI1BlockB clock source selection. - * @note This function must be called before enabling PLLSAI, PLLI2S and + * @brief Configures SAI1BlockB clock source selection. + * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source. * This parameter can be one of the following values: @@ -1651,10 +1654,10 @@ void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource) void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource)); - + tmpreg = RCC->DCKCFGR; /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */ @@ -1685,7 +1688,7 @@ void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) { /* Check the parameters */ assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); - + /* Clear I2Sx clock source selection bits */ RCC->DCKCFGR &= ~RCC_DCKCFGR_I2SSRC; /* Set new I2Sx clock source*/ @@ -1709,24 +1712,24 @@ void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) /* Check the parameters */ assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); - *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; + *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; } #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */ #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) /** * @brief Configures SAI1BlockA clock source selection. - * + * * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. - * - * @note This function must be called before enabling PLLSAI, PLLI2S and + * + * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source. * This parameter can be one of the following values: - * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 Block A clock - * @arg RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI1 Block A clock + * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 Block A clock + * @arg RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 Block A clock * @arg RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin * used as SAI1 Block A clock * @retval None @@ -1734,10 +1737,10 @@ void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource)); - + tmpreg = RCC->DCKCFGR; /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */ @@ -1752,17 +1755,17 @@ void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource) /** * @brief Configures SAI1BlockB clock source selection. - * + * * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. - * - * @note This function must be called before enabling PLLSAI, PLLI2S and + * + * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source. * This parameter can be one of the following values: - * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 Block B clock - * @arg RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI1 Block B clock + * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 Block B clock + * @arg RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 Block B clock * @arg RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin * used as SAI1 Block B clock * @retval None @@ -1770,10 +1773,10 @@ void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource) void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource)); - + tmpreg = RCC->DCKCFGR; /* Clear RCC_DCKCFGR_SAI1BSRC[1:0] bits */ @@ -1789,24 +1792,24 @@ void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource) /** * @brief Configures the SAI clock Divider coming from PLLI2S. - * + * * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices. - * + * * @note This function must be called before enabling the PLLI2S. - * + * * @param RCC_PLLI2SDivQ: specifies the PLLI2S division factor for SAI1 clock . * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ - * + * SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ + * * @retval None */ -void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ) +void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(RCC_PLLI2SDivQ)); - + tmpreg = RCC->DCKCFGR; /* Clear PLLI2SDIVQ[4:0] bits */ @@ -1821,24 +1824,24 @@ void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ) /** * @brief Configures the SAI clock Divider coming from PLLSAI. - * + * * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices. - * + * * @note This function must be called before enabling the PLLSAI. - * + * * @param RCC_PLLSAIDivQ: specifies the PLLSAI division factor for SAI1 clock . * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ - * + * SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ + * * @retval None */ -void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ) +void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ)); - + tmpreg = RCC->DCKCFGR; /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */ @@ -1854,21 +1857,21 @@ void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ) #if defined(STM32F413_423xx) /** * @brief Configures the SAI clock Divider coming from PLLI2S. - * + * * @note This function can be used only for STM32F413_423xx - * + * * @param RCC_PLLI2SDivR: specifies the PLLI2S division factor for SAI1 clock. * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLI2SR) / RCC_PLLI2SDivR + * SAI1 clock frequency = f(PLLI2SR) / RCC_PLLI2SDivR * @retval None */ -void RCC_SAIPLLI2SRClkDivConfig(uint32_t RCC_PLLI2SDivR) +void RCC_SAIPLLI2SRClkDivConfig(uint32_t RCC_PLLI2SDivR) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_RCC_PLLI2S_DIVR_VALUE(RCC_PLLI2SDivR)); - + tmpreg = RCC->DCKCFGR; /* Clear PLLI2SDIVR[4:0] bits */ @@ -1883,24 +1886,24 @@ void RCC_SAIPLLI2SRClkDivConfig(uint32_t RCC_PLLI2SDivR) /** * @brief Configures the SAI clock Divider coming from PLL. - * + * * @note This function can be used only for STM32F413_423xx - * + * * @note This function must be called before enabling the PLLSAI. - * + * * @param RCC_PLLDivR: specifies the PLL division factor for SAI1 clock. * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLR) / RCC_PLLDivR - * + * SAI1 clock frequency = f(PLLR) / RCC_PLLDivR + * * @retval None */ -void RCC_SAIPLLRClkDivConfig(uint32_t RCC_PLLDivR) +void RCC_SAIPLLRClkDivConfig(uint32_t RCC_PLLDivR) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_RCC_PLL_DIVR_VALUE(RCC_PLLDivR)); - + tmpreg = RCC->DCKCFGR; /* Clear PLLDIVR[12:8] */ @@ -1916,28 +1919,28 @@ void RCC_SAIPLLRClkDivConfig(uint32_t RCC_PLLDivR) /** * @brief Configures the LTDC clock Divider coming from PLLSAI. - * + * * @note The LTDC peripheral is only available with STM32F42xxx/43xxx/446xx/469xx/479xx Devices. - * + * * @note This function must be called before enabling the PLLSAI. - * + * * @param RCC_PLLSAIDivR: specifies the PLLSAI division factor for LTDC clock . - * LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR + * LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR * This parameter can be one of the following values: * @arg RCC_PLLSAIDivR_Div2: LTDC clock = f(PLLSAI_R)/2 * @arg RCC_PLLSAIDivR_Div4: LTDC clock = f(PLLSAI_R)/4 * @arg RCC_PLLSAIDivR_Div8: LTDC clock = f(PLLSAI_R)/8 * @arg RCC_PLLSAIDivR_Div16: LTDC clock = f(PLLSAI_R)/16 - * + * * @retval None */ void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_RCC_PLLSAI_DIVR_VALUE(RCC_PLLSAIDivR)); - + tmpreg = RCC->DCKCFGR; /* Clear PLLSAIDIVR[2:0] bits */ @@ -1958,16 +1961,16 @@ void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR) * This parameter can be one of the following values: * @arg RCC_DFSDMCLKSource_APB: APB clock used as DFSDM clock source. * @arg RCC_DFSDMCLKSource_SYS: System clock used as DFSDM clock source. - * + * * @retval None */ void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDMCLKSource) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLK_SOURCE(RCC_DFSDMCLKSource)); - + tmpreg = RCC->DCKCFGR; /* Clear CKDFSDM-SEL bit */ @@ -1987,16 +1990,16 @@ void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDMCLKSource) * This parameter can be one of the following values: * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source. * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source. - * + * * @retval None */ void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_RCC_DFSDMACLK_SOURCE(RCC_DFSDM1ACLKSource)); - + tmpreg = RCC->DCKCFGR; /* Clear CKDFSDMA SEL bit */ @@ -2017,16 +2020,16 @@ void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource) * This parameter can be one of the following values: * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source. * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source. - * + * * @retval None */ void RCC_DFSDM2ACLKConfig(uint32_t RCC_DFSDMACLKSource) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_RCC_DFSDMCLK_SOURCE(RCC_DFSDMACLKSource)); - + tmpreg = RCC->DCKCFGR; /* Clear CKDFSDMA SEL bit */ @@ -2043,19 +2046,19 @@ void RCC_DFSDM2ACLKConfig(uint32_t RCC_DFSDMACLKSource) /** * @brief Configures the Timers clocks prescalers selection. - * - * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices. - * + * + * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices. + * * @param RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection * This parameter can be one of the following values: - * @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1 or 2, - * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to + * @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1 or 2, + * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to * division by 4 or more. - * - * @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, - * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding + * + * @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, + * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding * to division by 8 or more. * @retval None */ @@ -2070,12 +2073,12 @@ void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler) /** * @brief Enables or disables the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. + * is disabled and the application software has to enable this clock before + * using it. * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock * @arg RCC_AHB1Periph_GPIOC: GPIOC clock * @arg RCC_AHB1Periph_GPIOD: GPIOD clock * @arg RCC_AHB1Periph_GPIOE: GPIOE clock @@ -2083,14 +2086,14 @@ void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler) * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) * @arg RCC_AHB1Periph_CRC: CRC clock * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock * @arg RCC_AHB1Periph_DMA1: DMA1 clock * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) + * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock @@ -2120,8 +2123,8 @@ void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) /** * @brief Enables or disables the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. + * is disabled and the application software has to enable this clock before + * using it. * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_AHB2Periph_DCMI: DCMI clock @@ -2153,10 +2156,10 @@ void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) /** * @brief Enables or disables the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. + * is disabled and the application software has to enable this clock before + * using it. * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. - * This parameter must be: + * This parameter must be: * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F413_423xx/STM32F429x/439x devices) * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices) * @param NewState: new state of the specified peripheral clock. @@ -2166,7 +2169,7 @@ void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) { /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) @@ -2183,8 +2186,8 @@ void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) /** * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. + * is disabled and the application software has to enable this clock before + * using it. * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_APB1Periph_TIM2: TIM2 clock @@ -2196,11 +2199,11 @@ void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) * @arg RCC_APB1Periph_TIM12: TIM12 clock * @arg RCC_APB1Periph_TIM13: TIM13 clock * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices) + * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices) * @arg RCC_APB1Periph_WWDG: WWDG clock * @arg RCC_APB1Periph_SPI2: SPI2 clock * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices) + * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices) * @arg RCC_APB1Periph_USART2: USART2 clock * @arg RCC_APB1Periph_USART3: USART3 clock * @arg RCC_APB1Periph_UART4: UART4 clock @@ -2223,7 +2226,7 @@ void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) { /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) @@ -2239,7 +2242,7 @@ void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) /** * @brief Enables or disables the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before + * is disabled and the application software has to enable this clock before * using it. * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. * This parameter can be any combination of the following values: @@ -2261,7 +2264,7 @@ void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) * @arg RCC_APB2Periph_SPI5: SPI5 clock * @arg RCC_APB2Periph_SPI6: SPI6 clock * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices) - * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices) + * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices) * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices) * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices) @@ -2293,7 +2296,7 @@ void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset. * This parameter can be any combination of the following values: * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock * @arg RCC_AHB1Periph_GPIOC: GPIOC clock * @arg RCC_AHB1Periph_GPIOD: GPIOD clock * @arg RCC_AHB1Periph_GPIOE: GPIOE clock @@ -2301,15 +2304,15 @@ void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices) + * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices) * @arg RCC_AHB1Periph_CRC: CRC clock * @arg RCC_AHB1Periph_DMA1: DMA1 clock * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) + * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * @arg RCC_AHB1Periph_RNG: RNG clock for STM32F410xx devices + * @arg RCC_AHB1Periph_RNG: RNG clock for STM32F410xx devices * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -2363,7 +2366,7 @@ void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) /** * @brief Forces or releases AHB3 peripheral reset. * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. - * This parameter must be: + * This parameter must be: * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG, STM32F413_423xx and STM32F429x/439x devices) * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices) * @param NewState: new state of the specified peripheral reset. @@ -2400,11 +2403,11 @@ void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) * @arg RCC_APB1Periph_TIM12: TIM12 clock * @arg RCC_APB1Periph_TIM13: TIM13 clock * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices) + * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices) * @arg RCC_APB1Periph_WWDG: WWDG clock * @arg RCC_APB1Periph_SPI2: SPI2 clock * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices) + * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices) * @arg RCC_APB1Periph_USART2: USART2 clock * @arg RCC_APB1Periph_USART3: USART3 clock * @arg RCC_APB1Periph_UART4: UART4 clock @@ -2419,7 +2422,7 @@ void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) * @arg RCC_APB1Periph_PWR: PWR clock * @arg RCC_APB1Periph_DAC: DAC clock * @arg RCC_APB1Periph_UART7: UART7 clock - * @arg RCC_APB1Periph_UART8: UART8 clock + * @arg RCC_APB1Periph_UART8: UART8 clock * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -2452,7 +2455,7 @@ void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) * @arg RCC_APB2Periph_ADC3: ADC3 clock * @arg RCC_APB2Periph_SDIO: SDIO clock * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SPI4: SPI4 clock + * @arg RCC_APB2Periph_SPI4: SPI4 clock * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock * @arg RCC_APB2Periph_TIM9: TIM9 clock * @arg RCC_APB2Periph_TIM10: TIM10 clock @@ -2460,7 +2463,7 @@ void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) * @arg RCC_APB2Periph_SPI5: SPI5 clock * @arg RCC_APB2Periph_SPI6: SPI6 clock * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices) - * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices) + * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices) * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices) * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices) @@ -2495,7 +2498,7 @@ void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock * @arg RCC_AHB1Periph_GPIOC: GPIOC clock * @arg RCC_AHB1Periph_GPIOD: GPIOD clock * @arg RCC_AHB1Periph_GPIOE: GPIOE clock @@ -2503,13 +2506,13 @@ void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) * @arg RCC_AHB1Periph_CRC: CRC clock * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock * @arg RCC_AHB1Periph_DMA1: DMA1 clock * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) + * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock @@ -2547,7 +2550,7 @@ void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewSt * @arg RCC_AHB2Periph_CRYP: CRYP clock * @arg RCC_AHB2Periph_HASH: HASH clock * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock + * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -2575,9 +2578,9 @@ void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewSt * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. - * This parameter must be: + * This parameter must be: * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F413_423xx/STM32F429x/439x devices) - * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices) + * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices) * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -2615,11 +2618,11 @@ void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewSt * @arg RCC_APB1Periph_TIM12: TIM12 clock * @arg RCC_APB1Periph_TIM13: TIM13 clock * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices) + * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices) * @arg RCC_APB1Periph_WWDG: WWDG clock * @arg RCC_APB1Periph_SPI2: SPI2 clock * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices) + * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices) * @arg RCC_APB1Periph_USART2: USART2 clock * @arg RCC_APB1Periph_USART3: USART3 clock * @arg RCC_APB1Periph_UART4: UART4 clock @@ -2719,7 +2722,7 @@ void RCC_LSEModeConfig(uint8_t RCC_Mode) { /* Check the parameters */ assert_param(IS_RCC_LSE_MODE(RCC_Mode)); - + if(RCC_Mode == RCC_LSE_HIGHDRIVE_MODE) { SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); @@ -2768,7 +2771,7 @@ void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource) { /* Check the parameters */ assert_param(IS_RCC_DSI_CLOCKSOURCE(RCC_ClockSource)); - + if(RCC_ClockSource == RCC_DSICLKSource_PLLR) { SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL); @@ -2795,7 +2798,7 @@ void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource) { /* Check the parameters */ assert_param(IS_RCC_48MHZ_CLOCKSOURCE(RCC_ClockSource)); -#if defined(STM32F469_479xx) +#if defined(STM32F469_479xx) if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI) { SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL); @@ -2823,7 +2826,7 @@ void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource) CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL); } #else -#endif /* STM32F469_479xx */ +#endif /* STM32F469_479xx */ } /** @@ -2839,7 +2842,7 @@ void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource) { /* Check the parameters */ assert_param(IS_RCC_SDIO_CLOCKSOURCE(RCC_ClockSource)); -#if defined(STM32F469_479xx) +#if defined(STM32F469_479xx) if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK) { SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL); @@ -2858,7 +2861,7 @@ void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource) CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL); } #else -#endif /* STM32F469_479xx */ +#endif /* STM32F469_479xx */ } #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ @@ -2869,7 +2872,7 @@ void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource) * @param RCC_AHB1ClockGating: specifies the AHB1 clock gating. * This parameter can be any combination of the following values: * @arg RCC_AHB1ClockGating_APB1Bridge: AHB1 to APB1 clock - * @arg RCC_AHB1ClockGating_APB2Bridge: AHB1 to APB2 clock + * @arg RCC_AHB1ClockGating_APB2Bridge: AHB1 to APB2 clock * @arg RCC_AHB1ClockGating_CM4DBG: Cortex M4 ETM clock * @arg RCC_AHB1ClockGating_SPARE: Spare clock * @arg RCC_AHB1ClockGating_SRAM: SRAM controller clock @@ -2908,7 +2911,7 @@ void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource) { /* Check the parameters */ assert_param(IS_RCC_SPDIFRX_CLOCKSOURCE(RCC_ClockSource)); - + if(RCC_ClockSource == RCC_SPDIFRXCLKSource_PLLI2SP) { SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL); @@ -2932,7 +2935,7 @@ void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource) { /* Check the parameters */ assert_param(IS_RCC_CEC_CLOCKSOURCE(RCC_ClockSource)); - + if(RCC_ClockSource == RCC_CECCLKSource_LSE) { SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL); @@ -3001,12 +3004,12 @@ void RCC_MCO2Cmd(FunctionalState NewState) #endif /* STM32F410xx */ /** @defgroup RCC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions + * @brief Interrupts and flags management functions * -@verbatim +@verbatim =============================================================================== ##### Interrupts and flags management functions ##### - =============================================================================== + =============================================================================== @endverbatim * @{ @@ -3158,8 +3161,8 @@ ITStatus RCC_GetITStatus(uint8_t RCC_IT) * @arg RCC_IT_HSIRDY: HSI ready interrupt * @arg RCC_IT_HSERDY: HSE ready interrupt * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices) + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices) * @arg RCC_IT_CSS: Clock Security System interrupt * @retval None */ @@ -3175,18 +3178,18 @@ void RCC_ClearITPendingBit(uint8_t RCC_IT) /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Project/Src/rt-thread/board.c b/Project/Src/rt-thread/board.c index ba5a999..f7a6192 100644 --- a/Project/Src/rt-thread/board.c +++ b/Project/Src/rt-thread/board.c @@ -102,8 +102,10 @@ const libc_device_file *g_usart; // ʱӣ25mҪ֤usbΪ48mƵֻΪ168m void reconfig_clock(void) { - RCC_PLLConfig(RCC_PLLSource_HSE, 25, 336, 2, 7); - SystemCoreClock = 168000000; + RCC_ClocksTypeDef rcc = {0}; + // RCC_PLLConfig(RCC_PLLSource_HSE, 25, 336, 2, 7); + RCC_GetClocksFreq(&rcc); + SystemCoreClock = rcc.SYSCLK_Frequency; } /** diff --git a/Project/make.py b/Project/make.py index c29adbb..13fb4b4 100644 --- a/Project/make.py +++ b/Project/make.py @@ -41,8 +41,9 @@ DEF=[ '-D__packed=__attribute__((__packed__))', '-D__weak=__attribute__((weak))', '-D__RTTHREAD__', - '-DSOC_SERIES_STM32F4', - '-DPKG_TINYUSB_DEVICE_ENABLE', + # 使用usb时打开这个宏 系统时钟会被设置为168MHz USB时钟为48MHz + # 如果不打开这个宏 系统时钟会被设置为180MHz USB会通信异常 + '-D__USB_USB__', ] INC=[