From e03aefba9d46065eb06eef75990a1bd4cacf36bd Mon Sep 17 00:00:00 2001
From: ranchuan <ran.chuan@acp-ic.com>
Date: Wed, 9 Jul 2025 19:18:19 +0800
Subject: [PATCH] =?UTF-8?q?6502=5Fgcc=5Fexp.s=E5=AE=8C=E5=85=A8=E5=B1=95?=
 =?UTF-8?q?=E5=BC=80?=
MIME-Version: 1.0
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---
 Project/Src/NES/6502_gcc_exp.S | 1973 +++++++++++++++++++++++++++++---
 1 file changed, 1788 insertions(+), 185 deletions(-)

diff --git a/Project/Src/NES/6502_gcc_exp.S b/Project/Src/NES/6502_gcc_exp.S
index 3ec6fb7..97cb722 100644
--- a/Project/Src/NES/6502_gcc_exp.S
+++ b/Project/Src/NES/6502_gcc_exp.S
@@ -5,7 +5,7 @@
   .thumb
 
 
-  .include "6502mac_gcc.S"
+  .include "6502def.s"
 
 
 .extern NES_RAM
@@ -60,7 +60,16 @@ _00:
   ldr r12,=IRQ_VECTOR
   bl VecCont
 
-  fetch 7
+  // fetch 7
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #7
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #7*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
 
   .ltorg                 // 把常量放在这里
 
@@ -96,7 +105,17 @@ _01://    ORA ($nn,X)
     orr m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _05://    ORA $nn
   //  doZ
@@ -121,8 +140,18 @@ _05://    ORA $nn
     orr m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 3
-// ----------------------------------------------------------------------------
+  // fetch 3
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _06://    ASL $nn
 // ----------------------------------------------------------------------------
   //  doZ
@@ -161,8 +190,18 @@ _06://    ASL $nn
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch_c 5
-// ----------------------------------------------------------------------------
+  // fetch_c 5
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _08://    PHP
 // ----------------------------------------------------------------------------
   // encodeP (B+R)
@@ -180,8 +219,18 @@ _08://    PHP
   strb r0, [r2], #-1
   strb r2, [globalptr,#m6502_s]
 
-  fetch 3
-// ----------------------------------------------------------------------------
+  // fetch 3
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _09://    ORA #$nn
   //  doIMM
 .set _type, _IMM
@@ -204,14 +253,34 @@ _09://    ORA #$nn
     orr m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 2
-// ----------------------------------------------------------------------------
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _0A://    ASL
 // ----------------------------------------------------------------------------
   adds m6502_a,m6502_a,m6502_a
   mov m6502_nz,m6502_a,asr#24    // NZ
   orr cycles,cycles,#CYC_C    // Prepare C
-  fetch_c 2            // also subs carry
+  // fetch_c 2
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _0D://    ORA $nnnn
   // doABS
@@ -238,8 +307,18 @@ _0D://    ORA $nnnn
     orr m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 4
-// ----------------------------------------------------------------------------
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _0E://    ASL $nnnn
   // doABS
 .set _type, _ABS
@@ -279,8 +358,18 @@ _0E://    ASL $nnnn
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch_c 6
-// ----------------------------------------------------------------------------
+  // fetch_c 6
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _10://    BPL *
 // ----------------------------------------------------------------------------
   tst m6502_nz,#0x80000000
@@ -288,8 +377,18 @@ _10://    BPL *
   ITT EQ
   addeq m6502_pc,m6502_pc,r0
   subeq cycles,cycles,#256
-  fetch 2
-// ----------------------------------------------------------------------------
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _11://    ORA ($nn),Y
   //  doIIY
 .set _type, _ABS
@@ -318,8 +417,18 @@ _11://    ORA ($nn),Y
     orr m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 5
-// ----------------------------------------------------------------------------
+  // fetch 5
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _15://    ORA $nn,X
   //  doZIXf
 .set _type, _ZPI
@@ -344,8 +453,18 @@ _15://    ORA $nn,X
     orr m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 4
-// ----------------------------------------------------------------------------
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _16://    ASL $nn,X
   //  doZIXf
 .set _type, _ZPI
@@ -384,13 +503,32 @@ _16://    ASL $nn,X
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch_c 6
-// ----------------------------------------------------------------------------
+  // fetch_c 6
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _18://    CLC
-// ----------------------------------------------------------------------------
   bic cycles,cycles,#CYC_C
-  fetch 2
-// ----------------------------------------------------------------------------
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _19://    ORA $nnnn,Y
   //  doAIY
 .set _type, _ABS
@@ -417,8 +555,18 @@ _19://    ORA $nnnn,Y
     orr m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 4
-// ----------------------------------------------------------------------------
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _1D://    ORA $nnnn,X
   //  doAIX
 .set _type, _ABS
@@ -445,8 +593,18 @@ _1D://    ORA $nnnn,X
     orr m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 4
-// ----------------------------------------------------------------------------
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _1E://    ASL $nnnn,X
   //  doAIX
 .set _type, _ABS
@@ -487,10 +645,19 @@ _1E://    ASL $nnnn,X
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch_c 7
-// ----------------------------------------------------------------------------
+  // fetch_c 7
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #7
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #7*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _20://    JSR $nnnn
-// ----------------------------------------------------------------------------
   ldrb r2,[m6502_pc],#1
   ldr r1,[globalptr,#lastbank]
   sub r0,m6502_pc,r1
@@ -513,7 +680,17 @@ _20://    JSR $nnnn
     str r0, [globalptr,#lastbank]
     add m6502_pc, m6502_pc, r0
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _21://    AND ($nn,X)
   //  doIIX
@@ -545,7 +722,17 @@ _21://    AND ($nn,X)
     and m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _24://    BIT $nn
   //  doZ
@@ -574,8 +761,18 @@ _24://    BIT $nn
     and m6502_nz, r0, m6502_a, lsr #24
     orr m6502_nz, m6502_nz, r0, lsl #24
 
-  fetch 3
-// ----------------------------------------------------------------------------
+  // fetch 3
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _25://    AND $nn
   //  doZ
 .set _type, _ZP
@@ -599,8 +796,18 @@ _25://    AND $nn
     and m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 3
-// ----------------------------------------------------------------------------
+  // fetch 3
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _26://    ROL $nn
   //  doZ
 .set _type, _ZP
@@ -639,8 +846,18 @@ _26://    ROL $nn
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 5
-// ----------------------------------------------------------------------------
+  // fetch 5
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _28://    PLP
   // pop8 r0
     ldrb r2, [globalptr,#m6502_s]
@@ -656,7 +873,17 @@ _28://    PLP
     bic m6502_nz, r0, #0xFD
     eor m6502_nz, m6502_nz, #Z
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _29://    AND #$nn
   //  doIMM
@@ -680,7 +907,17 @@ _29://    AND #$nn
     and m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _2A://    ROL
   movs cycles,cycles,lsr#1    // get C
@@ -689,7 +926,17 @@ _2A://    ROL
   adds m6502_a,m6502_a,m6502_a
   mov m6502_nz,m6502_a,asr#24    // NZ
   adc cycles,cycles,cycles    // Set C
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _2C://    BIT $nnnn
   // doABS
@@ -720,8 +967,18 @@ _2C://    BIT $nnnn
     and m6502_nz, r0, m6502_a, lsr #24
     orr m6502_nz, m6502_nz, r0, lsl #24
 
-  fetch 4
-// ----------------------------------------------------------------------------
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _2D://    AND $nnnn
   // doABS
 .set _type, _ABS
@@ -747,8 +1004,18 @@ _2D://    AND $nnnn
     and m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 4
-// ----------------------------------------------------------------------------
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
+
 _2E://    ROL $nnnn
   // doABS
 .set _type, _ABS
@@ -789,7 +1056,17 @@ _2E://    ROL $nnnn
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _30://    BMI *
   tst m6502_nz,#0x80000000
@@ -797,7 +1074,17 @@ _30://    BMI *
   ITT NE
   addne m6502_pc,m6502_pc,r0
   subne cycles,cycles,#256
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _31://    AND ($nn),Y
   //  doIIY
@@ -827,7 +1114,17 @@ _31://    AND ($nn),Y
     and m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 5
+  // fetch 5
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _35://    AND $nn,X
   //  doZIXf
@@ -853,7 +1150,17 @@ _35://    AND $nn,X
     and m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _36://    ROL $nn,X
   //  doZIXf
@@ -894,11 +1201,31 @@ _36://    ROL $nn,X
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _38://    SEC
   orr cycles,cycles,#CYC_C
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _39://    AND $nnnn,Y
   //  doAIY
@@ -926,7 +1253,17 @@ _39://    AND $nnnn,Y
     and m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _3D://    AND $nnnn,X
   //  doAIX
@@ -954,7 +1291,17 @@ _3D://    AND $nnnn,X
     and m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _3E://    ROL $nnnn,X
   //  doAIX
@@ -997,7 +1344,17 @@ _3E://    ROL $nnnn,X
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 7
+  // fetch 7
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #7
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #7*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _40://    RTI
   // pop8 r0
@@ -1032,7 +1389,17 @@ _40://    RTI
     str r0, [globalptr,#lastbank]
     add m6502_pc, m6502_pc, r0
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _41://    EOR ($nn,X)
   //  doIIX
@@ -1064,7 +1431,17 @@ _41://    EOR ($nn,X)
     eor m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _45://    EOR $nn
   //  doZ
@@ -1089,7 +1466,17 @@ _45://    EOR $nn
     eor m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 3
+  // fetch 3
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _46://    LSR $nn
   //  doZ
@@ -1126,7 +1513,17 @@ _46://    LSR $nn
         strb m6502_nz, [cpu_zpage, r1]
     .endif
 
-  fetch_c 5
+  // fetch_c 5
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _48://    PHA
   mov r0,m6502_a,lsr#24
@@ -1136,7 +1533,17 @@ _48://    PHA
   strb r0, [r2], #-1
   strb r2, [globalptr,#m6502_s]
 
-  fetch 3
+  // fetch 3
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _49://    EOR #$nn
   //  doIMM
@@ -1160,13 +1567,33 @@ _49://    EOR #$nn
     eor m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _4A://    LSR
   movs m6502_nz,m6502_a,lsr#25  // Z, N=0
   mov m6502_a,m6502_nz,lsl#24    // result without garbage
   orr cycles,cycles,#CYC_C    // Prepare C
-  fetch_c 2
+  // fetch_c 2
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _4C://    JMP $nnnn
   ldrb r0,[m6502_pc],#1
@@ -1180,7 +1607,17 @@ _4C://    JMP $nnnn
     str r0, [globalptr,#lastbank]
     add m6502_pc, m6502_pc, r0
 
-  fetch 3
+  // fetch 3
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _4D://    EOR $nnnn
   // doABS
@@ -1207,7 +1644,17 @@ _4D://    EOR $nnnn
     eor m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _4E://    LSR $nnnn
   // doABS
@@ -1246,7 +1693,17 @@ _4E://    LSR $nnnn
         strb m6502_nz, [cpu_zpage, r1]
     .endif
 
-  fetch_c 6
+  // fetch_c 6
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _50://    BVC *
   tst cycles,#CYC_V
@@ -1254,7 +1711,17 @@ _50://    BVC *
   ITT EQ
   addeq m6502_pc,m6502_pc,r0
   subeq cycles,cycles,#256
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _51://    EOR ($nn),Y
   //  doIIY
@@ -1284,7 +1751,17 @@ _51://    EOR ($nn),Y
     eor m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 5
+  // fetch 5
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _55://    EOR $nn,X
   //  doZIXf
@@ -1310,7 +1787,17 @@ _55://    EOR $nn,X
     eor m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _56://    LSR $nn,X
   //  doZIXf
@@ -1348,11 +1835,31 @@ _56://    LSR $nn,X
         strb m6502_nz, [cpu_zpage, r1]
     .endif
 
-  fetch_c 6
+  // fetch_c 6
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _58://    CLI
   bic cycles,cycles,#CYC_I
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _59://    EOR $nnnn,Y
   //  doAIY
@@ -1380,7 +1887,17 @@ _59://    EOR $nnnn,Y
     eor m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _5D://    EOR $nnnn,X
   //  doAIX
@@ -1408,7 +1925,17 @@ _5D://    EOR $nnnn,X
     eor m6502_a, m6502_a, r0, lsl #24
     mov m6502_nz, m6502_a, asr #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _5E://    LSR $nnnn,X
   //  doAIX
@@ -1448,7 +1975,17 @@ _5E://    LSR $nnnn,X
         strb m6502_nz, [cpu_zpage, r1]
     .endif
 
-  fetch_c 7
+  // fetch_c 7
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #7
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #7*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _60://    RTS
   //  pop16
@@ -1470,7 +2007,17 @@ _60://    RTS
     str r0, [globalptr,#lastbank]
     add m6502_pc, m6502_pc, r0
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _61://    ADC ($nn,X)
   //  doIIX
@@ -1508,7 +2055,17 @@ _61://    ADC ($nn,X)
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch_c 6
+  // fetch_c 6
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _65://    ADC $nn
   //  doZ
@@ -1539,7 +2096,17 @@ _65://    ADC $nn
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch_c 3
+  // fetch_c 3
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _66://    ROR $nn
   //  doZ
@@ -1581,7 +2148,17 @@ _66://    ROR $nn
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 5
+  // fetch 5
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _68://    PLA
   // pop8 m6502_nz
@@ -1592,7 +2169,17 @@ _68://    PLA
     ldrsb m6502_nz, [cpu_zpage, r2]
 
   mov m6502_a,m6502_nz,lsl#24
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _69://    ADC #$nn
   //  doIMM
@@ -1622,7 +2209,17 @@ _69://    ADC #$nn
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch_c 2
+  // fetch_c 2
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _6A://    ROR
   movs cycles,cycles,lsr#1    // get C
@@ -1630,7 +2227,17 @@ _6A://    ROR
   movs m6502_nz,m6502_a,asr#24  // NZ
   and m6502_a,m6502_a,#0xff000000
   adc cycles,cycles,cycles    // Set C
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _6C://    JMP ($nnnn)  JMP ($data16) 间接寻址 *********************************
   // doABS
@@ -1655,7 +2262,17 @@ _6C://    JMP ($nnnn)  JMP ($data16) 
     str r0, [globalptr,#lastbank]
     add m6502_pc, m6502_pc, r0
 
-  fetch 5
+  // fetch 5
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _6D://    ADC $nnnn
   // doABS
@@ -1688,7 +2305,17 @@ _6D://    ADC $nnnn
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch_c 4
+  // fetch_c 4
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _6E://    ROR $nnnn
   // doABS
@@ -1732,7 +2359,17 @@ _6E://    ROR $nnnn
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _70://    BVS *
   tst cycles,#CYC_V
@@ -1740,7 +2377,17 @@ _70://    BVS *
   ITT NE
   addne m6502_pc,m6502_pc,r0
   subne cycles,cycles,#256
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _71://    ADC ($nn),Y
   //  doIIY
@@ -1776,7 +2423,17 @@ _71://    ADC ($nn),Y
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch_c 5
+  // fetch_c 5
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _75://    ADC $nn,X
   //  doZIXf
@@ -1808,7 +2465,17 @@ _75://    ADC $nn,X
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch_c 4
+  // fetch_c 4
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _76://    ROR $nn,X
   //  doZIXf
@@ -1851,11 +2518,31 @@ _76://    ROR $nn,X
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _78://    SEI
   orr cycles,cycles,#CYC_I
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _79://    ADC $nnnn,Y
   //  doAIY
@@ -1889,7 +2576,17 @@ _79://    ADC $nnnn,Y
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch_c 4
+  // fetch_c 4
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _7D://    ADC $nnnn,X
   //  doAIX
@@ -1923,7 +2620,17 @@ _7D://    ADC $nnnn,X
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch_c 4
+  // fetch_c 4
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _7E://    ROR $nnnn,X
   //  doAIX
@@ -1968,7 +2675,17 @@ _7E://    ROR $nnnn,X
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 7
+  // fetch 7
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #7
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #7*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _81://    STA ($nn,X)
   //  doIIX
@@ -1998,7 +2715,17 @@ _81://    STA ($nn,X)
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _84://    STY $nn
   //  doZ
@@ -2021,7 +2748,17 @@ _84://    STY $nn
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 3
+  // fetch 3
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _85://    STA $nn
   //  doZ
@@ -2044,7 +2781,17 @@ _85://    STA $nn
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 3
+  // fetch 3
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _86://    STX $nn
   //  doZ
@@ -2067,17 +2814,47 @@ _86://    STX $nn
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 3
+  // fetch 3
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _88://    DEY
   sub m6502_y,m6502_y,#0x01000000
   mov m6502_nz,m6502_y,asr#24
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _8A://    TXA
   mov m6502_a,m6502_x
   mov m6502_nz,m6502_x,asr#24
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _8C://    STY $nnnn
   // doABS
@@ -2102,7 +2879,17 @@ _8C://    STY $nnnn
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _8D://    STA $nnnn
   // doABS
@@ -2127,7 +2914,17 @@ _8D://    STA $nnnn
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _8E://    STX $nnnn
   // doABS
@@ -2152,7 +2949,17 @@ _8E://    STX $nnnn
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _90://    BCC *
   tst cycles,#CYC_C      // Test Carry
@@ -2160,7 +2967,17 @@ _90://    BCC *
   ITT EQ
   addeq m6502_pc,m6502_pc,r0
   subeq cycles,cycles,#256
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _91://    STA ($nn),Y
   //  doIIY
@@ -2188,7 +3005,17 @@ _91://    STA ($nn),Y
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _94://    STY $nn,X
   //  doZIXf
@@ -2212,7 +3039,17 @@ _94://    STY $nn,X
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _95://    STA $nn,X
   //  doZIXf
@@ -2236,7 +3073,17 @@ _95://    STA $nn,X
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _96://    STX $nn,Y
   //  doZIYf
@@ -2260,12 +3107,32 @@ _96://    STX $nn,Y
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _98://    TYA
   mov m6502_a,m6502_y
   mov m6502_nz,m6502_y,asr#24
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _99://    STA $nnnn,Y
   //  doAIY
@@ -2291,12 +3158,32 @@ _99://    STA $nnnn,Y
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 5
+  // fetch 5
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _9A://    TXS
   mov r0,m6502_x,lsr#24
   strb r0,[globalptr,#m6502_s]
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _9D://    STA $nnnn,X
   //  doAIX
@@ -2322,7 +3209,17 @@ _9D://    STA $nnnn,X
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 5
+  // fetch 5
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _A0://    LDY #$nn
   //  doIMM
@@ -2343,7 +3240,17 @@ _A0://    LDY #$nn
     .endif
     mov m6502_y, m6502_nz, lsl #24
 
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _A1://    LDA ($nn,X)
   //  doIIX
@@ -2372,7 +3279,17 @@ _A1://    LDA ($nn,X)
     .endif
     mov m6502_a, m6502_nz, lsl #24
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _A2://    LDX #$nn
   //  doIMM
@@ -2393,7 +3310,17 @@ _A2://    LDX #$nn
     .endif
     mov m6502_x, m6502_nz, lsl #24
 
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _A4://    LDY $nn
   //  doZ
@@ -2415,7 +3342,17 @@ _A4://    LDY $nn
     .endif
     mov m6502_y, m6502_nz, lsl #24
 
-  fetch 3
+  // fetch 3
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _A5://    LDA $nn
   //  doZ
@@ -2437,7 +3374,17 @@ _A5://    LDA $nn
     .endif
     mov m6502_a, m6502_nz, lsl #24
 
-  fetch 3
+  // fetch 3
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _A6://    LDX $nn
   //  doZ
@@ -2459,12 +3406,32 @@ _A6://    LDX $nn
     .endif
     mov m6502_x, m6502_nz, lsl #24
 
-  fetch 3
+  // fetch 3
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _A8://    TAY
   mov m6502_y,m6502_a
   mov m6502_nz,m6502_y,asr#24
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _A9://    LDA #$nn
   //  doIMM
@@ -2485,12 +3452,32 @@ _A9://    LDA #$nn
     .endif
     mov m6502_a, m6502_nz, lsl #24
 
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _AA://    TAX
   mov m6502_x,m6502_a
   mov m6502_nz,m6502_x,asr#24
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _AC://    LDY $nnnn
   // doABS
@@ -2514,7 +3501,17 @@ _AC://    LDY $nnnn
     .endif
     mov m6502_y, m6502_nz, lsl #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _AD://    LDA $nnnn
   // doABS
@@ -2538,7 +3535,17 @@ _AD://    LDA $nnnn
     .endif
     mov m6502_a, m6502_nz, lsl #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _AE://    LDX $nnnn
   // doABS
@@ -2562,7 +3569,17 @@ _AE://    LDX $nnnn
     .endif
     mov m6502_x, m6502_nz, lsl #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _B0://    BCS *
   tst cycles,#CYC_C      // Test Carry
@@ -2570,7 +3587,17 @@ _B0://    BCS *
   ITT NE
   addne m6502_pc,m6502_pc,r0
   subne cycles,cycles,#256
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _B1://    LDA ($nn),Y
   //  doIIY
@@ -2597,7 +3624,17 @@ _B1://    LDA ($nn),Y
     .endif
     mov m6502_a, m6502_nz, lsl #24
 
-  fetch 5
+  // fetch 5
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _B4://    LDY $nn,X
   //  doZIX
@@ -2621,7 +3658,17 @@ _B4://    LDY $nn,X
     .endif
     mov m6502_y, m6502_nz, lsl #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _B5://    LDA $nn,X
   //  doZIX
@@ -2645,7 +3692,17 @@ _B5://    LDA $nn,X
     .endif
     mov m6502_a, m6502_nz, lsl #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _B6://    LDX $nn,Y
   // doZIY
@@ -2669,11 +3726,31 @@ _B6://    LDX $nn,Y
     .endif
     mov m6502_x, m6502_nz, lsl #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _B8://    CLV
   bic cycles,cycles,#CYC_V
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _B9://    LDA $nnnn,Y
   //  doAIY
@@ -2698,13 +3775,33 @@ _B9://    LDA $nnnn,Y
     .endif
     mov m6502_a, m6502_nz, lsl #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _BA://    TSX
   ldrb m6502_x,[globalptr,#m6502_s]
   mov m6502_x,m6502_x,lsl#24
   mov m6502_nz,m6502_x,asr#24
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _BC://    LDY $nnnn,X
   //  doAIX
@@ -2729,7 +3826,17 @@ _BC://    LDY $nnnn,X
     .endif
     mov m6502_y, m6502_nz, lsl #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _BD://    LDA $nnnn,X
   //  doAIX
@@ -2754,7 +3861,17 @@ _BD://    LDA $nnnn,X
     .endif
     mov m6502_a, m6502_nz, lsl #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _BE://    LDX $nnnn,Y
   //  doAIY
@@ -2779,7 +3896,17 @@ _BE://    LDX $nnnn,Y
     .endif
     mov m6502_x, m6502_nz, lsl #24
 
-  fetch 4
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _C0://    CPY #$nn
   //  doIMM
@@ -2804,7 +3931,17 @@ _C0://    CPY #$nn
     mov m6502_nz, m6502_nz, asr #24
     orr cycles, cycles, #CYC_C
 
-  fetch_c 2
+  // fetch_c 2
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _C1://    CMP ($nn,X)
   //  doIIX
@@ -2837,7 +3974,17 @@ _C1://    CMP ($nn,X)
     mov m6502_nz, m6502_nz, asr #24
     orr cycles, cycles, #CYC_C
 
-  fetch_c 6
+  // fetch_c 6
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _C4://    CPY $nn
   //  doZ
@@ -2863,7 +4010,17 @@ _C4://    CPY $nn
     mov m6502_nz, m6502_nz, asr #24
     orr cycles, cycles, #CYC_C
 
-  fetch_c 3
+  // fetch_c 3
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _C5://    CMP $nn
   //  doZ
@@ -2889,7 +4046,17 @@ _C5://    CMP $nn
     mov m6502_nz, m6502_nz, asr #24
     orr cycles, cycles, #CYC_C
 
-  fetch_c 3
+  // fetch_c 3
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _C6://    DEC $nn
   //  doZ
@@ -2927,12 +4094,32 @@ _C6://    DEC $nn
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 5
+  // fetch 5
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _C8://    INY
   add m6502_y,m6502_y,#0x01000000
   mov m6502_nz,m6502_y,asr#24
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _C9://    CMP #$nn
   //  doIMM
@@ -2957,12 +4144,32 @@ _C9://    CMP #$nn
     mov m6502_nz, m6502_nz, asr #24
     orr cycles, cycles, #CYC_C
 
-  fetch_c 2
+  // fetch_c 2
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _CA://    DEX
   sub m6502_x,m6502_x,#0x01000000
   mov m6502_nz,m6502_x,asr#24
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _CC://    CPY $nnnn
   // doABS
@@ -2990,7 +4197,17 @@ _CC://    CPY $nnnn
     mov m6502_nz, m6502_nz, asr #24
     orr cycles, cycles, #CYC_C
 
-  fetch_c 4
+  // fetch_c 4
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _CD://    CMP $nnnn
   // doABS
@@ -3018,7 +4235,17 @@ _CD://    CMP $nnnn
     mov m6502_nz, m6502_nz, asr #24
     orr cycles, cycles, #CYC_C
 
-  fetch_c 4
+  // fetch_c 4
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _CE://    DEC $nnnn
   // doABS
@@ -3058,7 +4285,17 @@ _CE://    DEC $nnnn
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _D0://    BNE *
   tst m6502_nz,#0xff
@@ -3066,7 +4303,17 @@ _D0://    BNE *
   ITT NE
   addne m6502_pc,m6502_pc,r0
   subne cycles,cycles,#256
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _D1://    CMP ($nn),Y
   //  doIIY
@@ -3097,7 +4344,17 @@ _D1://    CMP ($nn),Y
     mov m6502_nz, m6502_nz, asr #24
     orr cycles, cycles, #CYC_C
 
-  fetch_c 5
+  // fetch_c 5
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _D5://    CMP $nn,X
   //  doZIXf
@@ -3124,7 +4381,17 @@ _D5://    CMP $nn,X
     mov m6502_nz, m6502_nz, asr #24
     orr cycles, cycles, #CYC_C
 
-  fetch_c 4
+  // fetch_c 4
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _D6://    DEC $nn,X
   //  doZIXf
@@ -3163,11 +4430,31 @@ _D6://    DEC $nn,X
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _D8://    CLD
   bic cycles,cycles,#CYC_D
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _D9://    CMP $nnnn,Y
   //  doAIY
@@ -3197,7 +4484,17 @@ _D9://    CMP $nnnn,Y
     mov m6502_nz, m6502_nz, asr #24
     orr cycles, cycles, #CYC_C
 
-  fetch_c 4
+  // fetch_c 4
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _DD://    CMP $nnnn,X
   //  doAIX
@@ -3226,7 +4523,17 @@ _DD://    CMP $nnnn,X
     mov m6502_nz, m6502_nz, asr #24
     orr cycles, cycles, #CYC_C
 
-  fetch_c 4
+  // fetch_c 4
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _DE://    DEC $nnnn,X
   //  doAIX
@@ -3267,7 +4574,17 @@ _DE://    DEC $nnnn,X
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 7
+  // fetch 7
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #7
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #7*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _E0://    CPX #$nn
   //  doIMM
@@ -3292,7 +4609,17 @@ _E0://    CPX #$nn
     mov m6502_nz, m6502_nz, asr #24
     orr cycles, cycles, #CYC_C
 
-  fetch_c 2
+  // fetch_c 2
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _E1://    SBC ($nn,X)
   //  doIIX
@@ -3329,7 +4656,17 @@ _E1://    SBC ($nn,X)
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch_c 6
+  // fetch_c 6
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _E4://    CPX $nn
   //  doZ
@@ -3355,7 +4692,17 @@ _E4://    CPX $nn
     mov m6502_nz, m6502_nz, asr #24
     orr cycles, cycles, #CYC_C
 
-  fetch_c 3
+  // fetch_c 3
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _E5://    SBC $nn
   //  doZ
@@ -3385,7 +4732,17 @@ _E5://    SBC $nn
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch_c 3
+  // fetch_c 3
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #3
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #3*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _E6://    INC $nn
   //  doZ
@@ -3423,12 +4780,32 @@ _E6://    INC $nn
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 5
+  // fetch 5
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _E8://    INX
   add m6502_x,m6502_x,#0x01000000
   mov m6502_nz,m6502_x,asr#24
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _E9://    SBC #$nn
   //  doIMM
@@ -3457,10 +4834,30 @@ _E9://    SBC #$nn
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch_c 2
+  // fetch_c 2
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _EA://    NOP
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _EC://    CPX $nnnn
   // doABS
@@ -3488,7 +4885,17 @@ _EC://    CPX $nnnn
     mov m6502_nz, m6502_nz, asr #24
     orr cycles, cycles, #CYC_C
 
-  fetch_c 4
+  // fetch_c 4
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _ED://    SBC $nnnn
   // doABS
@@ -3520,7 +4927,17 @@ _ED://    SBC $nnnn
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch_c 4
+  // fetch_c 4
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _EE://    INC $nnnn
   // doABS
@@ -3560,7 +4977,17 @@ _EE://    INC $nnnn
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _F0://    BEQ *
   tst m6502_nz,#0xff
@@ -3568,7 +4995,17 @@ _F0://    BEQ *
   ITT EQ
   addeq m6502_pc,m6502_pc,r0
   subeq cycles,cycles,#256
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _F1://    SBC ($nn),Y
   //  doIIY
@@ -3603,7 +5040,17 @@ _F1://    SBC ($nn),Y
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch_c 5
+  // fetch_c 5
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _F5://    SBC $nn,X
   //  doZIXf
@@ -3634,7 +5081,17 @@ _F5://    SBC $nn,X
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch_c 4
+  // fetch_c 4
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _F6://    INC $nn,X
   //  doZIXf
@@ -3673,11 +5130,31 @@ _F6://    INC $nn,X
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 6
+  // fetch 6
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #6
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #6*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _F8://    SED
   orr cycles,cycles,#CYC_D
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _F9://    SBC $nnnn,Y
   //  doAIY
@@ -3710,7 +5187,17 @@ _F9://    SBC $nnnn,Y
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch_c 4
+  // fetch_c 4
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _FD://    SBC $nnnn,X
   //  doAIX
@@ -3743,7 +5230,17 @@ _FD://    SBC $nnnn,X
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch_c 4
+  // fetch_c 4
+    ldr r0, [globalptr,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    sbcs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _FE://    INC $nnnn,X
   //  doAIX
@@ -3784,7 +5281,17 @@ _FE://    INC $nnnn,X
     strb r0, [cpu_zpage, r1]
     .endif
 
-  fetch 7
+  // fetch 7
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #7
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #7*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 
 // ***********************************************************以下指令是一些HACK游戏需要******************
@@ -3819,7 +5326,17 @@ _FF://   ISB $????,X  
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch 5      // ADD_CYCLE(5)//                                   // DT .... DATA
+  // fetch 5
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _FB://   ISB $????,X  加的，不确定正确    激龟忍者传2无敌HACK需要
   //  doAIY
@@ -3852,11 +5369,31 @@ _FB://   ISB $????,X  
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch 5      // ADD_CYCLE(5)//
+  // fetch 5
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _14://       加的，不确定正确          激龟忍者传2无敌HACK需要
   add m6502_pc,m6502_pc,#1  // R.PC++//
-  fetch 4                    // ADD_CYCLE(4)//
+  // fetch 4
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #4
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #4*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _67://  // RRA $??                 帝国战机无敌HACK需要
   //  doZ
@@ -3887,7 +5424,17 @@ _67://  // RRA $??                 
     IT VC
     bicvc cycles, cycles, #CYC_V
 
-  fetch 5       // ADD_CYCLE(5)//
+  // fetch 5
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _03://  // SLO ($??,X)              帝国战机无敌HACK需要
   //  doIIX
@@ -3901,23 +5448,51 @@ _03://  // SLO ($??,X)              
     ldrb r1, [cpu_zpage, r1]
     orr addy, addy, r1, lsl #8
 
-  fetch 8//   // ADD_CYCLE(8)//
+  // fetch 8
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #8
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #8*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 _07://  // SLO $??
   //  doZ
 .set _type, _ZP
     ldrb addy, [m6502_pc], #1
 
-        // SLO()//
-        // MW_ZP()//
-  fetch 5    // ADD_CYCLE(5)//
+  // fetch 5
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #5
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #5*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 
 _xx://   ???          // invalid opcode  无效的操作码
   mov r1,#1           // 不用debug可以直接注译这两行
     bl debug_6502
 
-  fetch 2
+  // fetch 2
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #2
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #2*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 
 
@@ -3938,7 +5513,16 @@ run6502:
   ldrb r0,[globalptr,#cpuirqf]  // cpu中断标志
   cmp r0,#0x01
   beq CheckI                    // EQ       相等(EQual) irq6502;
-  fetch 0                       // 提取操作码并运行
+  // fetch 0
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #0
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #0*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
 
 exit_run:
   ldrb r0,[globalptr,#cpunmif]  // cpu中断标志
@@ -3964,7 +5548,16 @@ NMI6502:
 
 
 default_scanlinehook:
-  fetch 0
+  // fetch 0
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #0
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #0*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
 
 
 CheckI:
@@ -3977,7 +5570,17 @@ irq6502:
 	str r0,[globalptr,#cpuirqf]             // 清除cpu中断标志
 	ldr r12,=IRQ_VECTOR
 	bl Vec6502
-	fetch 7
+  // fetch 7
+    ldr r0, [r10,#clocksh]
+    add r0, r0, #7
+    str r0, [globalptr,#clocksh]
+    ldr r1, [globalptr,#opz]
+    subs cycles, cycles, #7*256
+    ITT PL
+    ldrbpl r0, [m6502_pc], #1
+    ldrpl pc, [r1, r0, lsl #2]
+    ldr pc, [globalptr,#nexttimeout]
+
 
 Vec6502:
   ldr r0,[globalptr,lastbank]