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217
Project/Src/rt-thread/libcpu/mips/x1000/cache.c
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217
Project/Src/rt-thread/libcpu/mips/x1000/cache.c
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/*
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* File : cache.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2016/11/02 Urey the first version
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*/
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#include <rtthread.h>
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#include <board.h>
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#include <rthw.h>
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#include "../common/mips.h"
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#define CONFIG_SYS_DCACHE_SIZE 16384
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#define CONFIG_SYS_ICACHE_SIZE 16384
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#define K0_TO_K1() \
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do { \
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unsigned long __k0_addr; \
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\
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__asm__ __volatile__( \
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"la %0, 1f\n\t" \
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"or %0, %0, %1\n\t" \
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"jr %0\n\t" \
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"nop\n\t" \
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"1: nop\n" \
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: "=&r"(__k0_addr) \
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: "r" (0x20000000) ); \
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} while(0)
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#define K1_TO_K0() \
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do { \
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unsigned long __k0_addr; \
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__asm__ __volatile__( \
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"nop;nop;nop;nop;nop;nop;nop\n\t" \
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"la %0, 1f\n\t" \
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"jr %0\n\t" \
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"nop\n\t" \
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"1: nop\n" \
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: "=&r" (__k0_addr)); \
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} while (0)
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#define INVALIDATE_BTB() \
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do { \
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unsigned long tmp; \
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__asm__ __volatile__( \
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".set mips32\n\t" \
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"mfc0 %0, $16, 7\n\t" \
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"nop\n\t" \
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"ori %0, 2\n\t" \
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"mtc0 %0, $16, 7\n\t" \
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"nop\n\t" \
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".set mips2\n\t" \
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: "=&r" (tmp)); \
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} while (0)
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#define __sync() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips2\n\t" \
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"sync\n\t" \
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".set pop" \
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: /* no output */ \
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: /* no input */ \
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: "memory")
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#if defined(JZ4775) || defined(X1000)
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#define SYNC_WB() \
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do { \
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__asm__ __volatile__ ( \
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"sync\n\t" \
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"lw $0, %0\n\t" \
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: \
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:"m"(*(int *)0xa0000000) \
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:"memory"); \
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} while (0)
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#else
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#error "not define sync wb"
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#define SYNC_WB() __asm__ __volatile__ ("sync")
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#endif
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#undef cache_op
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#define cache_op(op, addr) \
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__asm__ __volatile__( \
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".set push\n" \
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".set noreorder\n" \
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".set mips3\n" \
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"cache %0, %1\n" \
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".set pop\n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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void rt_hw_dcache_flush_line(rt_uint32_t addr)
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{
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cache_op(HIT_WRITEBACK_INV_D, addr);
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SYNC_WB();
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}
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void rt_hw_dcache_flush_range(rt_uint32_t start_addr, rt_uint32_t size)
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{
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rt_uint32_t lsize = CONFIG_SYS_CACHELINE_SIZE;
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rt_uint32_t addr = start_addr & ~(lsize - 1);
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rt_uint32_t aend = (start_addr + size - 1) & ~(lsize - 1);
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rt_uint32_t writebuffer;
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for (; addr <= aend; addr += lsize)
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{
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cache_op(HIT_WRITEBACK_INV_D, addr);
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}
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SYNC_WB();
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}
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void rt_hw_dcache_flush_all(void)
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{
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rt_uint32_t addr;
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for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE)
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{
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cache_op(INDEX_WRITEBACK_INV_D, addr);
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}
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SYNC_WB();
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}
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void rt_hw_dcache_invalidate_range(rt_uint32_t start_addr,rt_uint32_t size)
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{
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rt_uint32_t lsize = CONFIG_SYS_CACHELINE_SIZE;
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rt_uint32_t addr = start_addr & ~(lsize - 1);
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rt_uint32_t aend = (start_addr + size - 1) & ~(lsize - 1);
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for (; addr <= aend; addr += lsize)
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cache_op(HIT_INVALIDATE_D, addr);
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}
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void rt_hw_dcache_invalidate_all(void)
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{
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rt_uint32_t addr;
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for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE)
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{
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cache_op(INDEX_STORE_TAG_D, addr);
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}
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SYNC_WB();
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}
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void rt_hw_icache_flush_line(rt_uint32_t addr)
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{
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cache_op(HIT_INVALIDATE_I, addr);
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}
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void rt_hw_icache_flush_all(void)
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{
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rt_uint32_t addr;
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asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
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asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
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for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE)
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{
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cache_op(INDEX_STORE_TAG_I, addr);
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}
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INVALIDATE_BTB();
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}
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void rt_hw_icache_invalidate_all(void)
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{
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rt_uint32_t i;
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K0_TO_K1();
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asm volatile (".set noreorder\n"
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".set mips32\n\t"
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"mtc0\t$0,$28\n\t"
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"mtc0\t$0,$29\n"
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".set mips0\n"
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".set reorder\n");
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for (i = CKSEG0; i < CKSEG0 + CONFIG_SYS_ICACHE_SIZE; i += CONFIG_SYS_CACHELINE_SIZE)
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cache_op(INDEX_STORE_TAG_I, i);
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K1_TO_K0();
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INVALIDATE_BTB();
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}
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void rt_hw_flush_cache_all(void)
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{
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rt_hw_dcache_flush_all();
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rt_hw_icache_flush_all();
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}
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