57 lines
2.0 KiB
C
57 lines
2.0 KiB
C
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef DWC2_GD32_H_
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#define DWC2_GD32_H_
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// for remote wakeup delay
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#define __NOP() __asm volatile ("nop")
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// These numbers are the same for the whole GD32VF103 family.
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#define OTG_FS_IRQn 86
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#define EP_MAX_FS 4
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#define EP_FIFO_SIZE_FS 1280
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// The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local
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// Interrupt Controller by Nuclei. It is nearly API compatible to the
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// NVIC used by ARM MCUs.
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#define ECLIC_INTERRUPT_ENABLE_BASE 0xD2001001UL
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#define NVIC_EnableIRQ __eclic_enable_interrupt
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#define NVIC_DisableIRQ __eclic_disable_interrupt
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static inline void __eclic_enable_interrupt (uint32_t irq) {
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*(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 1;
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}
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static inline void __eclic_disable_interrupt (uint32_t irq){
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*(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 0;
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}
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#endif /* DWC2_GD32_H_ */
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