128 lines
4.6 KiB
C
128 lines
4.6 KiB
C
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/**
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**************************************************************************
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* @file at32f423_clock.c
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* @brief system clock config program
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* includes ------------------------------------------------------------------*/
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#include "at32f423_clock.h"
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/**
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* @brief system clock config program
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* @note the system clock is configured as follow:
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* system clock (sclk) = (hext * pll_ns)/(pll_ms * pll_fr) / 2
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* system clock source = pll (hext)
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* - hext = HEXT_VALUE
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* - sclk = 144000000
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* - ahbdiv = 1
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* - ahbclk = 144000000
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* - apb2div = 1
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* - apb2clk = 144000000
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* - apb1div = 2
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* - apb1clk = 72000000
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* - pll_ns = 72
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* - pll_ms = 1
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* - pll_fr = 1
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* @param none
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* @retval none
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*/
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void system_clock_config(void)
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{
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/* reset crm */
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crm_reset();
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/* config flash psr register */
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flash_psr_set(FLASH_WAIT_CYCLE_4);
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/* enable pwc periph clock */
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crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
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/* ensure system clock to highest, set power ldo output voltage to 1.3v */
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pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3);
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crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
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/* wait till hext is ready */
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while(crm_hext_stable_wait() == ERROR)
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{
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}
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/* config pll clock resource
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common frequency config list: pll source selected hick or hext(8mhz)
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_____________________________________________________________________________
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| sysclk | 150 | 144 | 120 | 108 | 96 | 72 | 36 |
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|________|_________|_________|_________|_________|_________|_________________|
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| | | | | | | | |
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|pll_ns | 75 | 72 | 120 | 108 | 96 | 72 | 72 |
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|pll_ms | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
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|pll_fr | FR_2 | FR_2 | FR_4 | FR_4 | FR_4 | FR_4 | FR_8 |
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|________|_________|_________|_________|_________|_________|________|________|
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if pll clock source selects hext with other frequency values, or configure pll to other
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frequency values, please use the at32 new clock configuration tool for configuration. */
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crm_pll_config(CRM_PLL_SOURCE_HEXT, 72, 1, CRM_PLL_FR_2);
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/* enable pll */
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crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
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/* wait till pll is ready */
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while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
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{
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}
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/* config ahbclk */
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crm_ahb_div_set(CRM_AHB_DIV_1);
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/* config apb2clk, the maximum frequency of APB2 clock is 150 MHz */
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crm_apb2_div_set(CRM_APB2_DIV_1);
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/* config apb1clk, the maximum frequency of APB1 clock is 120 MHz */
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crm_apb1_div_set(CRM_APB1_DIV_2);
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/* enable auto step mode */
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crm_auto_step_mode_enable(TRUE);
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/* select pll as system clock source */
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crm_sysclk_switch(CRM_SCLK_PLL);
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/* wait till pll is used as system clock source */
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while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
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{
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}
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/* disable auto step mode */
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crm_auto_step_mode_enable(FALSE);
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/* update system_core_clock global variable */
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system_core_clock_update();
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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