302 lines
12 KiB
C
302 lines
12 KiB
C
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/*
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* @brief LPC13xx A/D conversion driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __ADC_13XX_H_
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#define __ADC_13XX_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup ADC_13XX CHIP: LPC13xx A/D conversion driver
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* @ingroup CHIP_13XX_Drivers
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* @{
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*/
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#if defined(CHIP_LPC1347)
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#define ADC_ACC_12BITS
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#define ADC_TRIM_SUPPORT
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#else
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#define ADC_ACC_10BITS
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#endif
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#if defined(CHIP_LPC1347)
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#define ADC_MAX_SAMPLE_RATE 500000
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#else
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#define ADC_MAX_SAMPLE_RATE 400000
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#endif
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/**
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* @brief 10 or 12-bit ADC register block structure
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*/
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typedef struct { /*!< ADCn Structure */
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__IO uint32_t CR; /*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
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__I uint32_t GDR; /*!< A/D Global Data Register. Contains the result of the most recent A/D conversion. */
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__I uint32_t RESERVED0;
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__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
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__I uint32_t DR[8]; /*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
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__I uint32_t STAT; /*!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
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#if defined(ADC_TRIM_SUPPORT)
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__IO uint32_t ADTRM;
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#endif
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} LPC_ADC_T;
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/**
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* @brief ADC register support bitfields and mask
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*/
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#if defined(ADC_ACC_12BITS)
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#define ADC_DR_RESULT(n) ((((n) >> 4) & 0xFFF)) /*!< Mask for getting the 12 bits ADC data read value */
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#else
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#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /*!< Mask for getting the 10 bits ADC data read value */
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#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /*!< Number of ADC accuracy bits */
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#endif
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#define ADC_DR_DONE(n) (((n) >> 31)) /*!< Mask for reading the ADC done status */
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#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /*!< Mask for reading the ADC overrun status */
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#define ADC_CR_CH_SEL(n) ((1UL << (n))) /*!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
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#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
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#define ADC_CR_BURST ((1UL << 16)) /*!< Repeated conversions A/D enable bit */
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#if defined(CHIP_LPC1347)
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#define ADC_CR_LPWRMODE ((1UL << 22)) /*!<Enable the low-power ADC mode */
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#define ADC_CR_MODE10BIT ((1UL << 23)) /*!<Enable the 10-bit conversion rate mode with high conversion rate. */
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#else
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#define ADC_CR_PDN ((1UL << 21)) /*!< ADC convert is operational */
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#endif
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#define ADC_CR_START_MASK ((7UL << 24)) /*!< ADC start mask bits */
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#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /*!< Select Start Mode */
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#define ADC_CR_START_NOW ((1UL << 24)) /*!< Start conversion now */
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#define ADC_CR_START_CTOUT15 ((2UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
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#define ADC_CR_START_CTOUT8 ((3UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
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#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
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#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
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#define ADC_CR_START_MCOA2 ((6UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
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#define ADC_CR_EDGE ((1UL << 27)) /*!< Start conversion on a falling edge on the selected CAP/MAT signal */
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#if defined(CHIP_LPC1347)
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#define ADC_SAMPLE_RATE_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_MODE10BIT)
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#else
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#define ADC_SAMPLE_RATE_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07))
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#endif
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/**
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* @brief ADC status register used for IP drivers
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*/
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typedef enum IP_ADC_STATUS {
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ADC_DR_DONE_STAT, /*!< ADC data register staus */
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ADC_DR_OVERRUN_STAT,/*!< ADC data overrun staus */
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ADC_DR_ADINT_STAT /*!< ADC interrupt status */
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} ADC_STATUS_T;
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/** The channels on one ADC peripheral*/
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typedef enum CHIP_ADC_CHANNEL {
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ADC_CH0 = 0, /**< ADC channel 0 */
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ADC_CH1, /**< ADC channel 1 */
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ADC_CH2, /**< ADC channel 2 */
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ADC_CH3, /**< ADC channel 3 */
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ADC_CH4, /**< ADC channel 4 */
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ADC_CH5, /**< ADC channel 5 */
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ADC_CH6, /**< ADC channel 6 */
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ADC_CH7, /**< ADC channel 7 */
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} ADC_CHANNEL_T;
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#if defined(CHIP_LPC1347)
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/** LPC1347 chip */
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typedef enum CHIP_ADC_RESOLUTION {
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ADC_12BITS = 0, /**< ADC 12 bits */
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ADC_10BITS = 1, /**< ADC 10 bits */
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} ADC_RESOLUTION_T;
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#else
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/** The number of bits of accuracy of the result in the LS bits of ADDR*/
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typedef enum CHIP_ADC_RESOLUTION {
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ADC_10BITS = 0, /**< ADC 10 bits */
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ADC_9BITS, /**< ADC 9 bits */
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ADC_8BITS, /**< ADC 8 bits */
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ADC_7BITS, /**< ADC 7 bits */
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ADC_6BITS, /**< ADC 6 bits */
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ADC_5BITS, /**< ADC 5 bits */
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ADC_4BITS, /**< ADC 4 bits */
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ADC_3BITS, /**< ADC 3 bits */
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} ADC_RESOLUTION_T;
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#endif
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/** Edge configuration, which controls rising or falling edge on the selected signal for the start of a conversion */
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typedef enum CHIP_ADC_EDGE_CFG {
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ADC_TRIGGERMODE_RISING = 0, /**< Trigger event: rising edge */
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ADC_TRIGGERMODE_FALLING, /**< Trigger event: falling edge */
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} ADC_EDGE_CFG_T;
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/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
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typedef enum CHIP_ADC_START_MODE {
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ADC_NO_START = 0,
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ADC_START_NOW, /*!< Start conversion now */
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ADC_START_ON_CTOUT15, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
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ADC_START_ON_CTOUT8, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
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ADC_START_ON_ADCTRIG0, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
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ADC_START_ON_ADCTRIG1, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
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ADC_START_ON_MCOA2 /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
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} ADC_START_MODE_T;
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/** Clock setup structure for ADC controller passed to the initialize function */
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typedef struct {
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uint32_t adcRate; /*!< ADC rate */
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uint8_t bitsAccuracy; /*!< ADC bit accuracy */
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bool burstMode; /*!< ADC Burt Mode */
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} ADC_CLOCK_SETUP_T;
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/**
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* @brief Initialize the ADC peripheral and the ADC setup structure to default value
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* @param pADC : The base of ADC peripheral on the chip
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* @param ADCSetup : ADC setup structure to be set
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* @return Nothing
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* @note Default setting for ADC is 400kHz - 10bits
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*/
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void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup);
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/**
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* @brief Shutdown ADC
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* @param pADC : The base of ADC peripheral on the chip
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* @return Nothing
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*/
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void Chip_ADC_DeInit(LPC_ADC_T *pADC);
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/**
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* @brief Read the ADC value from a channel
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* @param pADC : The base of ADC peripheral on the chip
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* @param channel : ADC channel to read
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* @param data : Pointer to where to put data
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* @return SUCCESS or ERROR if no conversion is ready
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*/
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Status Chip_ADC_ReadValue(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data);
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/**
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* @brief Read the ADC value and convert it to 8bits value
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* @param pADC : The base of ADC peripheral on the chip
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* @param channel: selected channel
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* @param data : Storage for data
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* @return Status : ERROR or SUCCESS
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*/
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Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data);
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/**
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* @brief Read the ADC channel status
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* @param pADC : The base of ADC peripheral on the chip
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* @param channel : ADC channel to read
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* @param StatusType : Status type of ADC_DR_*
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* @return SET or RESET
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*/
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FlagStatus Chip_ADC_ReadStatus(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType);
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/**
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* @brief Enable/Disable interrupt for ADC channel
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* @param pADC : The base of ADC peripheral on the chip
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* @param channel : ADC channel to read
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* @param NewState : New state, ENABLE or DISABLE
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* @return SET or RESET
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*/
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void Chip_ADC_Int_SetChannelCmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState);
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/**
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* @brief Enable/Disable global interrupt for ADC channel
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* @param pADC : The base of ADC peripheral on the chip
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* @param NewState : New state, ENABLE or DISABLE
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* @return Nothing
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*/
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STATIC INLINE void Chip_ADC_Int_SetGlobalCmd(LPC_ADC_T *pADC, FunctionalState NewState)
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{
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Chip_ADC_Int_SetChannelCmd(pADC, 8, NewState);
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}
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/**
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* @brief Select the mode starting the AD conversion
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* @param pADC : The base of ADC peripheral on the chip
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* @param mode : Stating mode, should be :
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* - ADC_NO_START : Must be set for Burst mode
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* - ADC_START_NOW : Start conversion now
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* - ADC_START_ON_CTOUT15 : Start conversion when the edge selected by bit 27 occurs on CTOUT_15
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* - ADC_START_ON_CTOUT8 : Start conversion when the edge selected by bit 27 occurs on CTOUT_8
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* - ADC_START_ON_ADCTRIG0 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG0
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* - ADC_START_ON_ADCTRIG1 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG1
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* - ADC_START_ON_MCOA2 : Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2
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* @param EdgeOption : Stating Edge Condition, should be :
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* - ADC_TRIGGERMODE_RISING : Trigger event on rising edge
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* - ADC_TRIGGERMODE_FALLING : Trigger event on falling edge
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* @return Nothing
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*/
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void Chip_ADC_SetStartMode(LPC_ADC_T *pADC, ADC_START_MODE_T mode, ADC_EDGE_CFG_T EdgeOption);
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/**
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* @brief Set the ADC Sample rate
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* @param pADC : The base of ADC peripheral on the chip
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* @param ADCSetup : ADC setup structure to be modified
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* @param rate : Sample rate, should be set so the clock for A/D converter is less than or equal to 4.5MHz.
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* @return Nothing
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*/
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void Chip_ADC_SetSampleRate(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, uint32_t rate);
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/**
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* @brief Set the ADC accuracy bits
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* @param pADC : The base of ADC peripheral on the chip
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* @param ADCSetup : ADC setup structure to be modified
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* @param resolution : The resolution, should be ADC_10BITS -> ADC_3BITS
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* @return Nothing
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*/
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void Chip_ADC_SetResolution(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, ADC_RESOLUTION_T resolution);
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/**
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* @brief Enable or disable the ADC channel on ADC peripheral
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* @param pADC : The base of ADC peripheral on the chip
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* @param channel : Channel to be enable or disable
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* @param NewState : New state, should be:
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* - ENABLE
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* - DISABLE
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* @return Nothing
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*/
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void Chip_ADC_EnableChannel(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, FunctionalState NewState);
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/**
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* @brief Enable burst mode
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* @param pADC : The base of ADC peripheral on the chip
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* @param NewState : New state, should be:
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* - ENABLE
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* - DISABLE
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* @return Nothing
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*/
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void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ADC_13XX_H_ */
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