197 lines
6.7 KiB
ArmAsm
197 lines
6.7 KiB
ArmAsm
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/**************************************************
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*
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* Part one of the system initialization code, contains low-level
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* initialization, plain thumb variant.
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*
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* Copyright 2009 IAR Systems. All rights reserved.
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*
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* $Revision: 47021 $
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*
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**************************************************/
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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PUBLIC __vector_table
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PUBLIC __vector_table_0x1c
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DATA
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__vector_table
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DCD sfe(CSTACK) ; Top of Stack
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DCD __iar_program_start ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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__vector_table_0x1c
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Ha dler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
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DCD FLEX_INT1_IRQHandler
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DCD FLEX_INT2_IRQHandler
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DCD FLEX_INT3_IRQHandler
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DCD FLEX_INT4_IRQHandler
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DCD FLEX_INT5_IRQHandler
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DCD FLEX_INT6_IRQHandler
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DCD FLEX_INT7_IRQHandler
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DCD GINT0_IRQHandler
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DCD GINT1_IRQHandler ; PIO0 (0:7)
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DCD Reserved_IRQHandler ; Reserved
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DCD Reserved_IRQHandler
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DCD Reserved_IRQHandler
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DCD Reserved_IRQHandler
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DCD SSP1_IRQHandler ; SSP1
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DCD I2C_IRQHandler ; I2C
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DCD TIMER16_0_IRQHandler ; 16-bit Timer0
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DCD TIMER16_1_IRQHandler ; 16-bit Timer1
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DCD TIMER32_0_IRQHandler ; 32-bit Timer0
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DCD TIMER32_1_IRQHandler ; 32-bit Timer1
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DCD SSP0_IRQHandler ; SSP0
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DCD UART_IRQHandler ; UART
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DCD USB_IRQHandler ; USB IRQ
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DCD USB_FIQHandler ; USB FIQ
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DCD ADC_IRQHandler ; A/D Converter
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DCD WDT_IRQHandler ; Watchdog timer
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DCD BOD_IRQHandler ; Brown Out Detect
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DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
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DCD Reserved_IRQHandler ; Reserved
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DCD Reserved_IRQHandler ; Reserved
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DCD USBWakeup_IRQHandler ; USB wake up
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DCD Reserved_IRQHandler ; Reserved
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB
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SECTION .text:CODE:REORDER:NOROOT(1)
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PUBWEAK NMI_Handler
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PUBWEAK HardFault_Handler
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PUBWEAK MemManage_Handler
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PUBWEAK BusFault_Handler
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PUBWEAK UsageFault_Handler
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PUBWEAK SVC_Handler
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PUBWEAK DebugMon_Handler
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PUBWEAK PendSV_Handler
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PUBWEAK SysTick_Handler
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PUBWEAK FLEX_INT0_IRQHandler
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PUBWEAK FLEX_INT1_IRQHandler
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PUBWEAK FLEX_INT2_IRQHandler
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PUBWEAK FLEX_INT3_IRQHandler
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PUBWEAK FLEX_INT4_IRQHandler
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PUBWEAK FLEX_INT5_IRQHandler
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PUBWEAK FLEX_INT6_IRQHandler
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PUBWEAK FLEX_INT7_IRQHandler
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PUBWEAK GINT0_IRQHandler
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PUBWEAK GINT1_IRQHandler
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PUBWEAK SSP1_IRQHandler
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PUBWEAK I2C_IRQHandler
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PUBWEAK TIMER16_0_IRQHandler
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PUBWEAK TIMER16_1_IRQHandler
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PUBWEAK TIMER32_0_IRQHandler
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PUBWEAK TIMER32_1_IRQHandler
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PUBWEAK SSP0_IRQHandler
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PUBWEAK UART_IRQHandler
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PUBWEAK USB_IRQHandler
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PUBWEAK USB_FIQHandler
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PUBWEAK ADC_IRQHandler
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PUBWEAK WDT_IRQHandler
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PUBWEAK BOD_IRQHandler
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PUBWEAK FMC_IRQHandler
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PUBWEAK USBWakeup_IRQHandler
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PUBWEAK Reserved_IRQHandler
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NMI_Handler
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HardFault_Handler
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MemManage_Handler
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BusFault_Handler
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UsageFault_Handler
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SVC_Handler
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DebugMon_Handler
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PendSV_Handler
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SysTick_Handler
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FLEX_INT0_IRQHandler
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FLEX_INT1_IRQHandler
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FLEX_INT2_IRQHandler
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FLEX_INT3_IRQHandler
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FLEX_INT4_IRQHandler
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FLEX_INT5_IRQHandler
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FLEX_INT6_IRQHandler
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FLEX_INT7_IRQHandler
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GINT0_IRQHandler
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GINT1_IRQHandler
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SSP1_IRQHandler
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I2C_IRQHandler
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TIMER16_0_IRQHandler
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TIMER16_1_IRQHandler
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TIMER32_0_IRQHandler
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TIMER32_1_IRQHandler
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SSP0_IRQHandler
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UART_IRQHandler
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USB_IRQHandler
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USB_FIQHandler
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ADC_IRQHandler
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WDT_IRQHandler
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BOD_IRQHandler
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FMC_IRQHandler
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USBWakeup_IRQHandler
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Reserved_IRQHandler
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Default_Handler:
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B Default_Handler
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SECTION .crp:CODE:ROOT(2)
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DATA
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/* Code Read Protection
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NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
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CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
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- Copy RAM to flash command can not write to Sector 0.
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- Erase command can erase Sector 0 only when all sectors
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are selected for erase.
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- Compare command is disabled.
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- Read Memory command is disabled.
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CRP2 0x87654321 - Read Memory is disabled.
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- Write to RAM is disabled.
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- "Go" command is disabled.
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- Copy RAM to flash is disabled.
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- Compare is disabled.
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CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
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by pulling PIO0_1 LOW is disabled if a valid user code is
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present in flash sector 0.
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Caution: If CRP3 is selected, no future factory testing can be
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performed on the device.
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*/
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DCD 0xFFFFFFFF
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END
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