590 lines
18 KiB
C
590 lines
18 KiB
C
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/*
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* @brief LPC11U6X Clock control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CLOCK_11U6X_H_
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#define __CLOCK_11U6X_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup CLOCK_11U6X CHIP: LPC11u6x Clock Control block driver
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* @ingroup CHIP_11U6X_Drivers
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* @{
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*/
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/** Internal oscillator frequency */
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#define SYSCTL_IRC_FREQ (12000000)
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/**
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* @brief Set System PLL divider values
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* @param msel : PLL feedback divider value. M = msel + 1.
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* @param psel : PLL post divider value. P = (1<<psel).
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* @return Nothing
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* @note See the user manual for how to setup the PLL.
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*/
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STATIC INLINE void Chip_Clock_SetupSystemPLL(uint8_t msel, uint8_t psel)
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{
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LPC_SYSCTL->SYSPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
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}
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/**
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* @brief Read System PLL lock status
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* @return true of the PLL is locked. false if not locked
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*/
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STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void)
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{
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return (bool) ((LPC_SYSCTL->SYSPLLSTAT & 1) != 0);
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}
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/**
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* Clock sources for system PLL
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*/
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typedef enum CHIP_SYSCTL_PLLCLKSRC {
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SYSCTL_PLLCLKSRC_IRC = 0, /*!< Internal oscillator in */
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SYSCTL_PLLCLKSRC_MAINOSC, /*!< Crystal (main) oscillator in */
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SYSCTL_PLLCLKSRC_SYSOSC = SYSCTL_PLLCLKSRC_MAINOSC,
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SYSCTL_PLLCLKSRC_RESERVED1, /*!< Reserved */
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SYSCTL_PLLCLKSRC_RTC32K, /*!< RTC 32KHz clock */
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} CHIP_SYSCTL_PLLCLKSRC_T;
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/**
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* @brief Set System PLL clock source
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* @param src : Clock source for system PLL
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* @return Nothing
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* @note This function will also toggle the clock source update register
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* to update the clock source.
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*/
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void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src);
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/**
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* @brief Set USB PLL divider values
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* @param msel : PLL feedback divider value. M = msel + 1.
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* @param psel : PLL post divider value. P = (1<<psel).
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* @return Nothing
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* @note See the user manual for how to setup the PLL.
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*/
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STATIC INLINE void Chip_Clock_SetupUSBPLL(uint8_t msel, uint8_t psel)
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{
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LPC_SYSCTL->USBPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
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}
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/**
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* @brief Read USB PLL lock status
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* @return true of the PLL is locked. false if not locked
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*/
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STATIC INLINE bool Chip_Clock_IsUSBPLLLocked(void)
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{
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return (bool) ((LPC_SYSCTL->USBPLLSTAT & 1) != 0);
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}
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/**
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* Clock sources for USB PLL
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*/
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typedef enum CHIP_SYSCTL_USBPLLCLKSRC {
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SYSCTL_USBPLLCLKSRC_IRC = 0, /*!< Internal oscillator in */
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SYSCTL_USBPLLCLKSRC_MAINOSC, /*!< Crystal (main) oscillator in */
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SYSCTL_USBPLLCLKSRC_SYSOSC = SYSCTL_USBPLLCLKSRC_MAINOSC,
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SYSCTL_USBPLLCLKSRC_RESERVED1, /*!< Reserved */
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SYSCTL_USBPLLCLKSRC_RESERVED2, /*!< Reserved */
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} CHIP_SYSCTL_USBPLLCLKSRC_T;
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/**
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* @brief Set USB PLL clock source
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* @param src : Clock source for USB PLL
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* @return Nothing
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* @note This function will also toggle the clock source update register
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* to update the clock source.
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*/
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void Chip_Clock_SetUSBPLLSource(CHIP_SYSCTL_USBPLLCLKSRC_T src);
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/**
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* @brief Bypass System Oscillator and set oscillator frequency range
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* @param bypass : Flag to bypass oscillator
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* @param highfr : Flag to set oscillator range from 15-25 MHz
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* @return Nothing
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* @note Sets the PLL input to bypass the oscillator. This would be
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* used if an external clock that is not an oscillator is attached
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* to the XTALIN pin.
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*/
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void Chip_Clock_SetPLLBypass(bool bypass, bool highfr);
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/**
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* @brief Enable the RTC 32KHz output
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* @return Nothing
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* @note This clock can be used for the main clock directly, but
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* do not use this clock with the system PLL.
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*/
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STATIC INLINE void Chip_Clock_EnableRTCOsc(void)
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{
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LPC_SYSCTL->RTCOSCCTRL = 1;
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}
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/**
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* @brief Disable the RTC 32KHz output
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* @return Nothing
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*/
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STATIC INLINE void Chip_Clock_DisableRTCOsc(void)
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{
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LPC_SYSCTL->RTCOSCCTRL = 0;
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}
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/**
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* Watchdog and low frequency oscillator frequencies plus or minus 40%
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*/
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typedef enum CHIP_WDTLFO_OSC {
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WDTLFO_OSC_ILLEGAL,
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WDTLFO_OSC_0_60, /*!< 0.6 MHz watchdog/LFO rate */
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WDTLFO_OSC_1_05, /*!< 1.05 MHz watchdog/LFO rate */
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WDTLFO_OSC_1_40, /*!< 1.4 MHz watchdog/LFO rate */
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WDTLFO_OSC_1_75, /*!< 1.75 MHz watchdog/LFO rate */
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WDTLFO_OSC_2_10, /*!< 2.1 MHz watchdog/LFO rate */
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WDTLFO_OSC_2_40, /*!< 2.4 MHz watchdog/LFO rate */
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WDTLFO_OSC_2_70, /*!< 2.7 MHz watchdog/LFO rate */
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WDTLFO_OSC_3_00, /*!< 3.0 MHz watchdog/LFO rate */
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WDTLFO_OSC_3_25, /*!< 3.25 MHz watchdog/LFO rate */
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WDTLFO_OSC_3_50, /*!< 3.5 MHz watchdog/LFO rate */
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WDTLFO_OSC_3_75, /*!< 3.75 MHz watchdog/LFO rate */
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WDTLFO_OSC_4_00, /*!< 4.0 MHz watchdog/LFO rate */
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WDTLFO_OSC_4_20, /*!< 4.2 MHz watchdog/LFO rate */
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WDTLFO_OSC_4_40, /*!< 4.4 MHz watchdog/LFO rate */
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WDTLFO_OSC_4_60 /*!< 4.6 MHz watchdog/LFO rate */
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} CHIP_WDTLFO_OSC_T;
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/**
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* @brief Setup Watchdog oscillator rate and divider
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* @param wdtclk : Selected watchdog clock rate
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* @param div : Watchdog divider value, even value between 2 and 64
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* @return Nothing
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* @note Watchdog rate = selected rate divided by divider rate
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*/
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STATIC INLINE void Chip_Clock_SetWDTOSC(CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
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{
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LPC_SYSCTL->WDTOSCCTRL = (((uint32_t) wdtclk) << 5) | ((div >> 1) - 1);
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}
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/**
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* Clock sources for main system clock
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*/
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typedef enum CHIP_SYSCTL_MAINCLKSRC {
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SYSCTL_MAINCLKSRC_IRC = 0, /*!< Internal oscillator */
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SYSCTL_MAINCLKSRC_PLLIN, /*!< System PLL input */
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SYSCTL_MAINCLKSRC_WDTOSC, /*!< Watchdog oscillator rate */
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SYSCTL_MAINCLKSRC_PLLOUT, /*!< System PLL output */
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} CHIP_SYSCTL_MAINCLKSRC_T;
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/**
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* @brief Set main system clock source
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* @param src : Clock source for main system
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* @return Nothing
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* @note This function will also toggle the clock source update register
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* to update the clock source.
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*/
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void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src);
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/**
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* @brief Returns the main clock source
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* @return Which clock is used for the core clock source?
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*/
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STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void)
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{
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return (CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL);
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}
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/**
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* @brief Set system clock divider
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* @param div : divider for system clock
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* @return Nothing
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* @note Use 0 to disable, or a divider value of 1 to 255. The system clock
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* rate is the main system clock divided by this value.
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*/
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STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div)
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{
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LPC_SYSCTL->SYSAHBCLKDIV = div;
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}
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/**
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* System and peripheral clocks
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*/
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typedef enum CHIP_SYSCTL_CLOCK {
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SYSCTL_CLOCK_SYS = 0, /*!< 0: System clock */
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SYSCTL_CLOCK_ROM, /*!< 1: ROM clock */
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SYSCTL_CLOCK_RAM0, /*!< 2: RAM0 clock */
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SYSCTL_CLOCK_FLASHREG, /*!< 3: FLASH register interface clock */
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SYSCTL_CLOCK_FLASHARRAY, /*!< 4: FLASH array access clock */
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SYSCTL_CLOCK_I2C0, /*!< 5: I2C0 clock */
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SYSCTL_CLOCK_GPIO, /*!< 6: GPIO clock */
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SYSCTL_CLOCK_CT16B0, /*!< 7: 16-bit Counter/timer 0 clock */
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SYSCTL_CLOCK_CT16B1, /*!< 8: 16-bit Counter/timer 1 clock */
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SYSCTL_CLOCK_CT32B0, /*!< 9: 32-bit Counter/timer 0 clock */
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SYSCTL_CLOCK_CT32B1, /*!< 10: 32-bit Counter/timer 1 clock */
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SYSCTL_CLOCK_SSP0, /*!< 11: SSP0 clock */
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SYSCTL_CLOCK_UART0, /*!< 12: UART0 clock */
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SYSCTL_CLOCK_ADC, /*!< 13: ADC clock */
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SYSCTL_CLOCK_USB, /*!< 14: USB clock */
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SYSCTL_CLOCK_WDT, /*!< 15: Watchdog timer clock */
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SYSCTL_CLOCK_IOCON, /*!< 16: IOCON block clock */
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SYSCTL_CLOCK_RESERVED17, /*!< 17: Reserved */
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SYSCTL_CLOCK_SSP1, /*!< 18: SSP1 clock */
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SYSCTL_CLOCK_PINT, /*!< 19: GPIO Pin int register interface clock */
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SYSCTL_CLOCK_USART1, /*!< 20: USART1 clock */
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SYSCTL_CLOCK_USART2, /*!< 21: USART2 clock */
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SYSCTL_CLOCK_USART3_4, /*!< 22: USART3_4 clock */
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SYSCTL_CLOCK_P0INT, /*!< 23: GPIO GROUP1 interrupt register clock */
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SYSCTL_CLOCK_GROUP0INT = SYSCTL_CLOCK_P0INT,/*!< 23: GPIO GROUP0 interrupt register interface clock */
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SYSCTL_CLOCK_P1INT, /*!< 24: GPIO GROUP1 interrupt register clock */
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SYSCTL_CLOCK_GROUP1INT = SYSCTL_CLOCK_P1INT,/*!< 24: GPIO GROUP1 interrupt register interface clock */
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SYSCTL_CLOCK_I2C1, /*!< 25: I2C1 clock */
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SYSCTL_CLOCK_RAM1, /*!< 26: SRAM block clock */
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SYSCTL_CLOCK_USBRAM, /*!< 27: USB SRAM block clock */
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SYSCTL_CLOCK_CRC, /*!< 25: CRC clock */
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SYSCTL_CLOCK_DMA, /*!< 25: DMA clock */
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SYSCTL_CLOCK_RTC, /*!< 25: RTC clock */
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SYSCTL_CLOCK_SCT0_1, /*!< 25: SCT 0/1 clock */
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} CHIP_SYSCTL_CLOCK_T;
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/**
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* @brief Enable a system or peripheral clock
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* @param clk : Clock to enable
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* @return Nothing
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*/
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STATIC INLINE void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
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{
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LPC_SYSCTL->SYSAHBCLKCTRL |= (1 << clk);
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}
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/**
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* @brief Disable a system or peripheral clock
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* @param clk : Clock to disable
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* @return Nothing
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*/
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STATIC INLINE void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
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{
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LPC_SYSCTL->SYSAHBCLKCTRL &= ~(1 << clk);
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}
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/**
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* @brief Set SSP0 divider
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* @param div : divider for SSP0 clock
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* @return Nothing
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* @note Use 0 to disable, or a divider value of 1 to 255. The SSP0 clock
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* rate is the main system clock divided by this value.
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*/
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STATIC INLINE void Chip_Clock_SetSSP0ClockDiv(uint32_t div)
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{
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LPC_SYSCTL->SSP0CLKDIV = div;
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}
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/**
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* @brief Return SSP0 divider
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* @return divider for SSP0 clock
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* @note A value of 0 means the clock is disabled.
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*/
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STATIC INLINE uint32_t Chip_Clock_GetSSP0ClockDiv(void)
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{
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return LPC_SYSCTL->SSP0CLKDIV;
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}
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/**
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* @brief Set USART0 divider clock
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* @param div : divider for UART clock
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* @return Nothing
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* @note Use 0 to disable, or a divider value of 1 to 255. The UART clock
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* rate is the main system clock divided by this value.
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*/
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STATIC INLINE void Chip_Clock_SetUSART0ClockDiv(uint32_t div)
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{
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LPC_SYSCTL->USART0CLKDIV = div;
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}
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/**
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* @brief Return USART0 divider
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* @return divider for UART clock
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* @note A value of 0 means the clock is disabled.
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*/
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STATIC INLINE uint32_t Chip_Clock_GetUASRT0ClockDiv(void)
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{
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return LPC_SYSCTL->USART0CLKDIV;
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}
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/**
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* @brief Set SSP1 divider clock
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* @param div : divider for SSP1 clock
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* @return Nothing
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* @note Use 0 to disable, or a divider value of 1 to 255. The SSP1 clock
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||
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|
* rate is the main system clock divided by this value.
|
||
|
|
*/
|
||
|
|
STATIC INLINE void Chip_Clock_SetSSP1ClockDiv(uint32_t div)
|
||
|
|
{
|
||
|
|
LPC_SYSCTL->SSP1CLKDIV = div;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return SSP1 divider
|
||
|
|
* @return divider for SSP1 clock
|
||
|
|
* @note A value of 0 means the clock is disabled.
|
||
|
|
*/
|
||
|
|
STATIC INLINE uint32_t Chip_Clock_GetSSP1ClockDiv(void)
|
||
|
|
{
|
||
|
|
return LPC_SYSCTL->SSP1CLKDIV;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Set USART 1/2/3/4 UART base rate (up to main clock rate)
|
||
|
|
* @param rate : Desired rate for fractional divider/multipler output
|
||
|
|
* @param fEnable : true to use fractional clocking, false for integer clocking
|
||
|
|
* @return Actual rate generated
|
||
|
|
* @note USARTs 1 - 4 use the same base clock for their baud rate
|
||
|
|
* basis. This function is used to generate that clock, while the
|
||
|
|
* UART driver's SetBaud functions will attempt to get the closest
|
||
|
|
* baud rate from this base clock without altering it. This needs
|
||
|
|
* to be setup prior to individual UART setup.<br>
|
||
|
|
* UARTs need a base clock 16x faster than the baud rate, so if you
|
||
|
|
* need a 115.2Kbps baud rate, you will need a clock rate of at
|
||
|
|
* least (115.2K * 16). The UART base clock is generated from the
|
||
|
|
* main system clock, so fractional clocking may be the only
|
||
|
|
* possible choice when using a low main system clock frequency.
|
||
|
|
* Do not alter the FRGCLKDIV register after this call.
|
||
|
|
*/
|
||
|
|
uint32_t Chip_Clock_SetUSARTNBaseClockRate(uint32_t rate, bool fEnable);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Get USART 1/2/3/4 UART base rate
|
||
|
|
* @return USART 1/2/3/4 UART base rate
|
||
|
|
*/
|
||
|
|
uint32_t Chip_Clock_GetUSARTNBaseClockRate(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Set USART 1/2/3/4 fractional baud rate divider clock
|
||
|
|
* @param div : divider for USART 1/2/3/4 fractional baud rate clock
|
||
|
|
* @return Nothing
|
||
|
|
* @note Use 0 to disable, or a divider value of 1 to 255.
|
||
|
|
* This does not affect USART0.
|
||
|
|
*/
|
||
|
|
STATIC INLINE void Chip_Clock_SetUSARTNBaseClockDiv(uint8_t div)
|
||
|
|
{
|
||
|
|
LPC_SYSCTL->FRGCLKDIV = (uint32_t) div;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return USART 1/2/3/4 fractional baud rate divider
|
||
|
|
* @return divider for USART 1/2/3/4 fractional baud rate clock
|
||
|
|
* @note A value of 0 means the clock is disabled.
|
||
|
|
* This does not affect USART0.
|
||
|
|
*/
|
||
|
|
STATIC INLINE uint32_t Chip_Clock_GetUSARTNBaseClockDiv(void)
|
||
|
|
{
|
||
|
|
return LPC_SYSCTL->FRGCLKDIV;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Set The USART Fractional Generator Divider
|
||
|
|
* @param div : Fractional Generator Divider value, should be 0xFF
|
||
|
|
* @return Nothing
|
||
|
|
*/
|
||
|
|
STATIC INLINE void Chip_Clock_SetUSARTNFRGDivider(uint8_t div)
|
||
|
|
{
|
||
|
|
LPC_SYSCTL->UARTFRGDIV = (uint32_t) div;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Set The USART Fractional Generator Divider
|
||
|
|
* @return Value of USART Fractional Generator Divider
|
||
|
|
*/
|
||
|
|
STATIC INLINE uint32_t Chip_Clock_GetUSARTNFRGDivider(void)
|
||
|
|
{
|
||
|
|
return LPC_SYSCTL->UARTFRGDIV;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Set The USART Fractional Generator Multiplier
|
||
|
|
* @param mult : An 8-bit value (0-255) U_PCLK = UARTCLKDIV/(1 + MULT/256)
|
||
|
|
* @return Nothing
|
||
|
|
*/
|
||
|
|
STATIC INLINE void Chip_Clock_SetUSARTNFRGMultiplier(uint8_t mult)
|
||
|
|
{
|
||
|
|
LPC_SYSCTL->UARTFRGMULT = (uint32_t) mult;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Get The USART Fractional Generator Multiplier
|
||
|
|
* @return Value of USART Fractional Generator Multiplier
|
||
|
|
*/
|
||
|
|
STATIC INLINE uint32_t Chip_Clock_GetUSARTNFRGMultiplier(void)
|
||
|
|
{
|
||
|
|
return LPC_SYSCTL->UARTFRGMULT;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Clock sources for USB
|
||
|
|
*/
|
||
|
|
typedef enum CHIP_SYSCTL_USBCLKSRC {
|
||
|
|
SYSCTL_USBCLKSRC_PLLOUT = 0, /*!< USB PLL out */
|
||
|
|
SYSCTL_USBCLKSRC_MAINSYSCLK, /*!< Main system clock */
|
||
|
|
} CHIP_SYSCTL_USBCLKSRC_T;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Set USB clock source and divider
|
||
|
|
* @param src : Clock source for USB
|
||
|
|
* @param div : divider for USB clock
|
||
|
|
* @return Nothing
|
||
|
|
* @note Use 0 to disable, or a divider value of 1 to 255. The USB clock
|
||
|
|
* rate is either the main system clock or USB PLL output clock divided
|
||
|
|
* by this value. This function will also toggle the clock source
|
||
|
|
* update register to update the clock source.
|
||
|
|
*/
|
||
|
|
void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Clock sources for CLKOUT
|
||
|
|
*/
|
||
|
|
typedef enum CHIP_SYSCTL_CLKOUTSRC {
|
||
|
|
SYSCTL_CLKOUTSRC_IRC = 0, /*!< Internal oscillator for CLKOUT */
|
||
|
|
SYSCTL_CLKOUTSRC_MAINOSC, /*!< Main oscillator for CLKOUT */
|
||
|
|
SYSCTL_CLKOUTSRC_SYSOSC = SYSCTL_CLKOUTSRC_MAINOSC,
|
||
|
|
SYSCTL_CLKOUTSRC_WDTOSC, /*!< Watchdog oscillator for CLKOUT */
|
||
|
|
SYSCTL_CLKOUTSRC_MAINSYSCLK, /*!< Main system clock for CLKOUT */
|
||
|
|
} CHIP_SYSCTL_CLKOUTSRC_T;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Set CLKOUT clock source and divider
|
||
|
|
* @param src : Clock source for CLKOUT
|
||
|
|
* @param div : divider for CLKOUT clock
|
||
|
|
* @return Nothing
|
||
|
|
* @note Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock
|
||
|
|
* rate is the clock source divided by the divider. This function will
|
||
|
|
* also toggle the clock source update register to update the clock
|
||
|
|
* source.
|
||
|
|
*/
|
||
|
|
void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Set IOCON glitch filter clock divider value
|
||
|
|
* @param index : IOCON divider index (0 - 6) to set
|
||
|
|
* @param div : value for IOCON filter divider value
|
||
|
|
* @return Nothing
|
||
|
|
* @note Use 0 to disable, or a divider value of 1 to 255.
|
||
|
|
*/
|
||
|
|
STATIC INLINE void Chip_Clock_SetIOCONFiltClockDiv(int index, uint32_t div)
|
||
|
|
{
|
||
|
|
LPC_SYSCTL->IOCONCLKDIV[6 - index] = div;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return IOCON glitch filter clock divider value
|
||
|
|
* @param index : IOCON divider index (0 - 6) to get
|
||
|
|
* @return IOCON glitch filter clock divider value
|
||
|
|
*/
|
||
|
|
STATIC INLINE uint32_t Chip_Clock_GetIOCONFiltClockDiv(int index)
|
||
|
|
{
|
||
|
|
return LPC_SYSCTL->IOCONCLKDIV[6 - index];
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Returns the main oscillator clock rate
|
||
|
|
* @return main oscillator clock rate in Hz
|
||
|
|
*/
|
||
|
|
STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
|
||
|
|
{
|
||
|
|
return OscRateIn;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Returns the internal oscillator (IRC) clock rate
|
||
|
|
* @return internal oscillator (IRC) clock rate in Hz
|
||
|
|
*/
|
||
|
|
STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
|
||
|
|
{
|
||
|
|
return SYSCTL_IRC_FREQ;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Returns the RTC clock rate
|
||
|
|
* @return RTC oscillator clock rate in Hz
|
||
|
|
*/
|
||
|
|
STATIC INLINE uint32_t Chip_Clock_GetRTCOscRate(void)
|
||
|
|
{
|
||
|
|
return RTCOscRateIn;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return estimated watchdog oscillator rate
|
||
|
|
* @return Estimated watchdog oscillator rate
|
||
|
|
* @note This rate is accurate to plus or minus 40%.
|
||
|
|
*/
|
||
|
|
uint32_t Chip_Clock_GetWDTOSCRate(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return System PLL input clock rate
|
||
|
|
* @return System PLL input clock rate
|
||
|
|
*/
|
||
|
|
uint32_t Chip_Clock_GetSystemPLLInClockRate(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return System PLL output clock rate
|
||
|
|
* @return System PLL output clock rate
|
||
|
|
*/
|
||
|
|
uint32_t Chip_Clock_GetSystemPLLOutClockRate(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return USB PLL input clock rate
|
||
|
|
* @return USB PLL input clock rate
|
||
|
|
*/
|
||
|
|
uint32_t Chip_Clock_GetUSBPLLInClockRate(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return USB PLL output clock rate
|
||
|
|
* @return USB PLL output clock rate
|
||
|
|
*/
|
||
|
|
uint32_t Chip_Clock_GetUSBPLLOutClockRate(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return main clock rate
|
||
|
|
* @return main clock rate
|
||
|
|
*/
|
||
|
|
uint32_t Chip_Clock_GetMainClockRate(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return system clock rate
|
||
|
|
* @return system clock rate
|
||
|
|
*/
|
||
|
|
uint32_t Chip_Clock_GetSystemClockRate(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __CLOCK_11U6X_H_ */
|