2021-03-18 16:28:44 +07:00
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DEPS_SUBMODULES += hw/mcu/nxp
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2021-03-04 22:50:45 +07:00
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2019-05-14 18:34:57 +07:00
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CFLAGS += \
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2019-11-20 16:06:40 +07:00
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-flto \
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2019-05-14 18:34:57 +07:00
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-mthumb \
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-mabi=aapcs \
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-mcpu=cortex-m3 \
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-nostdlib \
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-DCORE_M3 \
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-D__USE_LPCOPEN \
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2019-09-11 11:55:16 +07:00
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-DCFG_EXAMPLE_MSC_READONLY \
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2019-09-03 13:25:36 +07:00
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-DCFG_TUSB_MCU=OPT_MCU_LPC13XX \
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2019-10-04 13:13:51 +07:00
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-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
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2019-05-14 18:34:57 +07:00
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-DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
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2019-09-06 15:06:04 +07:00
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# startup.c and lpc_types.h cause following errors
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2020-03-23 22:52:59 +07:00
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CFLAGS += -Wno-error=strict-prototypes
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2019-09-06 15:06:04 +07:00
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2019-11-11 11:51:51 +07:00
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MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx
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2019-09-09 12:39:58 +07:00
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2019-05-14 18:34:57 +07:00
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# All source paths should be relative to the top level.
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2020-03-07 17:49:30 +07:00
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LD_FILE = hw/bsp/$(BOARD)/lpc1347.ld
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2019-05-14 18:34:57 +07:00
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SRC_C += \
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2021-03-17 16:52:07 +07:00
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src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
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2019-09-09 12:39:58 +07:00
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$(MCU_DIR)/../gcc/cr_startup_lpc13xx.c \
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$(MCU_DIR)/src/chip_13xx.c \
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$(MCU_DIR)/src/clock_13xx.c \
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$(MCU_DIR)/src/gpio_13xx_1.c \
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$(MCU_DIR)/src/iocon_13xx.c \
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$(MCU_DIR)/src/sysctl_13xx.c \
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$(MCU_DIR)/src/sysinit_13xx.c
|
2019-05-14 18:34:57 +07:00
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|
INC += \
|
2019-09-09 12:39:58 +07:00
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|
$(TOP)/$(MCU_DIR)/inc
|
2019-05-14 18:34:57 +07:00
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM3
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# For flash-jlink target
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|
JLINK_DEVICE = LPC1347
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|
# flash using jlink
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|
flash: flash-jlink
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