151 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
		
		
			
		
	
	
			151 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
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								#ifndef __ARM32_H__
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								#define __ARM32_H__
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								#ifdef __cplusplus
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								extern "C" {
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								#endif
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								#include <stdint.h>
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								struct arm_regs_t {
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									uint32_t r[13];
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									uint32_t sp;
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									uint32_t lr;
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									uint32_t pc;
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									uint32_t cpsr;
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								};
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								static inline uint32_t arm32_read_p15_c1(void)
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								{
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									uint32_t value;
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									__asm__ __volatile__(
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										"mrc p15, 0, %0, c1, c0, 0"
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										: "=r" (value)
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										:
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										: "memory");
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									return value;
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								}
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								static inline void arm32_write_p15_c1(uint32_t value)
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								{
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									__asm__ __volatile__(
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										"mcr p15, 0, %0, c1, c0, 0"
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										:
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										: "r" (value)
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										: "memory");
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									arm32_read_p15_c1();
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								}
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								static inline void arm32_interrupt_enable(void)
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								{
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									uint32_t tmp;
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									__asm__ __volatile__(
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										"mrs %0, cpsr\n"
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										"bic %0, %0, #(1<<7)\n"
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										"msr cpsr_cxsf, %0"
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										: "=r" (tmp)
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										:
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										: "memory");
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								}
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								static inline void arm32_interrupt_disable(void)
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								{
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									uint32_t tmp;
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									__asm__ __volatile__(
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										"mrs %0, cpsr\n"
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										"orr %0, %0, #(1<<7)\n"
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										"msr cpsr_cxsf, %0"
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										: "=r" (tmp)
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										:
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										: "memory");
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								}
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								static inline void arm32_mmu_enable(void)
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								{
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									uint32_t value = arm32_read_p15_c1();
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									arm32_write_p15_c1(value | (1 << 0));
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								}
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								static inline void arm32_mmu_disable(void)
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								{
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									uint32_t value = arm32_read_p15_c1();
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									arm32_write_p15_c1(value & ~(1 << 0));
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								}
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								static inline void arm32_dcache_enable(void)
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								{
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									uint32_t value = arm32_read_p15_c1();
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									arm32_write_p15_c1(value | (1 << 2));
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								}
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								static inline void arm32_dcache_disable(void)
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								{
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									uint32_t value = arm32_read_p15_c1();
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									arm32_write_p15_c1(value & ~(1 << 2));
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								}
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								static inline void arm32_icache_enable(void)
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								{
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									uint32_t value = arm32_read_p15_c1();
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									arm32_write_p15_c1(value | (1 << 12));
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								}
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								static inline void arm32_icache_disable(void)
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								{
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									uint32_t value = arm32_read_p15_c1();
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									arm32_write_p15_c1(value & ~(1 << 12));
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								}
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								static inline uint32_t arm32_smp_processor_id(void)
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								{
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									uint32_t tmp;
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									__asm__ __volatile__(
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										"mrc p15,0,%0,c0,c0,5\n"
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										"and %0,%0,#0x3\n"
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										: "=r" (tmp)
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										:
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										: "memory");
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									return tmp;
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								}
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								static inline void arm32_ttb_set(uint32_t base)
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								{
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									__asm__ __volatile__(
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										"mcr p15, 0, %0, c2, c0, 0"
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										:
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										: "r" (base)
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										: "memory");
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								}
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								static inline void arm32_domain_set(uint32_t domain)
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								{
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									__asm__ __volatile__(
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										"mcr p15, 0, %0, c3, c0, 0"
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										:
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										: "r" (domain)
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										: "memory");
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								}
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								static inline void arm32_tlb_invalidate(void)
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								{
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									__asm__ __volatile__(
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										"mov r0, #0\n"
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										"mcr p15, 0, r0, c7, c10, 4\n"
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										"mcr p15, 0, r0, c8, c6, 0\n"
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										"mcr p15, 0, r0, c8, c5, 0\n"
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										:
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										:
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										: "r0");
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								}
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								#ifdef __cplusplus
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								}
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								#endif
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								#endif /* __ARM32_H__ */
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