303 lines
7.9 KiB
C
303 lines
7.9 KiB
C
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2023 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "tusb_option.h"
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#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
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#include "host/hcd.h"
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//--------------------------------------------------------------------+
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//
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//--------------------------------------------------------------------+
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// Command format is
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// Reg [7:3] | 0 [2] | Dir [1] | Ack [0]
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enum {
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CMDBYTE_WRITE = 0x02,
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};
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enum {
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RCVVFIFO_ADDR = 1u << 3, // 0x08
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SNDFIFO_ADDR = 2u << 3, // 0x10
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SUDFIFO_ADDR = 4u << 3, // 0x20
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RCVBC_ADDR = 6u << 3, // 0x30
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SNDBC_ADDR = 7u << 3, // 0x38
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USBIRQ_ADDR = 13u << 3, // 0x68
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USBIEN_ADDR = 14u << 3, // 0x70
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USBCTL_ADDR = 15u << 3, // 0x78
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CPUCTL_ADDR = 16u << 3, // 0x80
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PINCTL_ADDR = 17u << 3, // 0x88
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REVISION_ADDR = 18u << 3, // 0x90
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HIRQ_ADDR = 25u << 3, // 0xC8
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HIEN_ADDR = 26u << 3, // 0xD0
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MODE_ADDR = 27u << 3, // 0xD8
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PERADDR_ADDR = 28u << 3, // 0xE0
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HCTL_ADDR = 29u << 3, // 0xE8
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HXFR_ADDR = 30u << 3, // 0xF0
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HRSL_ADDR = 31u << 3, // 0xF8
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};
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enum {
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USBIRQ_OSCOK_IRQ = 1u << 0,
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USBIRQ_NOVBUS_IRQ = 1u << 5,
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USBIRQ_VBUS_IRQ = 1u << 6,
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};
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enum {
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USBCTL_PWRDOWN = 1u << 4,
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USBCTL_CHIPRES = 1u << 5,
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};
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enum {
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CPUCTL_IE = 1u << 0,
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CPUCTL_PULSEWID0 = 1u << 6,
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CPUCTL_PULSEWID1 = 1u << 7,
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};
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enum {
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PINCTL_GPXA = 1u << 0,
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PINCTL_GPXB = 1u << 1,
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PINCTL_POSINT = 1u << 2,
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PINCTL_INTLEVEL = 1u << 3,
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PINCTL_FDUPSPI = 1u << 4,
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};
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enum {
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HIRQ_BUSEVENT_IRQ = 1u << 0,
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HIRQ_RWU_IRQ = 1u << 1,
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HIRQ_RCVDAV_IRQ = 1u << 2,
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HIRQ_SNDBAV_IRQ = 1u << 3,
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HIRQ_SUSDN_IRQ = 1u << 4,
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HIRQ_CONDET_IRQ = 1u << 5,
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HIRQ_FRAME_IRQ = 1u << 6,
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HIRQ_HXFRDN_IRQ = 1u << 7,
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};
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enum {
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MODE_HOST = 1u << 0,
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MODE_LOWSPEED = 1u << 1,
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MODE_HUBPRE = 1u << 2,
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MODE_SOFKAENAB = 1u << 3,
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MODE_SEPIRQ = 1u << 4,
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MODE_DELAYISO = 1u << 5,
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MODE_DMPULLDN = 1u << 6,
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MODE_DPPULLDN = 1u << 7,
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};
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enum {
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HCTL_BUSRST = 1u << 1,
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HCTL_FRMRST = 1u << 2,
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HCTL_SAMPLEBUS = 1u << 3,
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HCTL_SIGRSM = 1u << 4,
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HCTL_RCVTOG0 = 1u << 5,
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HCTL_RCVTOG1 = 1u << 6,
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HCTL_SNDTOG0 = 1u << 7,
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HCTL_SNDTOG1 = 1u << 8,
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};
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enum {
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HXFR_EPNUM_MASK = 0x0f,
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HXFR_SETUP = 1u << 4,
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HXFR_OUT_NIN = 1u << 5,
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HXFR_ISO = 1u << 6,
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HXFR_HS = 1u << 7,
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};
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enum {
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HRSL_RESULT_MASK = 0x0f,
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HRSL_RCVTOGRD = 1u << 4,
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HRSL_SNDTOGRD = 1u << 5,
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HRSL_KSTATUS = 1u << 6,
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HRSL_JSTATUS = 1u << 7,
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};
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// API: SPI transfer with MAX3421E, must be implemented by application
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bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
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// return HIRQ register since we are in full-duplex mode
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static uint8_t reg_write(uint8_t reg, uint8_t data) {
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uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
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uint8_t rx_buf[2] = {0, 0};
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tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
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return rx_buf[0];
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}
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static uint8_t reg_read(uint8_t reg) {
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uint8_t tx_buf[2] = {reg, 0};
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uint8_t rx_buf[2] = {0, 0};
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return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2) ? rx_buf[1] : 0;
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}
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//--------------------------------------------------------------------+
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// Controller API
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//--------------------------------------------------------------------+
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// optional hcd configuration, called by tuh_configure()
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bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
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(void) rhport;
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(void) cfg_id;
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(void) cfg_param;
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return false;
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}
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// Initialize controller to host mode
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bool hcd_init(uint8_t rhport) {
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(void) rhport;
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// full duplex, interrupt level (should be configurable)
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reg_write(PINCTL_ADDR, PINCTL_FDUPSPI | PINCTL_INTLEVEL);
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// reset
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reg_write(USBCTL_ADDR, USBCTL_CHIPRES);
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reg_write(USBCTL_ADDR, 0);
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while( !(reg_read(USBIRQ_ADDR) & USBIRQ_OSCOK_IRQ) ) {
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// wait for oscillator to stabilize
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}
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// Mode: Host and DP/DM pull down
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reg_write(MODE_ADDR, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
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// Connection detection
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reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ /*| HIRQ_FRAME_IRQ */);
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return false;
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}
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// Interrupt Handler
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void hcd_int_handler(uint8_t rhport) {
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(void) rhport;
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}
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// Enable USB interrupt
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void hcd_int_enable (uint8_t rhport) {
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(void) rhport;
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}
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// Disable USB interrupt
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void hcd_int_disable(uint8_t rhport) {
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(void) rhport;
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}
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// Get frame number (1ms)
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uint32_t hcd_frame_number(uint8_t rhport) {
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(void) rhport;
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return 0;
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}
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//--------------------------------------------------------------------+
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// Port API
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//--------------------------------------------------------------------+
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// Get the current connect status of roothub port
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bool hcd_port_connect_status(uint8_t rhport) {
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(void) rhport;
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return false;
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}
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// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
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// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
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void hcd_port_reset(uint8_t rhport) {
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(void) rhport;
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}
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// Complete bus reset sequence, may be required by some controllers
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void hcd_port_reset_end(uint8_t rhport) {
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(void) rhport;
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}
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// Get port link speed
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tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
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(void) rhport;
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return TUSB_SPEED_FULL;
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}
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// HCD closes all opened endpoints belong to this device
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void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
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(void) rhport;
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(void) dev_addr;
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}
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//--------------------------------------------------------------------+
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// Endpoints API
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//--------------------------------------------------------------------+
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// Open an endpoint
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bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
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(void) rhport;
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(void) dev_addr;
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(void) ep_desc;
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return false;
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}
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// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
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bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
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(void) rhport;
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(void) dev_addr;
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(void) ep_addr;
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(void) buffer;
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(void) buflen;
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return false;
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}
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// Abort a queued transfer. Note: it can only abort transfer that has not been started
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// Return true if a queued transfer is aborted, false if there is no transfer to abort
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bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
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(void) rhport;
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(void) dev_addr;
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(void) ep_addr;
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return false;
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}
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// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
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bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
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(void) rhport;
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(void) dev_addr;
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(void) setup_packet;
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return false;
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}
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// clear stall, data toggle is also reset to DATA0
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bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
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(void) rhport;
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(void) dev_addr;
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(void) ep_addr;
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return false;
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}
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#endif
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