344 lines
14 KiB
C
344 lines
14 KiB
C
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/**********************************************************************
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* $Id$ lpc43xx_mcpwm.h 2011-06-02
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*//**
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* @file lpc43xx_mcpwm.h
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* @brief Contains all macro definitions and function prototypes
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* support for Motor Control PWM firmware library on lpc43xx
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* @version 1.0
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* @date 02. June. 2011
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2011, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors<EFBFBD>
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* relevant copyright in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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**********************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @defgroup MCPWM MCPWM (Motor Control PWM)
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* @ingroup LPC4300CMSIS_FwLib_Drivers
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* @{
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*/
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#ifndef lpc43xx_MCPWM_H_
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#define lpc43xx_MCPWM_H_
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/* Includes ------------------------------------------------------------------- */
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#include "LPC43xx.h"
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#include "lpc_types.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Private Macros ------------------------------------------------------------- */
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/** @defgroup MCPWM_Private_Macros MCPWM Private Macros
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* @{
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*/
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/** Edge aligned mode for channel in MCPWM */
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#define MCPWM_CHANNEL_EDGE_MODE ((uint32_t)(0))
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/** Center aligned mode for channel in MCPWM */
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#define MCPWM_CHANNEL_CENTER_MODE ((uint32_t)(1))
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/** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */
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#define MCPWM_CHANNEL_PASSIVE_LO ((uint32_t)(0))
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/** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */
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#define MCPWM_CHANNEL_PASSIVE_HI ((uint32_t)(1))
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/* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of
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* the six output pins under the control of the bits in this register */
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#define MCPWM_PATENT_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */
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#define MCPWM_PATENT_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */
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#define MCPWM_PATENT_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */
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#define MCPWM_PATENT_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */
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#define MCPWM_PATENT_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */
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#define MCPWM_PATENT_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */
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/* Interrupt type in MCPWM */
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/** Limit interrupt for channel (0) */
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#define MCPWM_INTFLAG_LIM0 MCPWM_INT_ILIM(0)
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/** Match interrupt for channel (0) */
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#define MCPWM_INTFLAG_MAT0 MCPWM_INT_IMAT(0)
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/** Capture interrupt for channel (0) */
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#define MCPWM_INTFLAG_CAP0 MCPWM_INT_ICAP(0)
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/** Limit interrupt for channel (1) */
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#define MCPWM_INTFLAG_LIM1 MCPWM_INT_ILIM(1)
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/** Match interrupt for channel (1) */
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#define MCPWM_INTFLAG_MAT1 MCPWM_INT_IMAT(1)
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/** Capture interrupt for channel (1) */
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#define MCPWM_INTFLAG_CAP1 MCPWM_INT_ICAP(1)
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/** Limit interrupt for channel (2) */
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#define MCPWM_INTFLAG_LIM2 MCPWM_INT_ILIM(2)
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/** Match interrupt for channel (2) */
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#define MCPWM_INTFLAG_MAT2 MCPWM_INT_IMAT(2)
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/** Capture interrupt for channel (2) */
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#define MCPWM_INTFLAG_CAP2 MCPWM_INT_ICAP(2)
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/** Fast abort interrupt */
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#define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT
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/*********************************************************************//**
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* Macro defines for MCPWM Control register
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**********************************************************************/
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/* MCPWM Control register, these macro definitions below can be applied for these
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* register type:
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* - MCPWM Control read address
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* - MCPWM Control set address
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* - MCPWM Control clear address
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*/
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/**< Stops/starts timer channel n */
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#define MCPWM_CON_RUN(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+0))) : (0))
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/**< Edge/center aligned operation for channel n */
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#define MCPWM_CON_CENTER(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+1))) : (0))
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/**< Select polarity of the MCOAn and MCOBn pin */
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#define MCPWM_CON_POLAR(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+2))) : (0))
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/**< Control the dead-time feature for channel n */
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#define MCPWM_CON_DTE(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+3))) : (0))
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/**< Enable/Disable update of functional register for channel n */
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#define MCPWM_CON_DISUP(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+4))) : (0))
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/**< Control the polarity for all 3 channels */
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#define MCPWM_CON_INVBDC ((uint32_t)(1<<29))
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/**< 3-phase AC mode select */
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#define MCPWM_CON_ACMODE ((uint32_t)(1<<30))
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/**< 3-phase DC mode select */
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#define MCPWM_CON_DCMODE (((uint32_t)1<<31))
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/*********************************************************************//**
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* Macro defines for MCPWM Capture Control register
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**********************************************************************/
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/* Capture Control register, these macro definitions below can be applied for these
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* register type:
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* - MCPWM Capture Control read address
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* - MCPWM Capture Control set address
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* - MCPWM Capture control clear address
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*/
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/** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */
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#define MCPWM_CAPCON_CAPMCI_RE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0))
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/** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */
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#define MCPWM_CAPCON_CAPMCI_FE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0))
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/** TC(n) is reset by channel (n) capture event */
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#define MCPWM_CAPCON_RT(n) (((n<=2)) ? ((uint32_t)(1<<(18+(n)))) : (0))
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/** Hardware noise filter: channel (n) capture events are delayed */
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#define MCPWM_CAPCON_HNFCAP(n) (((n<=2)) ? ((uint32_t)(1<<(21+(n)))) : (0))
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/*********************************************************************//**
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* Macro defines for MCPWM Interrupt register
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**********************************************************************/
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/* Interrupt registers, these macro definitions below can be applied for these
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* register type:
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* - MCPWM Interrupt Enable read address
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* - MCPWM Interrupt Enable set address
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* - MCPWM Interrupt Enable clear address
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* - MCPWM Interrupt Flags read address
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* - MCPWM Interrupt Flags set address
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* - MCPWM Interrupt Flags clear address
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*/
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/** Limit interrupt for channel (n) */
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#define MCPWM_INT_ILIM(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0))
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/** Match interrupt for channel (n) */
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#define MCPWM_INT_IMAT(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0))
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/** Capture interrupt for channel (n) */
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#define MCPWM_INT_ICAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0))
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/** Fast abort interrupt */
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#define MCPWM_INT_ABORT ((uint32_t)(1<<15))
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/*********************************************************************//**
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* Macro defines for MCPWM Count Control register
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**********************************************************************/
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/* MCPWM Count Control register, these macro definitions below can be applied for these
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* register type:
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* - MCPWM Count Control read address
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* - MCPWM Count Control set address
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* - MCPWM Count Control clear address
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*/
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/** Counter(tc) advances on a rising edge on MCI(mci) pin */
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#define MCPWM_CNTCON_TCMCI_RE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0))
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/** Counter(cnt) advances on a falling edge on MCI(mci) pin */
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#define MCPWM_CNTCON_TCMCI_FE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0))
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/** Channel (n) is in counter mode */
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#define MCPWM_CNTCON_CNTR(n) (((n<=2)) ? ((uint32_t)(1<<(29+n))) : (0))
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/*********************************************************************//**
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* Macro defines for MCPWM Dead-time register
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**********************************************************************/
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/** Dead time value x for channel n */
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#define MCPWM_DT(n,x) (((n<=2)) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0))
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/*********************************************************************//**
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* Macro defines for MCPWM Communication Pattern register
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**********************************************************************/
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#define MCPWM_CP_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */
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#define MCPWM_CP_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */
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#define MCPWM_CP_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */
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#define MCPWM_CP_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */
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#define MCPWM_CP_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */
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#define MCPWM_CP_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */
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/*********************************************************************//**
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* Macro defines for MCPWM Capture clear address register
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**********************************************************************/
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/** Clear the MCCAP (n) register */
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#define MCPWM_CAPCLR_CAP(n) (((n<=2)) ? ((uint32_t)(1<<n)) : (0))
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/**
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* @}
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*/
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/* Public Types --------------------------------------------------------------- */
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/** @defgroup MCPWM_Public_Types MCPWM Public Types
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* @{
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*/
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/*********************************************************************//**
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* @brief MCPWM enumeration
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**********************************************************************/
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/**
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* @brief MCPWM channel identifier definition
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*/
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typedef enum
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{
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MCPWM_CHANNEL_0 = 0, /**< MCPWM channel 0 */
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MCPWM_CHANNEL_1, /**< MCPWM channel 1 */
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MCPWM_CHANNEL_2 /**< MCPWM channel 2 */
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} en_MCPWM_Channel_Id;
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/*********************************************************************//**
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* @brief MCPWM structure definitions
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**********************************************************************/
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/**
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* @brief Motor Control PWM Channel Configuration structure type definition
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*/
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typedef struct {
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uint32_t channelType; /**< Edge/center aligned mode for this channel,
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should be:
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- MCPWM_CHANNEL_EDGE_MODE: Channel is in Edge mode
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- MCPWM_CHANNEL_CENTER_MODE: Channel is in Center mode
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*/
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uint32_t channelPolarity; /**< Polarity of the MCOA and MCOB pins, should be:
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- MCPWM_CHANNEL_PASSIVE_LO: Passive state is LOW, active state is HIGH
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- MCPWM_CHANNEL_PASSIVE_HI: Passive state is HIGH, active state is LOW
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*/
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uint32_t channelDeadtimeEnable; /**< Enable/Disable DeadTime function for channel, should be:
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- ENABLE.
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- DISABLE.
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*/
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uint32_t channelDeadtimeValue; /**< DeadTime value, should be less than 0x3FF */
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uint32_t channelUpdateEnable; /**< Enable/Disable updates of functional registers,
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should be:
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- ENABLE.
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- DISABLE.
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*/
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uint32_t channelTimercounterValue; /**< MCPWM Timer Counter value */
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uint32_t channelPeriodValue; /**< MCPWM Period value */
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uint32_t channelPulsewidthValue; /**< MCPWM Pulse Width value */
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} MCPWM_CHANNEL_CFG_Type;
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/**
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* @brief MCPWM Capture Configuration type definition
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*/
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typedef struct {
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uint32_t captureChannel; /**< Capture Channel Number, should be in range from 0 to 2 */
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uint32_t captureRising; /**< Enable/Disable Capture on Rising Edge event, should be:
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- ENABLE.
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- DISABLE.
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*/
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uint32_t captureFalling; /**< Enable/Disable Capture on Falling Edge event, should be:
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- ENABLE.
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- DISABLE.
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*/
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uint32_t timerReset; /**< Enable/Disable Timer reset function an capture, should be:
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- ENABLE.
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- DISABLE.
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*/
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uint32_t hnfEnable; /**< Enable/Disable Hardware noise filter function, should be:
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- ENABLE.
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- DISABLE.
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*/
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} MCPWM_CAPTURE_CFG_Type;
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/**
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* @brief MCPWM Count Control Configuration type definition
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*/
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typedef struct {
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uint32_t counterChannel; /**< Counter Channel Number, should be in range from 0 to 2 */
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uint32_t countRising; /**< Enable/Disable Capture on Rising Edge event, should be:
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- ENABLE.
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- DISABLE.
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*/
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uint32_t countFalling; /**< Enable/Disable Capture on Falling Edge event, should be:
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- ENABLE.
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- DISABLE.
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*/
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} MCPWM_COUNT_CFG_Type;
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/**
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* @}
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*/
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/* Public Functions ----------------------------------------------------------- */
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/** @defgroup MCPWM_Public_Functions MCPWM Public Functions
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* @{
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*/
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void MCPWM_Init(LPC_MCPWM_Type *MCPWMx);
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void MCPWM_ConfigChannel(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
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MCPWM_CHANNEL_CFG_Type * channelSetup);
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void MCPWM_WriteToShadow(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
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MCPWM_CHANNEL_CFG_Type *channelSetup);
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void MCPWM_ConfigCapture(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
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MCPWM_CAPTURE_CFG_Type *captureConfig);
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void MCPWM_ClearCapture(LPC_MCPWM_Type *MCPWMx, uint32_t captureChannel);
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uint32_t MCPWM_GetCapture(LPC_MCPWM_Type *MCPWMx, uint32_t captureChannel);
|
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|
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void MCPWM_CountConfig(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
|
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|
|
uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig);
|
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|
|
void MCPWM_Start(LPC_MCPWM_Type *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
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|
|
void MCPWM_Stop(LPC_MCPWM_Type *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
|
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|
|
void MCPWM_ACMode(LPC_MCPWM_Type *MCPWMx,uint32_t acMode);
|
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|
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void MCPWM_DCMode(LPC_MCPWM_Type *MCPWMx, uint32_t dcMode,
|
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|
|
uint32_t outputInvered, uint32_t outputPattern);
|
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|
|
void MCPWM_IntConfig(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType, FunctionalState NewState);
|
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|
|
void MCPWM_IntSet(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType);
|
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|
|
void MCPWM_IntClear(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType);
|
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|
|
FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType);
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|
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|
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/**
|
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|
|
* @}
|
|||
|
|
*/
|
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|
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|
|
#ifdef __cplusplus
|
|||
|
|
}
|
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|
|
#endif
|
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|
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|
|
#endif /* lpc43xx_MCPWM_H_ */
|
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|
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|
|
/**
|
|||
|
|
* @}
|
|||
|
|
*/
|
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